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Design and simulation of a standing wave oscillator based PLL
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
2016 (English)In: FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, ISSN 2095-9184, Vol. 17, no 3, 258-264 p.Article in journal (Refereed) PublishedText
Abstract [en]

A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9M complementary metal-oxide-semiconductor (CMOS) technology, and can be used directly in a high performance multi-core microprocessor.

Place, publisher, year, edition, pages
Zhejiang University , 2016. Vol. 17, no 3, 258-264 p.
Keyword [en]
Standing wave oscillator (SWO), Clock distribution, Phase locked loop (PLL), Varactor
National Category
Computer Science Software Engineering
Identifiers
URN: urn:nbn:se:kth:diva-185070DOI: 10.1631/FITEE.1500210ISI: 000372254100007ScopusID: 2-s2.0-84960368123OAI: oai:DiVA.org:kth-185070DiVA: diva2:920044
Note

QC 20160415

Available from: 2016-04-15 Created: 2016-04-11 Last updated: 2016-04-15Bibliographically approved

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Zheng, Li-rong
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Industrial and Medical ElectronicsVinnExcellence Center for Intelligence in Paper and Packaging, iPACK
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