Design and simulation of a standing wave oscillator based PLL
2016 (English)In: FRONTIERS OF INFORMATION TECHNOLOGY & ELECTRONIC ENGINEERING, ISSN 2095-9184, Vol. 17, no 3, 258-264 p.Article in journal (Refereed) PublishedText
A standing wave oscillator (SWO) is a perfect clock source which can be used to produce a high frequency clock signal with a low skew and high reliability. However, it is difficult to tune the SWO in a wide range of frequencies. We introduce a frequency tunable SWO which uses an inversion mode metal-oxide-semiconductor (IMOS) field-effect transistor as a varactor, and give the simulation results of the frequency tuning range and power dissipation. Based on the frequency tunable SWO, a new phase locked loop (PLL) architecture is presented. This PLL can be used not only as a clock source, but also as a clock distribution network to provide high quality clock signals. The PLL achieves an approximately 50% frequency tuning range when designed in Global Foundry 65 nm 1P9M complementary metal-oxide-semiconductor (CMOS) technology, and can be used directly in a high performance multi-core microprocessor.
Place, publisher, year, edition, pages
Zhejiang University , 2016. Vol. 17, no 3, 258-264 p.
Standing wave oscillator (SWO), Clock distribution, Phase locked loop (PLL), Varactor
Computer Science Software Engineering
IdentifiersURN: urn:nbn:se:kth:diva-185070DOI: 10.1631/FITEE.1500210ISI: 000372254100007ScopusID: 2-s2.0-84960368123OAI: oai:DiVA.org:kth-185070DiVA: diva2:920044
QC 201604152016-04-152016-04-112016-04-15Bibliographically approved