Physical Design Aware System Level Synthesis of Hardware
2015 (English)In: Proceedings - Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015, IEEE , 2015, 141-148 p.Conference paper (Refereed)
In spite of decades of research, only a small percentage of hardware is designed using high-level synthesis because of the large gap between the abstraction levels of standard cells and algorithmic level. We propose a grid-based regular physical design platform composed of large grain hardened building blocks called SiLago blocks. This platform is divided into regions which are specialized for different functionalities like computation, storage, system control, etc. The characterized micro-architectural operations of the SiLago platform serve as the interface to meet-in-the-middle high-level and system-level syntheses framework. This framework was used to generate three hardware macro instances, derived from SiLago platform for three applications from signal processing domain. Results show two orders of magnitude improvements in efficiency of the system-level design space exploration and synthesis time, with average loss in design quality of 18% for energy and 54% for area compared to the commercial SOC flow.
Place, publisher, year, edition, pages
IEEE , 2015. 141-148 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-185777DOI: 10.1109/SAMOS.2015.7363669ISI: 000380507900020ScopusID: 2-s2.0-84963655342OAI: oai:DiVA.org:kth-185777DiVA: diva2:923757
International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS) 2015, 19-23 July 2015
QC 201604292016-04-272016-04-272016-09-05Bibliographically approved