Atomic stream computation unit based on micro-thread level parallelism
2015 (English)In: IEEE 26th Application-specific Systems, Architectures and Processors (ASAP) 2015, IEEE , 2015, 25-29 p.Conference paper (Refereed)
The increasing demand for higher resolution of images and communication bandwidth requires the streaming applications to deal with ever increasing size of datasets. Further, with technology scaling the cost of moving data is reducing at a slower pace compared to the cost of computing. These trends have motivated the proposed micro-architectural reorganization of stream processors by dividing the stream computation into functional computation, address constraints computation and address generation and deploying independent, distributed micro-threads to implement them. This scheme is an alternative to parallelizing them at instruction level. The proposed scheme has two benefits: a more efficient sequencer logic and energy savings in address generation and transportation. These benefits are quantified for a set of streaming applications and show average percentage improvement of 39 in silicon efficiency of the sequencer logic and 23 in total computational efficiency.
Place, publisher, year, edition, pages
IEEE , 2015. 25-29 p.
Engineering and Technology
IdentifiersURN: urn:nbn:se:kth:diva-185779DOI: 10.1109/ASAP.2015.7245700ISI: 000380462200004ScopusID: 2-s2.0-84955568733ISBN: 978-147991924-6OAI: oai:DiVA.org:kth-185779DiVA: diva2:923769
IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2015
QC 201604292016-04-272016-04-272016-08-23Bibliographically approved