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Atomic stream computation unit based on micro-thread level parallelism
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0565-9376
2015 (English)In: IEEE 26th Application-specific Systems, Architectures and Processors (ASAP) 2015, IEEE , 2015, 25-29 p.Conference paper (Refereed)
Abstract [en]

The increasing demand for higher resolution of images and communication bandwidth requires the streaming applications to deal with ever increasing size of datasets. Further, with technology scaling the cost of moving data is reducing at a slower pace compared to the cost of computing. These trends have motivated the proposed micro-architectural reorganization of stream processors by dividing the stream computation into functional computation, address constraints computation and address generation and deploying independent, distributed micro-threads to implement them. This scheme is an alternative to parallelizing them at instruction level. The proposed scheme has two benefits: a more efficient sequencer logic and energy savings in address generation and transportation. These benefits are quantified for a set of streaming applications and show average percentage improvement of 39 in silicon efficiency of the sequencer logic and 23 in total computational efficiency.

Place, publisher, year, edition, pages
IEEE , 2015. 25-29 p.
National Category
Engineering and Technology
Identifiers
URN: urn:nbn:se:kth:diva-185779DOI: 10.1109/ASAP.2015.7245700ISI: 000380462200004ScopusID: 2-s2.0-84955568733ISBN: 978-147991924-6OAI: oai:DiVA.org:kth-185779DiVA: diva2:923769
Conference
IEEE 26th International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2015
Note

QC 20160429

Available from: 2016-04-27 Created: 2016-04-27 Last updated: 2016-08-23Bibliographically approved
In thesis
1. SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
Open this publication in new window or tab >>SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
2016 (English)Doctoral thesis, comprehensive summary (Other academic)
Place, publisher, year, edition, pages
Stockholm, Sweden: KTH Royal Institute of Technology, 2016. 56 p.
Series
, TRITA-ICT, 2016:05
Keyword
System Level Synthesis, High Level Synthesis, VLSI Design Methodology, Brain-like Computation, Neuromorphic Hardware, Address Generation, Thread Level Parallelism
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Research subject
Electrical Engineering
Identifiers
urn:nbn:se:kth:diva-185787 (URN)978-91-7595-900-9 (ISBN)
Public defence
2016-05-17, Sal B, Electrum 229, Isafjordsgatan 22, Kista, Stockholm, 20:24 (English)
Opponent
Supervisors
Note

QC 20160428

Available from: 2016-04-28 Created: 2016-04-27 Last updated: 2016-04-28Bibliographically approved

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