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TLM-RTL Equivalence Automated Verification Method and Tool Evaluation
KTH, School of Information and Communication Technology (ICT).
2015 (English)Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Abstract [en]

Raising the abstraction level, from Register Transfer Level (RTL) to Transaction Level Model (TLM), accelerates the design and simulation speed for Application Specific Integrated Circuit (ASIC) design in modern industry.

TLM can be used for reference model for RTL in verification process. TLM can also be used in High Level Synthesis (HLS) as the original model for RTL implementation. With the development of design automation tools for HLS by big Electronic Design Automation (EDA) vendors in recent years, it is now possible to generate RTL code from TLM directly by these fully automated industry commercial tools.

When it comes up to automated ASIC design, the functional consistency between TLM and RTL is the top task of the verification. Several methodologies are developed or under development in both industry and research area. Some automated verification tools may help to greatly reduce the verification effort.

This thesis report has proposed a flow for verifying the functional equivalence between TLM/SystemC/C code against its corresponding RTL code. The RTL code is the result of automated HLS from TLM. One commercial tool based on sequential equivalence checking (SEC) has been evaluated and its limitations have been assessed. The way to overcome those limitations by complementary verification methods has been scrutinized.

Place, publisher, year, edition, pages
2015. , 65 p.
TRITA-ICT, 2015:6
National Category
Computer and Information Science
URN: urn:nbn:se:kth:diva-186275OAI: diva2:926704
Educational program
Master of Science - System-on-Chip Design
Available from: 2016-05-13 Created: 2016-05-09 Last updated: 2016-05-13Bibliographically approved

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