Re-configurable hardware programming in a protocol processor unit
Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
Reconfigurable hardware architectures have been a research topic for many years. Programming such architectures requires manual low level coding or the design of custom compilers to generate the required configuration data for the architecture.
In general, a protocol processor processes the packets according to the protocol. There are number of protocols like Ethernet and CPRI to define how the data has to be sent and received between the source and destination points. Data packets can be processed using generic processors programmed in software, but hardware processing is always faster and energy efficient.
A compiler/mapper is investigated in this thesis work. The language application is developed using a parser generator tool called Antlr. The grammar is written in Extended Backus Naur Form (EBNF) and the corresponding language is used to describe the architecture and the protocols. The tool will generate a hardware model and its interconnections in SystemC TLM2.0 based on the protocol description. The hardware model is connected to Universal Verification Methodology (UVM) driver and functionality is verified by simulation. The Ethernet protocol is described using the developed language and the complete framework is verified.
Place, publisher, year, edition, pages
2015. , 86 p.
Computer and Information Science
IdentifiersURN: urn:nbn:se:kth:diva-186731OAI: oai:DiVA.org:kth-186731DiVA: diva2:927855