Interplay between hot carrier and bias stress components in single-layer double-gated graphene field-effect transistors
2015 (English)In: European Solid-State Device Research Conference, IEEE , 2015, 172-175 p.Conference paper (Refereed)Text
We examine the interplay between the degradations associated with the bias-temperature instability (BTI) and hot carrier degradation (HCD) in single-layer double-gated graphene field-effect transistors (GFETs). Depending on the polarity of the applied BTI stress, the HCD component acting in conjuction can either accelerate or compensate the degradation. The related phenomena are studied in detail at different temperatures. Our results show that the variations of the charged trap density and carrier mobility induced by both contributions are correlated. Moreover, the electron/hole mobility behaviour agrees with the previously reported attractive/repulsive scattering asymmetry. © 2015 IEEE.
Place, publisher, year, edition, pages
IEEE , 2015. 172-175 p.
Charge carrier processes, Degradation, Graphene, Logic gates, Performance evaluation, Stress, Transistors, Graphene transistors, Hot carriers, Reconfigurable hardware, Solid state devices, Stresses, Bias temperature instability, Charge carrier process, Charged traps, Graphene field effect transistor (GFETs), Graphene field-effect transistors, Hot carrier degradation, Single layer, Field effect transistors
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-186834DOI: 10.1109/ESSDERC.2015.7324741ISI: 000376615800041ScopusID: 2-s2.0-84959349571ISBN: 9781467371339OAI: oai:DiVA.org:kth-186834DiVA: diva2:928958
45th European Solid-State Device Research Conference, ESSDERC 2015, 14 September 2015 through 18 September 2015
QC 201605172016-05-172016-05-132016-06-20Bibliographically approved