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A formal, model-driven design flow for system simulation and multi-core implementation
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0002-2171-1528
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-4859-3100
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2015 (English)In: 2015 10th IEEE International Symposium on Industrial Embedded Systems, IEEE , 2015, 254-263 p.Conference paper (Refereed)Text
Abstract [en]

With the growing complexity of Real-Time Embedded Systems (RTES), there is a huge interest in using modeling languages such as the Unified Modeling Language (UML), and other Model-Driven Engineering (MDE) techniques targeting RTES system design. These approaches provide language abstractions for system design, allowing to focus on their relevant properties. Unfortunately, such approaches still suffer from several shortcomings including the lack of well-defined semantics. Therefore, it remains difficult to connect the MDE specification tools and the design tools that are based on formal grounds and well-defined semantics to perform analysis, validation or system synthesis for RTES. This paper presents a top-down RTES design flow aiming to reduce the gap between MDE and formal design approaches. We present the connection between a framework dedicated to the enrichment of modeling languages such as UML with formal semantics, a framework based on formal models of computation supporting validation by simulation, and a system synthesis tool targeting a flexible platform with well-defined execution services. Our purpose is to cover several system design phases from specification, simulation down to implementation on a platform. As a case study, a JPEG Encoder application was realized following the different design steps of the tool-chain.

Place, publisher, year, edition, pages
IEEE , 2015. 254-263 p.
National Category
Embedded Systems
Identifiers
URN: urn:nbn:se:kth:diva-187135DOI: 10.1109/SIES.2015.7185067ISI: 000380569800033ScopusID: 2-s2.0-84959543996ISBN: 978-1-4673-7711-9OAI: oai:DiVA.org:kth-187135DiVA: diva2:929219
Conference
10th IEEE International Symposium on Industrial Embedded Systems, SIES 2015; Siegen; Germany
Note

QC 20160518

Available from: 2016-05-18 Created: 2016-05-17 Last updated: 2016-09-06Bibliographically approved

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Attarzadeh-Niaki, Seyed HoseinRobino, FrancescoSander, IngoÖberg, Johnny
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ReferencesLink to record
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