Hardware-in-the-loop simulation of PV systems in micro-grids using SysML models
2015 (English)In: 2015 IEEE 16th Workshop on Control and Modeling for Power Electronics, IEEE , 2015Conference paper (Refereed)Text
This paper outlines a methodology for modeling photovoltaic systems in embedded hardware. This methodology uses the HiLeS platform to transform SysML models in Petri nets and generate VHDL code. The proposed methodology is intended for Hardware-in-the-Loop simulations of power converters and PV panels in microgrids. In addition, this methodology allows the design of MPPT controllers for their direct implementation in FPGA.
Place, publisher, year, edition, pages
IEEE , 2015.
Boost converter, FPGA, Hardware-in-the-Loop, MPPT, Petri net, Photovoltaic, SysML
IdentifiersURN: urn:nbn:se:kth:diva-187120DOI: 10.1109/COMPEL.2015.7236466ISI: 000380547800031ScopusID: 2-s2.0-84957921794ISBN: 978-146736847-6OAI: oai:DiVA.org:kth-187120DiVA: diva2:929588
16th IEEE Workshop on Control and Modeling for Power Electronics, COMPEL 2015; The University of British ColumbiaVancouver; Canada
QC 201605192016-05-192016-05-172016-09-14Bibliographically approved