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Bias-temperature instability on the back gate of single-layer double-gated graphene field-effect transistors
KTH, School of Information and Communication Technology (ICT).
KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.ORCID iD: 0000-0003-1234-6060
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2016 (English)In: Japanese Journal of Applied Physics, ISSN 0021-4922, E-ISSN 1347-4065, Vol. 55, no 4, 04EP03Article in journal (Refereed) PublishedText
Abstract [en]

We study the positive and negative bias-temperature instabilities (PBTI and NBTI) on the back gate of single-layer double-gated graphene fieldeffect transistors (GFETs). By analyzing the resulting degradation at different stress times and oxide fields we show that there is a significant asymmetry between PBTI and NBTI with respect to their dependences on these parameters. Finally, we compare the results obtained on the high-k top gate and SiO2 back gate of the same device and show that SiO2 gate is more stable with respect to BTI.

Place, publisher, year, edition, pages
Institute of Physics (IOP), 2016. Vol. 55, no 4, 04EP03
Keyword [en]
Graphene, Graphene transistors, Integrated circuits, Reconfigurable hardware, Back gates, Bias temperature instability, Graphene field-effect transistors, High- k, Negative bias temperature instability, Single layer, Stress time, Top gate
National Category
Physical Sciences
Identifiers
URN: urn:nbn:se:kth:diva-187205DOI: 10.7567/JJAP.55.04EP03ISI: 000373929400152ScopusID: 2-s2.0-84963650746OAI: oai:DiVA.org:kth-187205DiVA: diva2:929711
Conference
International Conference on Solid State Devices and Materials (SSDM), SEP 27-30, 2015, Sapporo, JAPAN
Funder
EU, European Research Council
Note

QC 20160519

Available from: 2016-05-19 Created: 2016-05-18 Last updated: 2016-06-08Bibliographically approved

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Smith, Anderson DavidVaziri, SamÖstling, Mikael
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ReferencesLink to record
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