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Adaptive fault simulation on many-core microprocessor systems
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
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2015 (English)In: Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, 151-154 p.Conference paper (Refereed)Text
Abstract [en]

Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platform, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach. © 2015 IEEE.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015. 151-154 p.
Keyword [en]
Fault Simulation, Intel Single-chip Cloud Computer, Load Balancing, Many-Core Systems, Cloud computing, Computer architecture, Defects, Fault tolerance, Memory architecture, Nanotechnology, Network management, Network-on-chip, Parallel processing systems, Resource allocation, VLSI circuits, Many core, Massive parallelism, Memory controller, Microprocessor systems, Parallel fault simulation, Runtime approach, Single-chip cloud computers, Distributed computer systems
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-186841DOI: 10.1109/DFT.2015.7315153ScopusID: 2-s2.0-84962798226ISBN: 9781509003129OAI: oai:DiVA.org:kth-186841DiVA: diva2:930324
Conference
28th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFTS 2015, 12 October 2015 through 14 October 2015
Note

QC 20160523

Available from: 2016-05-23 Created: 2016-05-13 Last updated: 2016-05-23Bibliographically approved

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Rahmani, AmirTenhunen, Hannu
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