Bias-temperature instability in single-layer graphene field-effect transistors: A reliability challengeShow others and affiliations
2014 (English)In: 2014 Silicon Nanoelectronics Workshop, SNW 2014, 2014Conference paper, Published paper (Refereed)
Resource type
Text
Abstract [en]
We present a detailed analysis of the bias-temperature instability (BTI) of single-layer graphene field-effect transistors (GFETs). We demonstrate that the dynamics can be systematically studied when the degradation is expressed in terms of a Dirac point voltage shift. Under these prerequisites it is possible to understand and benchmark both NBTI and PBTI using models previously developed for Si technologies. In particular, we show that the capture/emission time (CET) map approach can be also applied to GFETs and that recovery in GFETs follows the same universal relaxation trend as their Si counterparts. While the measured defect densities can still be considerably larger than those known from Si technology, the dynamics of BTI are in general comparable, allowing for quantitative benchmarking of the graphene/dielectric interface quality. © 2014 IEEE.
Place, publisher, year, edition, pages
2014.
Keywords [en]
Benchmarking, Graphene, Graphene transistors, Integrated circuits, Nanoelectronics, Silicon, Bias temperature instability, Dirac point voltages, Graphene field effect transistor (GFETs), Graphene field-effect transistors, Interface quality, MAP approach, Si technology, Single layer, Field effect transistors
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-186806DOI: 10.1109/SNW.2014.7348539Scopus ID: 2-s2.0-84963877879ISBN: 9781479956777 (print)OAI: oai:DiVA.org:kth-186806DiVA, id: diva2:930720
Conference
Silicon Nanoelectronics Workshop, SNW 2014, 8 June 2014 through 9 June 2014
Note
QC 20160525
2016-05-252016-05-132016-05-25Bibliographically approved