Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model
2015 (English)In: Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, 283-288 p.Conference paper (Refereed)Text
A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement. © 2015 IEEE.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015. 283-288 p.
AMBA bus, Complementary graph, Fault model, SoC, State graph, Buses, Graphic methods, Programmable logic controllers, System-on-chip, Extensive simulations, Graph-based techniques, High-level fault models, On chip communication, State graphs, Testing
IdentifiersURN: urn:nbn:se:kth:diva-186829DOI: 10.1109/MCSoC.2015.46ISI: 000380390400037ScopusID: 2-s2.0-84962733117ISBN: 9781479986699OAI: oai:DiVA.org:kth-186829DiVA: diva2:931391
9th IEEE International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015, 23 September 2015 through 25 September 2015
QC 201605272016-05-272016-05-132016-08-23Bibliographically approved