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Design and process issues of junction- and ferroelectric-field effect transistors in silicon carbide
KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
2003 (English)Doctoral thesis, comprehensive summary (Other scientific)
Abstract [en]

In today’s solid-state electronics, Si and SiO2 are thedominant materials used. However, new materials such as SiC orferroelectrics are required for some special applications sincesuperior characteristics can be achieved in electronic devices.The main objective of this work is the design, fabrication andcharacterization of different field effect transistors (FETs)including the new device structures referred to asjunction-gated metal-oxide-semiconductor FET (JMOSFET) andferroelectric-FETs (FeFET) as well as the conventionaljunction-FET (JFET).

Buried-gate JFETs with two different structures have beenfabricated in epitaxial layers of 4H-SiC using only 2- to3-mask steps. It has been shown that the trenching effectduring dry etching can induce static induction transistor(SIT)-like drain conduction for JFETs with small channelthickness (less than 0.5 micro-meter). The conduction mechanismin these JFETs is examined by the potential profiles fromtwo-dimensional numerical simulations. The trenching effect canbe reduced for JFETs using an oxide mask for dry etching withsloped etch profile (an angle of around 30o). It has also beendemonstrated that, by introducing a sacrificial oxidation (SO)step on the inductively coupled plasma (ICP)-etched surface ofSiC, the electrical properties of MOS capacitors and Ohmiccontacts can be effectively recovered after dry etch damage.The switching performance of JFETs in a test circuit has beeninvestigated with an inductive load and compared with numericaldevice simulations. A drain voltage rise/fall time of around 30ns has been observed for turn-off and turn-on. The results havebeen compared to numerical mixed-mode circuit simulations withfinite element structures.

To improve the high temperature stability and to lower theon-state resistance, we have designed the so-called‘JMOSFET’, which is a buried-gate JFET with anadditional MOS-gate on top. The JMOSFETs have shown thefeasibility for operation with a constant current level fromroom temperature all the way up to 300 oC by applying properbackside-gate voltage. An advantage of this device is theimproved channel transconductance (2.5 times), which resultsfrom accumulating the n-channel with the MOS gate.

In realizing ferroelectric devices above room temperatureand in severe environment, high temperature polarizationbehavior and retention of ferroelectric thin films are criticalfactors to explore. Thus SiC is one of the most attractivesemiconductor material for these applications. We have found anoptimum ferroelectric gate structure (using pulsed laserdeposition) of PZT/Al2O3/4H-SiC (large C-V memory window of 10V, low conductance<0.1 mS/cm2, tangent delta of 0.0007 at400kHz). Based on this structure, the nonvolatile operation ofFeFETs in SiC has been shown for the first timeat elevatedtemperatures. The transistor showed a memory effect from roomtemperature up to 200oC and stable transistor operation wasobserved up to 300 oC. The retention of the nonvolatile memorywas 2´104 seconds at 150 oC without applying bias on thegate.

Keywords:silicon carbide, ferroelectrics, PZT, fieldeffect transistor, FET, JFET, MOSFET, device simulation,capacitance-voltage measurements, pulsed laser deposition

Place, publisher, year, edition, pages
Kista: Mikroelektronik och informationsteknik , 2003. , 102 p.
Trita-EKT, ISSN 1650-8599 ; 2003:1
URN: urn:nbn:se:kth:diva-3526OAI: diva2:9341
Public defence
NR 20140805Available from: 2003-05-14 Created: 2003-05-14Bibliographically approved

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