Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Backlog bound analysis for virtual-channel routers
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.ORCID iD: 0000-0003-0061-3475
2015 (English)In: 2015 IEEE Computer Society Annual Symposium on VLSI, Institute of Electrical and Electronics Engineers (IEEE), 2015, Vol. 07, p. 422-427Conference paper, Published paper (Refereed)
Resource type
Text
Abstract [en]

Backlog bound analysis is crucial for predicting buffer sizing boundary in on-chip virtual-channel routers. However, the complicated resource contention among traffic flows makes the analysis difficult. Because conventional simulation-based approaches are generally incapable of investigating the worst-case scenarios for the backlog bounds, we propose a formal analysis technique. We identify basic buffer use scenarios and propose corresponding analysis models to formally deduce per-buffer backlog bound using network calculus. A topology independent analysis technique is developed to convey the per-buffer backlog bound analysis step by step. We further develop an algorithm to automate the analysis procedure with polynomial complexity. A case study shows how to apply the technique and the analytical bounds are tight.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015. Vol. 07, p. 422-427
Series
IEEE Computer Society Annual Symposium on VLSI, ISSN 2159-3469
Keywords [en]
Network calculus, Network on chip, Performance analysis, Calculations, Complex networks, Network-on-chip, VLSI circuits, Analytical bounds, Polynomial complexity, Resource contention, Simulation based approaches, Topology-independent, Worst case scenario, Routers
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-186850DOI: 10.1109/ISVLSI.2015.92ISI: 000377094100075Scopus ID: 2-s2.0-84957032253ISBN: 978-1-4799-8719-1 (print)OAI: oai:DiVA.org:kth-186850DiVA, id: diva2:936179
Conference
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015; Montpellier; France; 8 July 2015 through 10 July 2015
Note

QC 20160613

Available from: 2016-06-13 Created: 2016-05-13 Last updated: 2016-07-19Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Search in DiVA

By author/editor
Zhao, XueqianLu, Zhonghai
By organisation
Electronics and Embedded Systems
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
isbn
urn-nbn

Altmetric score

doi
isbn
urn-nbn
Total: 10 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf