Backlog bound analysis for virtual-channel routers
2015 (English)In: 2015 IEEE Computer Society Annual Symposium on VLSI, Institute of Electrical and Electronics Engineers (IEEE), 2015, Vol. 07, 422-427 p.Conference paper (Refereed)Text
Backlog bound analysis is crucial for predicting buffer sizing boundary in on-chip virtual-channel routers. However, the complicated resource contention among traffic flows makes the analysis difficult. Because conventional simulation-based approaches are generally incapable of investigating the worst-case scenarios for the backlog bounds, we propose a formal analysis technique. We identify basic buffer use scenarios and propose corresponding analysis models to formally deduce per-buffer backlog bound using network calculus. A topology independent analysis technique is developed to convey the per-buffer backlog bound analysis step by step. We further develop an algorithm to automate the analysis procedure with polynomial complexity. A case study shows how to apply the technique and the analytical bounds are tight.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015. Vol. 07, 422-427 p.
, IEEE Computer Society Annual Symposium on VLSI, ISSN 2159-3469
Network calculus, Network on chip, Performance analysis, Calculations, Complex networks, Network-on-chip, VLSI circuits, Analytical bounds, Polynomial complexity, Resource contention, Simulation based approaches, Topology-independent, Worst case scenario, Routers
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-186850DOI: 10.1109/ISVLSI.2015.92ISI: 000377094100075ScopusID: 2-s2.0-84957032253ISBN: 978-1-4799-8719-1OAI: oai:DiVA.org:kth-186850DiVA: diva2:936179
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015; Montpellier; France; 8 July 2015 through 10 July 2015
QC 201606132016-06-132016-05-132016-07-19Bibliographically approved