A 61 μa/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things
2016 (English)In: International System on Chip Conference, IEEE Computer Society, 2016, 235-239 p.Conference paper (Refereed)Text
This paper presents a SoC design that combines general purpose control and application-specific acceleration within a reconfigurable ASIP core for Internet-of-Things applications. Sufficient processing capability and re-configurability are provided by highly customizable data path and efficient sequence control loop. By fully utilizing the data path of proposed architecture, the processor significantly reduces >4X code size and offers superior performance compared with MSP430 and Atmega128 in FIR and Whetstone benchmarks. More than 10X speedup can be obtained in executing encryption algorithms by optimized micro-instructions without extra hardware accelerators. Fabricated in 0.18 μm CMOS, our SoC's energy efficiency beats most of the microcontrollers with a value as low as 61 μA/MHz.
Place, publisher, year, edition, pages
IEEE Computer Society, 2016. 235-239 p.
Application specific integrated circuits, Benchmarking, Energy efficiency, Internet, Internet of things, Programmable logic controllers, Reconfigurable hardware, Application specific, Application specific processors, Encryption algorithms, Hardware accelerators, Processing capability, Proposed architectures, Reconfigurable ASIP, Sequence control, System-on-chip
IdentifiersURN: urn:nbn:se:kth:diva-188251DOI: 10.1109/SOCC.2015.7406954ScopusID: 2-s2.0-84962374849ISBN: 9781467390934OAI: oai:DiVA.org:kth-188251DiVA: diva2:937440
28th IEEE International System on Chip Conference, SOCC 2015, 8 September 2015 through 11 September 2015
QC 201606152016-06-152016-06-092016-06-15Bibliographically approved