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Fault-resilient routing unit in NoCs
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
2016 (English)In: International System on Chip Conference, IEEE Computer Society, 2016, 164-169 p.Conference paper (Refereed)Text
Abstract [en]

With aggressive technology scaling in deep submicron era, burgeoning transistors make chips more susceptible to failures. It is inevitable that process variation is gradually becoming a crucial challenge in the IC design. In addition, aging leads to faults, shortening the lifetime of the circuits. Networks-on-chip also come to the problems caused by variations and aging, leading to degraded performance and erroneous behaviors. Faults may occur in numerous locations of the on-chip networks and once they occur in the control path, more severe effects such as deadlock and livelock are expected. In this paper, we present a fine-grained mechanism to tolerate faults in the routing computation units without disabling the faulty routers. By applying this mechanism, routing and packet-receiving services are separated. The faulty routing computation unit is replaced by a light-weight redundant circuit, providing static but reliable routing services. The other components in this router are still functional retaining the on-chip performance. Experimental results indicate that the on-chip network with the proposed mechanism is fault-tolerant when 14% of all routing computation modules are suffering from faults. The area overhead and power consumption of the proposed method is around 7.29% and 6.20% over the baseline approach.

Place, publisher, year, edition, pages
IEEE Computer Society, 2016. 164-169 p.
Keyword [en]
Fault Tolerance, Network-On-Chip, Redundant Routing Unit Design, Application specific integrated circuits, Distributed computer systems, Embedded systems, Program compilers, Programmable logic controllers, Reconfigurable hardware, Routers, Switching networks, VLSI circuits, Computation modules, Degraded performance, Networks on chips, On-chip networks, Process Variation, Redundant circuits, Technology scaling, Unit design, Network routing
National Category
Computer Engineering
URN: urn:nbn:se:kth:diva-188252DOI: 10.1109/SOCC.2015.7406933ISI: 000380400500033ScopusID: 2-s2.0-84962440830ISBN: 9781467390934OAI: diva2:937483
28th IEEE International System on Chip Conference, SOCC 2015, 8 September 2015 through 11 September 2015

QC 20160615

Available from: 2016-06-15 Created: 2016-06-09 Last updated: 2016-08-30Bibliographically approved

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Ebrahimi, Masoumeh
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Industrial and Medical Electronics
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