Dynamic application mapping algorithm for wireless network-on-chip
2015 (English)In: Proceedings - 23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, IEEE Press, 2015, 421-424 p.Conference paper (Refereed)Text
Because of high bandwidth, low latency and flexible topology configurations provided by wireless NoC, this emerging technology is gaining momentum to be a promising future on-chip interconnection paradigm. However, congestion occurrence in wireless routers reduces the benefit of high speed wireless links and significantly increases the network latency; therefore, in this paper, a Dynamic Application Mapping Algorithm (DAMA) is introduced for wireless NoCs in order to reduce both internal and external congestion. DAMA has three key steps: finding the first node to map, choosing the first task to be mapped onto the first node, and allocation of the remaining tasks to the remaining nodes. Simulation results show significant gain in the mapping cost functions compared to state-of-the-art works.
Place, publisher, year, edition, pages
IEEE Press, 2015. 421-424 p.
Congestion, Dynamic Application Mapping, Latency, Network-on-chip, Wireless network-on-chip, Algorithms, Conformal mapping, Cost functions, Mapping, Routers, Servers, VLSI circuits, Wireless interconnects, Wireless networks, Dynamic applications, Emerging technologies, Flexible topology, High speed wireless, Network latencies, On-chip interconnection
Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-187542DOI: 10.1109/PDP.2015.14ISI: 000380471500064ScopusID: 2-s2.0-84962905490ISBN: 9781479984909OAI: oai:DiVA.org:kth-187542DiVA: diva2:937930
23rd Euromicro International Conference on Parallel, Distributed, and Network-Based Processing, PDP 2015, 4 March 2015 through 6 March 2015
QC 201606162016-06-162016-05-252016-09-05Bibliographically approved