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Validating delay bounds in networks on chip: Tightness and pitfalls
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
2015 (English)In: Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, Institute of Electrical and Electronics Engineers (IEEE), 2015, 404-409 p.Conference paper (Refereed)Text
Abstract [en]

Analytical methods for estimating on-chip network performance can be very useful to accelerate and simplify the design process of Networks on Chip. However, in order to increase the confidence in these approaches it is fundamental to perform systematic studies that assess their potential. We present a methodical investigation on the tightness between analytical end-to-end delay bounds and worst-case simulation latencies in various scenarios. We first introduce our network calculus based analytical technique to derive per-flow communication delay bounds. Then, we examine the worst-case performance analysis process in NoCs outlining the major aspects that affect the tightness. Finally, experimental results confirm our deductions and allow us to provide general guidelines to avoid pitfalls in the validation process of analytical delay bounds.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015. 404-409 p.
Keyword [en]
Network calculus, Network-on-chip, Tightness, Calculations, VLSI circuits, Communication delays, End-to-end delay bounds, Networks on chips, Validation process, Worst-case performance analysis, Worst-case simulation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-186847DOI: 10.1109/ISVLSI.2015.111ISI: 000377094100072ScopusID: 2-s2.0-84957025169OAI: oai:DiVA.org:kth-186847DiVA: diva2:938078
Conference
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, 8 July 2015 through 10 July 2015
Note

QC 20160615

Available from: 2016-06-16 Created: 2016-05-13 Last updated: 2016-06-28Bibliographically approved

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