Change search
ReferencesLink to record
Permanent link

Direct link
Design of fault-tolerant and reliable networks-on-chip
Show others and affiliations
2015 (English)In: Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI, Institute of Electrical and Electronics Engineers (IEEE), 2015, 545-550 p.Conference paper (Refereed)Text
Abstract [en]

Networks-on-Chips (NoCs) are at the core of high performance multi-processor systems-on-chips. As the number of cores and sub-systems on chip grows, the size and complexity of NoCs increase as well. Due to the process variation, aging effects and soft-errors in current and expected future process generations, the probability of failure in the NoCs rises and has to be fought at all levels: circuit, architecture, and communication protocols. This paper discusses appropriate fault models for NoCs and their effects on the architecture and network levels. A method to design fault-tolerant NoCs comprising of techniques at the link level, the routing level, and the end-to-end level of the communication is presented. In addition, the proposed method offers an isolation technique where the computing cores are decoupled from the faults in the network. This technique avoids or at least attenuates the severe impacts of faults on the network performance and functionality. These point techniques are combined together to design fault-tolerant and reliable NoCs.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2015. 545-550 p.
Keyword [en]
Fault modelling, Fault-tolerant design flow, Networks-on-Chip, Complex networks, Design, Fault tolerance, Multiprocessing systems, Network architecture, Network-on-chip, Program compilers, Radiation hardening, Silicon on insulator technology, System-on-chip, Fault tolerant design, Isolation techniques, Multi processor systems, Networks on chips, Probability of failure, Process generation, Process Variation, Reliable Networks, Integrated circuit design
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:kth:diva-186846DOI: 10.1109/ISVLSI.2015.33ISI: 000377094100099ScopusID: 2-s2.0-84957009492OAI: oai:DiVA.org:kth-186846DiVA: diva2:938085
Conference
IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2015, 8 July 2015 through 10 July 2015
Note

QC 20160616

Available from: 2016-06-16 Created: 2016-05-13 Last updated: 2016-06-27Bibliographically approved

Open Access in DiVA

No full text

Other links

Publisher's full textScopusDesign of fault-tolerant and reliable networks-on-chip
Electrical Engineering, Electronic Engineering, Information Engineering

Search outside of DiVA

GoogleGoogle Scholar
The number of downloads is the sum of all downloads of full texts. It may include eg previous versions that are now no longer available

Altmetric score

Total: 6 hits
ReferencesLink to record
Permanent link

Direct link