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SysML Methodology for HIL Implementation of PV Models
Universidad de Los Andes, Colombia; Univ. de Toulouse, Univ. Paul Sabatier, France.
KTH, School of Electrical Engineering (EES), Electric Power Systems.
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2015 (English)In: 2015 17TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE'15 ECCE-EUROPE), IEEE , 2015Conference paper (Refereed)Text
Abstract [en]

This paper describes a methodology for implementing in FPGA models of photovoltaic panels for Hardware-in-the-Loop (HIL) and real-time simulations. The proposed methodology integrates numerical solutions, SysML diagrams and Petri nets for structural design and formal validation. In this study, photovoltaic cells have been modeled using the single diode circuit. The photovoltaic panel model is solved by the Newton-Raphson method, and the Lagrange remainder is employed to limit the iteration number. Results show suitable accuracy and performance of the proposed methodology.

Place, publisher, year, edition, pages
IEEE , 2015.
, European Conference on Power Electronics and Applications, ISSN 2325-0313
Keyword [en]
Photovoltaic panel, Hardware-in-the-Loop, FPGA, SysML, Petri net
National Category
Energy Engineering
URN: urn:nbn:se:kth:diva-189409DOI: 10.1109/EPE.2015.7309196ISI: 000377101801039ScopusID: 2-s2.0-84965074519ISBN: 978-9-0758-1523-8OAI: diva2:947186
17th European Conference on Power Electronics and Applications (EPE ECCE-Europe), SEP 08-10, 2015, Geneva, SWITZERLAND

QC 20160707

Available from: 2016-07-07 Created: 2016-07-04 Last updated: 2016-09-14Bibliographically approved

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Gutierrez, A.Chamorro, Harold Rene
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ReferencesLink to record
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