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SysML Methodology for HIL Implementation of PV Models
Universidad de Los Andes, Colombia; Univ. de Toulouse, Univ. Paul Sabatier, France.ORCID iD: 0000-0001-5417-5939
KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
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2015 (English)In: 2015 17TH EUROPEAN CONFERENCE ON POWER ELECTRONICS AND APPLICATIONS (EPE'15 ECCE-EUROPE), IEEE , 2015Conference paper, Published paper (Refereed)
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Text
Abstract [en]

This paper describes a methodology for implementing in FPGA models of photovoltaic panels for Hardware-in-the-Loop (HIL) and real-time simulations. The proposed methodology integrates numerical solutions, SysML diagrams and Petri nets for structural design and formal validation. In this study, photovoltaic cells have been modeled using the single diode circuit. The photovoltaic panel model is solved by the Newton-Raphson method, and the Lagrange remainder is employed to limit the iteration number. Results show suitable accuracy and performance of the proposed methodology.

Place, publisher, year, edition, pages
IEEE , 2015.
Series
European Conference on Power Electronics and Applications, ISSN 2325-0313
Keyword [en]
Photovoltaic panel, Hardware-in-the-Loop, FPGA, SysML, Petri net
National Category
Energy Engineering
Identifiers
URN: urn:nbn:se:kth:diva-189409DOI: 10.1109/EPE.2015.7309196ISI: 000377101801039Scopus ID: 2-s2.0-84965074519ISBN: 9789075815238 (print)OAI: oai:DiVA.org:kth-189409DiVA: diva2:947186
Conference
17th European Conference on Power Electronics and Applications (EPE ECCE-Europe), SEP 08-10, 2015, Geneva, SWITZERLAND
Note

QC 20160707

Available from: 2016-07-07 Created: 2016-07-04 Last updated: 2017-05-11Bibliographically approved

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CiteExportLink to record
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Citation style
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