Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology
2016 (English)In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 163, 49-54 p.Article in journal (Refereed) Published
In this study, the process integration of SiGe selective epitaxy on source/drain regions, for 16/14 nm nodes FinFET with high-k & metal gate has been presented. Selectively grown Si1-xGex (0.35 <= x <= 0.40) with boron concentration of 1 x 10(20) cm(-3) was used to elevate the source/drain of the transistors. The epi-quality, layer profile and strain amount of the selectively grown SiGe layers were also investigated by means of various characterizations. A series of prebaking experiments were performed for temperatures ranging from 740 to 825 degrees C in order to in situ clean the Si fins prior to the epitaxy. The results showed that the thermal budget needs to be limited to 780-800 degrees C in order to avoid any damages to the shape of Si fins but to remove the native oxide effectively which is essential for high epitaxial quality. The Ge content in SiGe layers on Si fins was determined from the strain measured directly by reciprocal space mappings using synchrotron radiation. Atomic layer deposition technique was applied to fill the gate trench with W using WF6 and B2H6 precursors. By such an AID approach, decent growth rate, low resistivity and excellent gap filling capability of W in pretty high aspect-ratio gate trench was realized. The as-fabricated FinFETs demonstrated decent electrical characteristics.
Place, publisher, year, edition, pages
Elsevier, 2016. Vol. 163, 49-54 p.
FinFET, SiGe selective epitaxy, RPCVD, High-k & metal gate
IdentifiersURN: urn:nbn:se:kth:diva-192720DOI: 10.1016/j.mee.2016.06.002ISI: 000381837300008OAI: oai:DiVA.org:kth-192720DiVA: diva2:974492
QC 201609262016-09-262016-09-202016-09-26Bibliographically approved