Influence of gate width on 50 nm gate length Si0.7Ge0.3 channel PMOSFETs
2003 (English)In: ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2003, 529-532 p.Conference paper (Refereed)
Compressively strained Si0.7Ge0.3 channel pMOSFETs were fabricated and the effective hole mobility was found to be 20-30% higher in the Si0.7Ge0.3 devices than in their Si counterparts. The g(m,) normalized to gate width, was found to increase strongly with decreasing gate width in the Si0.7Ge0.3 devices, a behavior that was not found in the Si devices. All the Si0.7Ge0.3 devices down to 50 nm gate length showed enhanced g. compared to the Si devices for gate widths <1 um. At L = 50 nm and W = 0.25 mum the Si0.7Ge0.3 devices exhibited increased g(m) and I-D of about 15 %, in saturation, compared to the Si devices. I-on was 286 muA/mum and I-off was 0.23 nA/mum at V-dd = 1.5 Vfor the Si0.7Ge0.3 device.
Place, publisher, year, edition, pages
2003. 529-532 p.
Other Electrical Engineering, Electronic Engineering, Information Engineering
IdentifiersURN: urn:nbn:se:kth:diva-5496ISI: 000189004800129OAI: oai:DiVA.org:kth-5496DiVA: diva2:9881
33rd European Solid-State Device Research Conference ESTORIL, PORTUGAL, SEP 16-18, 2003
QC 201009282006-03-212006-03-212010-09-28Bibliographically approved