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  • 1. Alty, S. R.
    et al.
    Jakobsson, A.
    Larsson, Erik G.
    KTH, Skolan för elektro- och systemteknik (EES), Kommunikationsteori.
    Efficient time-recursive implementation of matched filterbank spectral estimators2005Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 52, nr 3, s. 516-521Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper, we present a computationally efficient sliding window time updating of the Capon and amplitude and phase,estimation (APES) matched filterbank spectral estimators based on the time-variant displacement structure of the data covariance matrix. The presented algorithm forms a natural extension of the most computationally efficient algorithm to date, and offers a significant computational gain as compared to the computational complexity associated with the batch re-evaluation of the spectral estimates for each time-update. Furthermore, via simulations, the algorithm is found to be numerically superior to the time-updated spectral estimate formed from directly updating the data covariance matrix.

  • 2. Alzaher, H.
    et al.
    Ismail, Mohammed
    A CMOS fully balanced four-terminal floating nullor2002Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 49, nr 4, s. 413-424Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper presents design and implementation of a CMOS fully balanced realization of the four-terminal floating nullor (FTFN). The proposed fully balanced FTFN (FBFTFN) is an essential building block for implementing fully balanced architectures of both voltage and current-mode analog CMOS integrated circuits (ICs). A low-power class AB CMOS realization of the proposed circuit is fabricated in a 1.2-mum technology. The proposed circuit has numerous applications. Several applications including fully balanced amplifiers, filters, and sinusoidal oscillators are presented. All proposed design techniques and circuits are experimentally verified.

  • 3. Ben Dhaou, I.
    et al.
    Ismail, Mohammed
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Current mode, low-power, on-chip signaling in deep-submicron CMOS technology2003Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, nr 3, s. 397-406Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    qThis paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10% Experimental results on a set of benchmark signaling problems implemented in a 0.25-mum 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a twofold reduction in the power and a reduction of 1.4 times the area.

  • 4. Harnefors, L.
    et al.
    Holmberg, J.
    Signell, Svante
    Suppression of overflow limit cycles in LDI all-pass/lattice filters2000Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 47, nr 4, s. 594-598Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    In this paper it is shown that zero-input overflow limit cycles can be suppressed in a class of lossless digital integrator (LDI) all-pass filters. namely, that introduced in [1], This holds for any filter order, provided that saturation overflow characteristics are used at the input of each delay and for certain restrictions for the multiplier values. The results are shown to apply also to lossless digital differentiator (LDD) filters. The restrictions of multiplier values have the effect of excluding certain combinations of poles within the unit circle, most of which are in the left half circle where corresponding LDD filters can be used. Asymptotic stability can be guaranteed for all second-order LDI and LDD filters.

  • 5. Iannelli, L.
    et al.
    Johansson, K. H.
    Jönsson, Ulf T.
    KTH, Tidigare Institutioner                               , Matematik.
    Vasca, F.
    Analysis of periodically forced uncertain feedback systems2003Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, nr 2, s. 244-258Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Conditions for existence and stability of stationary periodic solutions of uncertain periodic systems are addressed in this paper. Existence and harmonic performance are studied using integral quadratic constraints (IQCs) defined on the space of square integrable periodic functions. Stability is investigated using IQCs defined on the usual space of square integrable functions. The analysis results in criteria formulated as affinely parameterized operator inequalities. Methods of convex optimization are used to find feasible parameters. Two applications will be discussed. The first is harmonic analysis of an electronic circuit and the second involves estimation of the amplitude of a periodic disturbance in a nonlinear control system.

  • 6. Iannelli, L.
    et al.
    Johansson, Karl H.
    KTH, Tidigare Institutioner, Signaler, sensorer och system.
    Jonsson, U. T.
    Vasca, F.
    Dither for smoothing relay feedback systems2003Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, nr 8, s. 1025-1035Artikel i tidskrift (Refereegranskat)
  • 7.
    Ninness, B.
    et al.
    University of Newcastle.
    Hjalmarsson, Håkan
    KTH, Tidigare Institutioner, Signaler, sensorer och system.
    Model structure and numerical properties of normal equations2001Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 48, nr 4, s. 425-437Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    There has been recent interest in using ortho-normalized forms of fixed denominator model structures for system identification, A key motivating factor in the employment of these forms is that of improved numerical properties. Namely, for white input, perfect conditioning of the least-squares normal equations is achieved by design. However, for the more usual case of colored input spectrum, it is not clear what the numerical conditioning properties should be in relation to simpler and perhaps more natural model structures. This paper provides theoretical and empirical evidence to argue that in fact, even though the orthonormal structures are only designed to provide perfect numerical conditioning for white input, they still provide improved conditioning for a wide variety of colored inputs.

  • 8. Strak, Adam
    et al.
    Gothenberg, Andreas
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Power-supply and substrate noise-induced timing jitter in nonoverlapping clock generation circuits2008Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, ISSN 1549-8328, Vol. 55, nr 4, s. 1041-1054Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    This paper describes a study of power-supply noise and substrate noise impact on the timing properties of two nonoverlapping clock generation circuits that are typically used in sigma-delta modulators. The constituent logic blocks of the clock generation circuits are also individually characterized where special attention has been put on the inverter whose behavior is fully described in mathematical terms. The analytical model is verified with SPICE using 0.35-mu m CMOS process parameters, and a reference simulation in 0.18 mu m is also presented showing the trend of technology downscaling. Furthermore, the nonoverlapping clock generation circuits are characterized in the 0.18-mu m process and the phenomenon of jitter peaking is described. Finally, all variations of connection configurations in the clock generation circuits are explored to reveal possible optimal configurations.

  • 9. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Kuntman, H. H.
    Robust design and yield enhancement of low-voltage CMOS analog integrated circuits2001Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 48, nr 4, s. 475-486Artikel i tidskrift (Refereegranskat)
    Abstract [en]

    Basic CMOS low-voltage analog cells are introduced and used in the design of low-voltage CMOS multipliers, A statistical design flow for enhancing the parametric functional yield of these low-voltage circuits, with the goal of achieving a robust performance,is described. The design flow is based on using the response surface methodology (RSM) and design of experiment (DOE) techniques as statistical VLSI design techniques together with the statistical MOS (SMOS) model. Offset and nonlinearity performances are statistically examined. The response surfaces show the trade-off between area and functional yield. Using these surface contours, the designer will be able to estimate the functional yield of the circuits before fabrication. The contours are also used in the statistical optimization of device sizes as they provide information regarding which transistor aspect ratios are to be altered to achieve a better functional yield.

  • 10. Wang, G. Y.
    et al.
    He, Sailing
    A quantitative study on detection and estimation of weak signals by using chaotic Duffing oscillators2003Ingår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, nr 7, s. 945-953Artikel i tidskrift (Refereegranskat)
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