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  • 1. Adiseno,
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Multiband high-linearity front-end receivers for wireless applications2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, no 1, p. 59-67Article in journal (Refereed)
    Abstract [en]

    In this paper, a modified front-end receiver configuration, which consists of an LNA and mixer suitable for zero-IF or low-IF receivers, is presented. The idea is to achieve a better linearity for receivers by combining circuit and system level solutions. Three circuit topologies, two in bipolar and one in CMOS technology, are presented in this paper with their simulation results. One of the bipolar topologies has been implemented and measurement results are presented. An IIP3 of up to +0.6 dBm of a combined bipolar LNA and mixer is achieved, depending on frequency of interest and with an acceptable noise figure performance at a current consumption of less than 13 mA from 5 V supply voltage in one circuit and 3 V supply voltage in the other one. An IIP3 up to +5 dBm is achieved for the CMOS topology at a lower overall gain and acceptable noise figure (14.4 mA and 3 V). All circuits presented in this paper are wideband circuits, suitable for area-efficient multiband receivers.

  • 2.
    Ahmad, Waqar
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Modeling of peak-to-peak core switching noise, output impedance, and decoupling capacitance along a vertical chain of power distribution TSV pairs2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 73, no 1, p. 311-328Article in journal (Refereed)
    Abstract [en]

    In this article we propose an efficient and accurate model to estimate peak-to-peak core switching noise, caused by simultaneous switching of logic loads along a vertical chain of power distribution TSV pairs in a 3D stack of dies interconnected through TSVs. The proposed model is accurate with only a 2–3% difference in peak-to-peak core switching noise as compared to the Ansoft Nexxim4.1 equivalent model. The proposed model is 3–4 times faster than Ansoft Nexxim4.1 and uses two times less memory as compared to the Ansoft Nexxim4.1 equivalent model. In this article we also thoroughly establish design guidelines for almost flat output impedance magnitude at each stage of a vertical chain of power distribution TSV pairs to realize a resonance free scenario over a wide operating frequency range. We also establish decoupling capacitance design guidelines based on the optimum output impedance and critically damped supply voltage for the core logic for each stage of a vertical chain of power distribution TSV pairs.

  • 3.
    Baghaei Nejad, Majid
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Shen, Meigen
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Koivisto, Tero
    Univ Turku, Dept Informat Technol.
    Peltonen, Teemu
    Univ Turku, Dept Informat Technol.
    Tjukanoff, Esa
    Univ Turku, Dept Informat Technol.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    UWB radio module design for wireless sensor networks2007In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 50, no 1, p. 47-57Article in journal (Refereed)
    Abstract [en]

    In this paper, we describe an impulse-based ultra wideband (UWB) radio system for wireless sensor network (WSN) applications. Different architectures have been studied for base station and sensor nodes. The base station node uses coherent UWB architecture because of the high performance and good sensitivity requirements. However, to meet complexity, power and cost constraints, the sensor module uses a novel non-coherent architecture that can autonomously detect the UWB signals. The radio modules include a transceiver block, a baseband processing unit and a power management block. The transceiver block includes a Gaussian pulse generator, a multiplier, an integrator and timing circuits. For long range applications, a wideband low noise amplifier (LNA) is included in the transceiver of the sensor module, whereas in short range applications it is simply eliminated to further reduce the power consumption. In order to verify the proposed system concept, circuit level implementation is studied using 1.5 V 0.18 mu m CMOS technology. Finally, the UWB radio modules have been designed for implementation in liquid-crystal-polymer (LCP) based System-on-Package (SOP) technology for low power, low cost and small size integration. A small low cost, double-slotted, Knight's helm antenna is embedded in the LCP substrate, which shows stable characterization and a return loss better than -10 dB over the UWB band.

  • 4.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Carlsson, Mats
    Hedenäs, Charlotta
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Flicker noise conversion in CMOS LC oscillators: capacitance modulation dominance and core device sizing2011In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 68, no 2, p. 145-154Article in journal (Refereed)
    Abstract [en]

    Flicker noise upconversion mechanisms in oscillators have been acquired in the literature, however their relative weights are still under investigation. It is desirable to find the dominant one, since a certain noise suppression method reduces one mechanism but may increase another. In this work, we propose a systematic simulation method to distinguish their relative impacts. The outcome indicates parasitic capacitance is the dominant factor for both tail 1/f noise and switch pair 1/f noise upconversions, implying to use small dimension core devices. Design guidelines on sizing devices are presented and two suppression techniques are compared. Two voltage-controlled oscillators (VCOs) with these suppression techniques are fabricated in a 0.18 mu m CMOS process, allowing us to compare their performance. The two VCOs can be Focused-Ion-Beam (FIB) trimmed to change the width of switch pair FETs. The fair comparison of measurement results among them verify the dominant role of parasitic capacitance in 1/f noise upconversion. The measurement results also confirm the design guidelines and demonstrate the difference of two suppression methods.

  • 5.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu R.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Modeling and simulation of spiral inductors in wafer level packaged RF/wireless chips2003In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, no 1, p. 39-47Article in journal (Refereed)
    Abstract [en]

    In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP) RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic) simulations. The performance of spiral inductors fabricated with various geometrical and technological parameters was analyzed. It is shown that Q (the quality factor) and f(res) (the self-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line, which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embedded components, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Through this study, optimal structures for such components are identified and guidelines for design and fabrications are derived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful to determine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a long time.

  • 6. Fayed, A. A.
    et al.
    Ismail, Mohammed
    A high speed, low voltage CMOS offset comparator2003In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 36, no 3, p. 267-272Article in journal (Refereed)
    Abstract [en]

    A high speed, low voltage offset comparator is presented. No common mode tracking circuit is used and the offset is added without compromising the high input impedance nature of the circuit. The circuit operates at 480 Mbps with 3.0-3.6 V and 1.6-2.0 V supplies and -40 to 125 degreesC temperature range on a typical 0.5 mum technology.

  • 7. Fayed, A.
    et al.
    Ismail, Mohammed
    A digital calibration algorithm for implementing accurate on-chip resistors2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 47, no 3, p. 259-272Article in journal (Refereed)
    Abstract [en]

    A digital calibration algorithm that provides a systematic method for implementing accurate integrated resistors without compromising linearity or noise performance is described. The technique uses a single external resistor as a reference to implement multiple, different valued integrated resistors without requiring any accurate reference voltage. The algorithm provides a method to calibrate several on-chip resistors without replicating the calibration circuit, and it can achieve an arbitrary accuracy limited only by the external resistor's accuracy and mismatch errors. Terminations for two high speed wire line transceivers are implemented using the algorithm and simulations and measurements results show adequate performance across process, temperature, and supply voltage.

  • 8. Gao, Y. C.
    et al.
    Wikner, J. J.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Design and analysis of an oversampling D/A converter in DMT-ADSL systems2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 3, p. 201-210Article in journal (Refereed)
    Abstract [en]

    Oversampling sigma-delta digital-to-analog converters are crucial building blocks for telecommunication applications. To reduce power consumption, lower oversampling ratios are preferred thus high-order digital sigma-delta modulators are needed to meet the dynamic performance requirements. This paper presents an oversampling DAC with 1.104 MHz signal bandwidth for DMT-ADSL application and focuses on the design issues of the high-order one-bit multiple feedback modulators (such as the stability problem, good inband SNDR performance, limit cycles, etc.). A new approach to obtain and optimize the stable feedback coefficients has been presented. From our analysis results it is found that the extra feedback coefficients and scaling coefficients in the modulator have non-negligible impact on the behavior of the limit cycles, and design guide for selecting the scaling coefficients is provided. Finally a 5th-order modulator with an oversampling ratio of 32 and 14-bit input has been implemented in a 0.6 mum 3.3 V CMOS process and integrated into the whole DAC chip.

  • 9. Gao, Y. H.
    et al.
    Jia, L. H.
    Isoaho, J.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A comparison design of comb decimators for sigma-delta analog-to-digital converters2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 22, no 1, p. 51-60Article in journal (Refereed)
    Abstract [en]

    This paper presents a comparison design of comb decimators based on the non-recursive algorithm and the recursive algorithm. Compared with the recursive algorithm, the main advantage of the non-recursive algorithm is its abilities of reducing power consumption and increasing circuit speed especially when the decimation ratio and filter order are high. Based on the non-recursive algorithm, a decimator with programmable filter orders (3rd, 4th and 5th), decimation ratios (8, 16, 32 and 64) and input bits (1 and 2 bits) has been implemented in a 0.6 mu m 3.3 V CMOS process. Its measured core power consumption is 44 mW at the oversampling rate of 25 MHz and its highest input data rate is 110 MHz.

  • 10. Gothenberg, A.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nonlinear quantization in low oversampling ratio sigma-delta noise shapers for RF applications2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, no 3, p. 193-206Article in journal (Refereed)
    Abstract [en]

    Baseband signal processing for current base stations or 3rd generation mobile systems will impose high bandwidth and high VLSI integration demand. Many of the desired integration aspects can be satisfied with sigma-delta converter front-ends. However, under the technology constraints there are simultaneous requirements for high sample rate and low oversampling ratio in order to achieve the desired baseband width. In this paper, we present system architecture results for the 4th-order cascaded noise shaper architectures to be used in baseband front-ends. We show that the cascaded structures with proper scaling will satisfy simultaneous demand on linearity (spurious free dynamic range) and high SQNR with low oversampling ratio based on usage of multibit quantizers outside the actual signal noise shaping path. We also present results for nonlinear quantization effects in low oversampling ratio cascaded noise shaper architectures. We analyse the effect of the non-linearity in both the A/D and D/A-block in quantization error quantizer path for the 4th-order cascaded topology and the design constraints associated to the performance of the used A/D and D/A structures. The performance requirement for the multi-bit quantizer for high SQNR is shown for the case of low oversampling ratios. The results show that non-uniform quantization around zero input are far more crucial to the SQNR than nonlinear quantization deviating from the ideal transfer function. As the key difference to standard multibit quantizers, no special error correction or error distribution schemes are required; the linearity requirements are satisfied with 0.2 LSB accuracy of the few bit quantizer. Finally, the performance of non-linear quantization using multitone test signals are also shown.

  • 11. Hwang, C.
    et al.
    Hyogo, A.
    Kim, H. S.
    Ismail, Mohammed
    Sekine, K.
    Low voltage high-speed CMOS square-law composite transistor cell2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 25, no 3, p. 347-349Article in journal (Refereed)
    Abstract [en]

    A new low voltage high-speed CMOS composite transistor is presented. It lowers supply voltage down to \V-t\ +2V(ds,sat) and considerably extends input voltage operating range and achieves high speed operation. As an application example, it is used in the design of a high-speed four quadrant analog multiplier. Simulations results using MOSIS 2 mu m N-well process with a 3 V supply are given.

  • 12. Jonsson, B. E.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A 3 V wideband CMOS switched-current A/D-converter suitable for time-interleaved operation2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 23, no 2, p. 127-139Article in journal (Refereed)
    Abstract [en]

    The simulated and measured performance of an experimental 10-b wideband CMOS A/D converter design is presented. Fully-differential first-generation switched-current circuits with common-mode feedforward were used to implement a 1.5-b/stage pipelined architecture in order to evaluate the switched-current technique for digital radio applications. With f(in) = 1.83 MHz, the measured spurious-free dynamic range (SFDR) is 60.3 dB and the signal-to-noise-and-distortion ratio (SNDR) = 46.5 dB at 3 MS/s. Although this 3 V design was fabricated in a standard digital 5 V, 0.8 mu m CMOS process, a high bandwidth was achieved. Since the ADC maintains an SNDR greater than or equal to 40 dB for input frequencies of more than 20 MHz, it has the highest input bandwidth reported for any CMOS switched-current A/D-converter implementation. Its sample rate can be increased by parallel, time-interleaved, operation. Measurement results are compared with the measured performance of other wideband switched-current A/D converters and found to be competitive also with respect to area and power efficiency.

  • 13. Larson, F.
    et al.
    Kascak, P.
    Ismail, Mohammed
    A BiCMOS wideband amplifier for the extraction of base spreading resistance with noise measurement techniques2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 24, no 3, p. 187-194Article in journal (Refereed)
    Abstract [en]

    This paper presents a BiCMOS wide band amplifier optimized for maximum sensitivity to noise introduced in the base spreading resistance. It was used to characterize the base spreading resistance of bipolar devices found in Orbit's low-noise, n-well BiCMOS process available through MOSIS. The base spreading resistance is extracted by measuring the output power spectral density of the aforementioned amplifier and isolating the amount caused by thermal noise in the base. The results give insight as to what noise sources are significant in this technology.

  • 14.
    Li, B. X.
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A second order multi-bit Sigma Delta modulator with single-bit feedback2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 38, no 1, p. 63-72Article in journal (Refereed)
    Abstract [en]

    Multi-bit Sigma Delta modulators suffer from the DAC non-linearity problem and often need complicated Dynamic Element Matching (DEM) circuits. Combining a multi-bit quantizer and a single-bit DAC eliminates the need of DEM circuits, simplifies the design, and reduces the power consumption. Using a digital circuit to compensate the truncation error caused by cutting the multi-bit feedback to single-bit, the structure can achieve the same noise transfer function as a conventional multi-bit modulator. One drawback is that the signal scaling in such a structure lowers the overall resolution. In this paper the influence of signal scaling is analyzed and a design example given. A second order 3-bit modulator is fabricated in 0.35 mum CMOS process, achieving 82 dB dynamic range at OSR 128 and a peak SNDR of 73.1 dB.

  • 15. Li, B. X.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Design of semi-uniform quantizers and their application in sigma delta A/D converters2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 41, no 03-feb, p. 253-267Article in journal (Refereed)
    Abstract [en]

    In this paper a new type of non-uniform quantizer, semi-uniform quantizer, is introduced. A k-bit semi-uniform quantizer uses the thresholds defined by a (k+1)-bit uniform quantizer and arranges them in such a way that small-amplitude inputs will be quantized by small quantization steps and large-amplitude inputs by large quantization steps. Therefore the total quantization error power could be reduced and the modulator's dynamic range could be increased by 1-bit. The condition for a semi-uniform quantizer to achieve a better performance than a uniform quantizer is analyzed and verified using a second order 3-bit sigma delta modulator prototype chip, fabricated in 0.35 mum CMOS process. At 32 x oversampling ratio the modulator achieves 81 dB dynamic range and 63.8 dB peak SNDR with 3-bit semi-uniform quantizer. With 3-bit uniform quantizer the dynamic range is 70 dB and the peak SNDR is 54.1 dB.

  • 16. Li, S. G.
    et al.
    Ismail, Mohammed
    A 7 GHz 1.5-V dual-modulus prescaler in 0.18 mu m copper-CMOS technology2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 32, no 1, p. 89-95Article in journal (Refereed)
    Abstract [en]

    A dual-modulus prescaler using True-Single-Phase-Clock (TSPC) logic is implemented in a 0.18 mum copper CMOS technology. With careful design and optimization the prescaler is able to operate at frequency up to 7.14 GHz at 1.5 V supply voltage. The high-speed operation is attributed to the adoption of the TSPC dynamic logic, and the all copper interconnect CMOS process which has much less interconnect parasitics than conventional aluminum technology. The design facilitates the implementation of a fully integrated RF CMOS phase-locked loop for applications in the 5.8 GHz ISM band such as wireless LAN.

  • 17. Park, Seok-Bae
    et al.
    Ismail, Mohammed
    DC offsets in direct conversion multistandard wireless receivers: Modeling and cancellation2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 2, p. 123-130Article in journal (Refereed)
    Abstract [en]

    To realize a high performance direct conversion receiver for multistandard wireless communications, the limiting factors in the direct conversion receiver should be identified and removed. In this paper, among many problems in direct conversion receivers, the DC offset problem is studied. The origins of the DC offset are summarized, and three self-mixing mechanisms generating the DC offset are modeled to better understand how the static (or time-invariant) and dynamic (or time-varying) DC offsets are produced from the mechanisms. A DC offset cancellation scheme consisting of a static DC offset canceller and a dynamic DC offset canceller is proposed and verified through simulations.

  • 18.
    Qin, Yajie
    et al.
    KTH, School of Information and Communication Technology (ICT), Communication Systems, CoS.
    Chen, Qihui
    Hong, Zhiliang
    Signell, Svante R.
    KTH, School of Information and Communication Technology (ICT), Communication Systems, CoS.
    A highly linear 1.2 V 12bit 5-45 MS/s CMOS pipelined ADC with CM-sensing-and-input-interchanged OTA sharing2012In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 72, no 1, p. 237-241Article in journal (Refereed)
    Abstract [en]

    A 1.2 V 12bit programmable pipelined ADC is presented and implemented in 0.13 mu m CMOS technology. A common-mode-sensing-and-input-interchanged OTA-sharing technique is proposed to address the non-resetting and successive-stage crosstalk issues in conventional OTA-sharing technique. Speed options of 5-45 MS/s are available with scalable power obtained by adjusting the bias currents for OTAs, comparators, and reference buffers, etc., or the global bias current. The measured signal-to-distortion-and-noise ratio is in range of 62.5-69.2 dB, and the peak spurious free dynamic range is 80.7 dB for all speed options, while the figure-of-merit is in the range of 0.26-0.49 pJ/conversion. The core area is 1.5 mm(2).

  • 19.
    Ramesh, Chithrupa
    et al.
    KTH, School of Electrical Engineering (EES), Automatic Control.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT).
    Skoglund, Mikael
    KTH, School of Electrical Engineering (EES), Communication Theory.
    System co-optimization in wireless receiver design with TrACS2008In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 57, no 1-2, p. 117-127Article in journal (Refereed)
    Abstract [en]

    System co-optimization of the analog receiver front end circuit and the digital baseband processing could enable receiver designs with lower power budgets, as the signal processing in the digital receiver is asymmetric across circuit topologies. This paper presents a simulation tool that could assist with such co-optimized designs. TrACS (Transceiver Architecture and Channel Simulator) is an RF/DSP co-simulator, capable of providing an application-specific system-level perspective to receiver design. The simulator is especially relevant in the context of energy-constrained wireless sensor node design, where the simulator's system perspective determines the compatibility of circuit topologies, modulation techniques and synchronization methods for various wireless scenarios. A few case studies are presented, which illustrate co-optimization of a ZigBEE receiver using TrACS.

  • 20. Ravindran, A.
    et al.
    Vidal, E.
    Yoo, S. J.
    Ramarao, K.
    Ismail, Mohammed
    A differential CMOS current-mode variable gain amplifier with digital dB-linear gain control2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 38, no 03-feb, p. 161-174Article in journal (Refereed)
    Abstract [en]

    A novel CMOS variable gain amplifier operating on current signals with a dB-linear gain control is presented. The gain control is achieved by multiplying a digitally synthesized exponentially varying control current signal by a differential input signal in the current domain. A current amplifier at the output sets the gain to the desired level. Current-mode operation allows for a reduced supply voltage by minimizing the voltage swing at the low impedance nodes of the circuit. Multiple circuit realizations for various blocks are presented allowing for designs meeting different constraints. Experimental realization of the variable gain amplifier shows the validity of the presented approach.

  • 21.
    Rodriguez, Saul
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Atallah, Jad G.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    ARCHER: an automated RF-IC Rx front-end circuit design tool2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 58, no 3, p. 255-270Article in journal (Refereed)
    Abstract [en]

    This paper presents a tool capable of automatically compiling the circuit of a direct-conversion receiver at the schematics level based on system specifications that include the frequency of operation, gain, noise figure, IIP2 and IIP3 linearity. The front-end of a direct-conversion receiver is built using inductive source degeneration (LSD) LNA and double-balanced source-degenerated Gilbert Cell mixers with charge injection. The tool uses power constrained noise and linearity optimization vector-space algorithms that automatically size the transistors, passive components, and find the optimum biasing points. The solution generated by the tool is automatically read by Agilent ADS where the blocks are easily fine-tuned and validated before layout. Case studies involving WiMAX, UMTS, GSM, Bluetooth and WLAN are presented to reveal the capabilities of the tool in reducing the design time.

  • 22.
    Rodríguez de Llera González, Delia
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A behavioral-based multi-agent optimization algorithm for system level radio design2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 61, no 1, p. 35-46Article in journal (Refereed)
    Abstract [en]

    This paper introduces a multi-agent behavioral-based optimization algorithm for system level radio design. Making multi-standard wireless communication receivers that meet their specs while keeping the requirements of the individual blocks as relaxed as possible is the goal of this algorithm. In order to achieve this goal a "divide and conquer" approach is proposed. Different agents focus on different objectives that are pursued in parallel. Agents adopt different behaviors depending on the status of the environment and their interaction with other agents. Agents are cooperative by default as they try to meet their spec without making changes that affect other agents. However, more aggressive behaviors that lead to global changes can be adopted when needed. The interaction between these simple entities yields an emergent behavior able to deal smoothly with the complexity of the problem at hand.

  • 23.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Borodenkov, A.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A triple-mode sigma-delta modulator for multi-standard wireless radio receivers2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 47, no 2, p. 113-124Article in journal (Refereed)
    Abstract [en]

    A 1.8 V sigma-delta modulator with a 4 bit quantizer has been designed for GSM/WCDMA/WLAN receivers in a 0.18 um CMOS process. The modulator makes use of low-distortion sigma-delta modulator architecture and Pseudo-Data-Weighted-Averaging technique to attain high linearity over a wide bandwidth. Power dissipation is minimized by optimizing the architecture and by a careful design of analog circuitry. In GSM mode, the modulator achieves 96/104 dB peak SNR/SFDR over 100 kHz bandwidth and dissipates 18 mW at a sampling frequency of 32 MHz. The modulator achieves 92/68 dB peak SFDR and 77/54 dB peak SNR over a 2 MHz/10 MHz bandwidth and dissipates 23/39 mW at a sampling frequency of 64 MHz/160 MHz in WCDMA/WLAN.

  • 24.
    Rusu, Ana
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Guest editorial: advanced design techniques for wireless communications2009In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 58, no 3, p. 179-181Article in journal (Other academic)
  • 25. Shi, C. L.
    et al.
    Wu, Y.
    Lin, C. H.
    Ismail, Mohammed
    Design and power optimization of high-speed pipeline ADC for wideband CDMA applications2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 26, no 3, p. 229-238Article in journal (Refereed)
    Abstract [en]

    This paper presents a 7-bit 64 MS/s pipeline A/D converter suitable for wideband CDMA applications. Targeting at achieving low power dissipation at high speed, techniques such as digital correction and optimal scaling of capacitor value have been employed. Switched-Opamp technique is used to further reduce power consumption. This ADC is implemented in 0.5 mum standard CMOS process. It operates from a single 3 V supply, and dissipates only 31 mW at 64 MS/s.

  • 26.
    Strak, Adam
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Gothenberg, Andreas
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Analysis of clock jitter effects in wideband sigma-delta modulators for RF-applications2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 41, no 03-feb, p. 223-236Article in journal (Refereed)
    Abstract [en]

    This paper presents a theoretical overview and analysis of clock jitter in a switched capacitor (SC) Sigma-Delta (SigmaDelta) Analog-to-Digital Converter ( ADC). We start by defining three different types of jitter effects and proceed to analyze their impact, both mathematically and by simulations. The main jitter assumption throughout this analysis is that it is stochastic white Gaussian noise. Using this assumption, the SigmaDelta performance is characterized in terms of Signal-to-Jitter-Noise-Ratio (SJNR) for each jitter effect. Non-uniform sampling effects have, to some extent, been characterized in litterature ( S. R. Norsworthy, R. Schreier and G. C. Temes, Delta-Sigma Data Converters - Theory, Design and Simulation, IEEE Press, NewJersey, 1997). However, varying phase-length effects are also a main focus in this work since they can have a significant impact on the total ADC performance depending on settling accuracy and characteristic. Furthermore, because SC circuits usually operate on a two-phase clock, jitter may give rise to a secondary effect, phase overlap, which does not appear when dealing with a single-phase clock. This effect severely degrades the resolution of a SigmaDelta and therefore a thorough understanding of the interaction of jitter on the two phases is necessary.

  • 27. Tang, Y. W.
    et al.
    Aktas, A.
    Ismail, Mohammed
    Bibyk, S.
    A high-speed low-power divide-by-15/16 dual modulus prescaler in 0.6 mu m CMOS2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 28, no 2, p. 195-200Article in journal (Refereed)
    Abstract [en]

    A new high-speed low-power dual modulus prescaler (DMP) topology is proposed. In this DMP, the synchronous part is designed as a divide-by-3/4 divider using a state-selection scheme. Compared with the conventional divide-by-4/5 divider, it has a higher speed by eliminating the NAND-gate introduced critical path delay, as well as a lower power consumption by minimizing the number of full-speed D-type flip-flops (DFF's) required. Based on this topology, a divide-by-15/16 DMP is implemented in the 0.6 mum standard CMOS process. Simulation result shows that a maximum operating frequency of 2.15 GHz is obtained at 3.3 V supply with a power consumption of 11.6 mW. The circuit can operate above 3 GHz with 5 V supply and down to 1.5 V supply voltage with 570 MHz input frequency.

  • 28.
    Tao, Sha
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A 60 GHz receiver front-end in 65 nm CMOS2011In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 67, no 1, p. 61-71Article in journal (Refereed)
    Abstract [en]

    In the past few years, the mm-wave silicon, especially 60 GHz CMOS design has experienced a transition from an obscure topic to a research hot spot. This paper presents the design of a 60 GHz receiver front-end using 65 nm CMOS technology. Initially, a heterodyne receiver front-end architecture is presented to exploit its possible compatibility with legacy systems. In order to implement the front-end, an EM simulation based methodology and the corresponding design flow are proposed. A transistor EM model, using existing compact models as core, is developed to account for the parasitic elements due to wiring stacks. A spiral inductor lumped model, based on S-parameter data from EM simulation is also derived. After the device modeling efforts, a single-stage LNA and a single-gate mixer are designed using 65 nm CMOS technology. They are characterized by EM co-simulation, and compared with the state-of-the-art. After integration, the simulated front-end achieves a conversion gain of 11.9 dB and an overall SSB noise figure of 8.2 dB, with an input return loss of -13.7 dB. It consumes 6.1 mW DC power, and its layout occupies a die area of 0.33 mm x 0.44 mm.

  • 29. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Statistical design of a 10 bit current division network2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 29, no 3, p. 221-229Article in journal (Refereed)
    Abstract [en]

    The statistical design of the 10 bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in the circuit is provided. Optimization of transistor W and L values, and yield enhancement are demonstrated. The circuit is fabricated through the MOSIS 2 mum process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.

  • 30. Tarim, T. B.
    et al.
    Ismail, Mohammed
    Statistical design of the four-MOSFET structure2001In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 28, no 1, p. 115-121Article in journal (Refereed)
    Abstract [en]

    The statistical design of the four-MOSFET structure is presented in this paper. The quantitative measure of the effect of mismatch between the four transistors on nonlinearity and offset current is provided through contours. Statistical optimization of the transistor W and L values is demonstrated. The four-MOSFET structure was fabricated through the MOSIS 2 mum process using MOS transistor Level-3 model parameters. Experimental results are included in the paper.

  • 31. Tarim, T. B.
    et al.
    Kuntman, H. H.
    Ismail, Mohammed
    Statistical design of low power square-law CMOS cells for high yield2000In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 23, no 3, p. 237-248Article in journal (Refereed)
    Abstract [en]

    A robust design of low voltage low power square law CMOS composite cells using statistical VLSI design techniques is presented. Since random device/process variations do not scale down with feature size or supply voltage, the statistical design of low voltage circuits is essential in order to keep functional yields of low voltage circuits at levels that are competitive and cost effective. The Response Surface Methodology and Design of Experiment techniques were used as statistical techniques. This article shows that statistical techniques will result in area/layout optimization which will enhance functional yield of low voltage analog ICs.

  • 32. Wu, Y.
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A SiGeHBT translinear harmonic mixer2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 31, no 1, p. 65-67Article in journal (Refereed)
    Abstract [en]

    A novel even-order harmonic mixer is proposed. Based on the translinear loop of BJT/HBTs, frequency doubling and single-to-differential conversion circuits have been employed in the design of harmonic mixer. The proposed mixer has been verified in a SiGe HBT process by SpectreRF simulations.

  • 33. Wu, Y.
    et al.
    Shi, C. L.
    Ding, X. H.
    Ismail, Mohammed
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Design of CMOS VHF/RF biquadratic filters2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 33, no 3, p. 239-248Article in journal (Refereed)
    Abstract [en]

    In this paper, a class of CMOS biquadratic filter suitable to work at VHF/RF frequency range is presented. The proposed circuit has a simple structure which is analyzed and designed according to a universal G(m)-C biquad filter. Simulation and experimental results show that these filters can work in GHz range and have wide tuning range.

  • 34. Younus, M. D. I.
    et al.
    Ismail, Mohammed
    Phase calibration technique for mismatch optimization in image-reject receivers2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 46, no 2, p. 165-168Article in journal (Refereed)
    Abstract [en]

    This paper presents phase calibration technique without using any external tone for weaver image-reject receiver. Error signal (phase mismatch information) is generated using a simple algorithm and this signal is used for mismatch elimination. Calibration system has been implemented using simulink which shows an image rejection ratio of 59.5 dB can be achieved for RF signal operating at 1.8 GHz.

  • 35. Zhang, Ling
    et al.
    Kim, Hyung Joon
    Nadig, Vinay
    Ismail, Mohammed
    A 1.8 V tri-mode Sigma Delta modulator for GSM/WCDMA/WLAN wireless receiver2006In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 49, no 3, p. 323-341Article in journal (Refereed)
    Abstract [en]

    The next generation of cellular systems will be increasingly similar to a data communication system. Not only will it transfer voice and multimedia data, it will also be integrated with WLAN to access Internet whenever possible. Thus these cellular systems need highly integrated multi-standard receivers. The design of the A/D converter in such receivers is a big challenge. A GSM/WCDMA/WLAN tri-mode receiver is first designed on the system level. A reconfigurable Sigma Delta modulator, which is suitable for GSM/WCDMA/WLAN receiver, is then proposed in this paper. According to the different signal bandwidth and Dynamic Range (DR) specifications, this Sigma Delta modulator is reconfigured to achieve the required dynamic range with less power consumption. The prototype is implemented in TSMC 0.18-mu m CMOS process with 1.8 V power supply. The circuit achieves signal-to-noise-and-distortion-ratio of 82 dB for GSM, 75 dB for WCDMA and 58 dB for WLAN.

  • 36.
    Zheng, Li-Rong
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Design and analysis of power integrity in deep submicron system-on-chip circuits2002In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 30, no 1, p. 15-29Article in journal (Refereed)
    Abstract [en]

    This paper proposes a new design methodology and new models for power integrity analysis in deep submicron system-on-chip circuit design. The placement plan and interconnect plan are the first design steps, preceding a priori signal and power integrity estimations. The initial power distribution is refined progressively from early mode to final placement and layout. In order to improve accuracy and efficiency in early stage estimates, a multilevel dynamic interconnect model and a fast power distribution model are employed, which consequently result in a drastic reduction of the number of iterations through the design cycle. HSPICE simulations verify the efficiency and the accuracy of the method. Finally, some noise-reduced power distribution techniques such as self-decoupling and area array power/ground pin distribution are discussed, and measurement result for effective power distribution is presented.

1 - 36 of 36
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