Change search
Refine search result
1 - 49 of 49
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the 'Create feeds' function.
  • 1. Chacinski, Marek
    et al.
    Westergren, Urban
    KTH, School of Information and Communication Technology (ICT), Optics and Photonics.
    Stoltz, Bjoern
    Thylén, Lars
    KTH, School of Information and Communication Technology (ICT), Optics and Photonics.
    Monolithically Integrated DFB-EA for 100 Gb/s Ethernet2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 12, p. 1312-1314Article in journal (Refereed)
    Abstract [en]

    The world's first monolithically integrated distributed feedback laser and electroabsorption (EA) modulator with an expected >= 100 GHz -3 dBe bandwidth suitable for 100 Gb/s operation with on-off keying is presented. The design of the EA modulator uses a traveling-wave structure with three active segments and a total active length of 180 mu m resulting in similar to 2.5 V peak-to-peak drive voltage for 10 dB optical extinction ratio and low electrical reflection.

  • 2. Chacinski, Marek
    et al.
    Westergren, Urban
    KTH, School of Information and Communication Technology (ICT), Optics and Photonics (Closed 20120101), Photonics (Closed 20120101).
    Willén, Bo
    Stoltz, Björn
    Thylén, Lars
    KTH, School of Information and Communication Technology (ICT), Optics and Photonics (Closed 20120101).
    Electroabsorption Modulators Suitable for 100-Gb/s Ethernet2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 9, p. 1014-1016Article in journal (Refereed)
    Abstract [en]

    The design of a traveling-wave electroabsorption modulator (TWEAM) has been improved to decrease the drive voltage. The absorption layer was optimized and together with a novel segmentation of microwave design was introduced to increase the active modulator length. The resulting -3-dBe bandwidth of fabricated devices was estimated to be 99 GHz. Extinction ratios of 10 dB back-to-back and 6.7 dB after transmission over 2.2-km long fiber were measured with an incident drive voltage of only 2 V peak to peak. This TWEAM performance is believed to constitute a new state of the art for modulators suitable for 100-Gb/s Ethernet with on-off keying.

  • 3.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Danielsson, Erik
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schöner, Adolf
    Acreo AB, Stockholm .
    Geometrical effects in high current gain 1100-V 4H-SiC BJTs2005In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 26, no 10, p. 743-745Article in journal (Refereed)
    Abstract [en]

    This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain beta = 64 and a breakdown voltage of 1100 V. The high beta value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The BJTs show a clear emitter-size effect indicating that surface recombination has a significant influence on beta. A minimum distance of 2-3 mu m between the emitter edge and base contact implant was found adequate to avoid a substantial beta reduction.

  • 4. Echtermeyer, Tim J.
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Baus, Matthias
    Szafranek, Bartholomaeus N.
    Geim, Andre K.
    Kurz, Heinrich
    Nonvolatile switching in graphene field-effect devices2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 8, p. 952-954Article in journal (Refereed)
    Abstract [en]

    The absence of a band gap in graphene restricts its straightforward application as a channel material in field-effect transistors. In this letter, we report on a new approach to engineer a band gap in graphene field-effect devices (FEDs) by controlled structural modification of the graphene channel itself. The conductance in the FEDs is switched between a conductive "ON-state" and an insulating "OFF-state" with more than six orders of magnitude difference in conductance. Above a critical value of an electric field applied to the FED gate under certain environmental conditions, a chemical modification takes place to form insulating graphene derivatives. The effect can be reversed by electrical fields of opposite polarity or short current pulses to recover the initial state. These reversible switches could potentially be applied to nonvolatile memories and novel neuromorphic processing concepts.

  • 5.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits2017In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal (Refereed)
    Abstract [en]

    High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain (β) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.

  • 6.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT).
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    500 degrees C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits2017In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 38, no 10, p. 1429-1432Article in journal (Refereed)
    Abstract [en]

    High-current 4H-SiC lateral BJTs for hightemperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (J(C)), lower on-resistance (R-ON), and more uniform current distribution. A maximum current gain (beta) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs aremeasured fromroom temperature to 500 degrees C. An open-base breakdown voltage (V-CEO) of > 50 V is measured for the devices.

  • 7.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 2, p. 168-170Article in journal (Refereed)
    Abstract [en]

    Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm(2) is obtained for the device with an active area of 0.065 mm(2). A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R-ON) of 28 m Omega.cm(2) was obtained.

  • 8.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 11, p. 1170-1172Article in journal (Refereed)
    Abstract [en]

    Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of similar to 1.2 x 10(13) cm(-2) in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single-and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.

  • 9.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High current-gain implantation-free 4H-SiC Monolithic Darlington Transistor2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 2, p. 188-190Article in journal (Refereed)
    Abstract [en]

    An implantation-free 4H-SiC Darlington transistor with high current gain of 2900 ( JC= \970A/cm2) and VCE) = 6V) at room temperature is reported. The device demonstrates a record maximum current gain of 640 at 200 hC, offering an attractive solution for high-temperature applications. The monolithic Darlington device exhibits an open-base breakdown voltage of 1 kV that is less than the optimum bulk breakdown due to isolation trench between the driver and the output bipolar junction transistor. On the same wafer, a monolithic Darlington pair with a nonisolated base layer was also fabricated. At room temperature, this device shows a maximum current gain of 1000 and an open-base breakdown voltage of 2.8 kV, which is 75% of the parallel-plane breakdown voltage

  • 10.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedotto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Shayestehaminzadeh, Seyedmohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Removal of Crystal Orientation Effects on the Current Gain of 4H-SiC BJTs Using Surface Passivation2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 5, p. 596-598Article in journal (Refereed)
    Abstract [en]

    In this letter, the dependence of current gain and base resistance on crystal orientations for single-finger 4H-SiC bipolar junction transistors ( BJTs) is analyzed. Statistical evaluation techniques were also applied to study the effect of surface passivation and mobility on the performance of the devices. It is shown that BJTs with an emitter edge aligned to the [1 (2) under bar 10] direction shows a lower current gain before surface passivation and higher base resistance after contact formation compared with other investigated crystal directions. However, the devices show a similar current gain independent of the crystal orientation after surface passivation.

  • 11.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of 2700-v 12-m Omega center dot cm(2) non ion-implanted 4H-SiC BJTs with common-emitter current gain of 502008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 10, p. 1135-1137Article in journal (Refereed)
    Abstract [en]

    High-voltage blocking (2.7-kV) implantation-free SiC bipolar junction transistors with low ON-state resistance (12 m Omega . cm(2)) and high common-emitter current gain of 50 have been fabricated. A graded-base doping was implemented to provide a low-resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high-temperature dopant activation annealing and for avoiding generation of lifetime-killing defects that reduce the current gain.

  • 12. Gottlob, H. D. B.
    et al.
    Echtermeyer, T.
    Schmidt, M.
    Mollenhauer, T.
    Efavi, J. K.
    Wahlbrink, T.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Czernohorsky, M.
    Bugiel, E.
    Fissel, A.
    Osten, H. J.
    Kurz, H.
    0.86-nm CET gate stacks with epitaxial Gd2O3 high-k dielectrics and FUSINiSi metal electrodes2006In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 27, no 10, p. 814-816Article in journal (Refereed)
    Abstract [en]

    In this letter, ultrathin gadolinium oxide (Gd2O3) high-kappa gate dielectrics with complementary-metal-oxide-semiconductor (CMOS)-compatible fully silicided nickel-silicide metal gate electrodes are reported for the first time. MOS capacitors with a Gd2O3 thickness of 3.1 nm yield a capacitance equivalent oxide thickness of CET = 0.86 nm. The extracted dielectric constant is kappa =-13-14. Leakage currents and equivalent oxide thicknesses of this novel gate stack meet the International Technology Roadmap for Semiconductors targets for the near term schedule and beyond.

  • 13.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Luo, Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 5, p. 541-543Article in journal (Refereed)
    Abstract [en]

    Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (<= 700 degrees C) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (t(si) = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 (.) 10(15) and 5. 10(15) cm(-2). Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.

  • 14.
    Hallén, Anders
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Nawaz, Muhammad
    Zaring, Carina
    Usman, Muhammad
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Low-Temperature Annealing of Radiation-Induced Degradation in 4H-SiC Bipolar Junction Transistors2010In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 31, no 7, p. 707-709Article in journal (Refereed)
    Abstract [en]

    Radiation hardness is tested for 4H-SiC n-p-n bipolar junction transistors designed for 1200-V breakdown voltage by implanting MeV protons and carbon ions at different doses and energies. The current gain is found to be a very sensitive parameter, and a fluence as low as 1 x 107 cm(-2) of 10 MeV C-12 can be clearly detected in the forward-output characteristics, I-C(V-CE). At this low dose, no influence of ion radiation is seen in the open-collector characteristics, I-B(V-EB), or the reverse bias leakage and breakdown properties. Moreover, by annealing the implanted devices at 420 degrees C for 30 min, a complete recovery of the electrical characteristics is accomplished.

  • 15.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Monolithic, 500 degrees C Operational Amplifier in 4H-SiC Bipolar Technology2014In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 35, no 7, p. 693-695Article in journal (Refereed)
    Abstract [en]

    A monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented. The opamp has been used in an inverting negative feedback amplifier configuration. Wide temperature operation of the amplifier is demonstrated from 25 degrees C to 500 degrees C. The measured closed loop gain is around 40 dB for all temperatures whereas the 3 dB bandwidth increases from 270 kHz at 25 degrees C to 410 kHz at 500 degrees C. The opamp achieves 1.46 V/mu s slew rate and 0.25% total harmonic distortion. This is the first report on high temperature operation of a fully integrated SiC bipolar opamp which demonstrates the feasibility of this technology for high temperature analog integrated circuits.

  • 16.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wide Temperature Range Integrated Bandgap Voltage References in 4H–SiC2016In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 37, no 2, p. 146-149Article in journal (Refereed)
    Abstract [en]

    Three fully integrated bandgap voltage references (BGVRs) have been demonstrated in a 4H-SiC bipolar technology. The circuits have been characterized over a wide temperature range from 25 degrees C to 500 degrees C. The three BGVRs are functional and exhibit 46 ppm/degrees C, 131 ppm/degrees C, and 120 ppm/degrees C output voltage variations from 25 degrees C up to 500 degrees C. This letter shows that SiC bipolar BGVRs are capable of providing stable voltage references over a wide temperature range.

  • 17.
    Hou, Shuoben
    et al.
    KTH, School of Information and Communication Technology (ICT), Elektronics.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Elektronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Elektronics.
    550 degrees C 4H-SiC p-i-n Photodiode Array With Two-Layer Metallization2016In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 37, no 12, p. 1594-1596Article in journal (Refereed)
    Abstract [en]

    The p-i-n ultraviolet (UV) photodiodes based on 4H-SiC have been fabricated and characterized from room temperature (RT) to 550 degrees C. Due to bandgap narrowing at higher temperatures, the photocurrent of the photodiode increases by 9 times at 365 nm and reduces by 2.6 times at 275 nm from RT to 550 degrees C. Moreover, a 4H-SiC p-i-n photodiode array has been fabricated. Each column and row of the array is separately connected by two-layer metallization.

  • 18.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    von Haartman, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hole mobility in ultrathin body SOI pMOSFETs with SiGe or SiGeC channels2006In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 27, no 6, p. 466-468Article in journal (Refereed)
    Abstract [en]

    The hole mobilities of SiGe and SiGeC channel pMOSFETs fabricated on ultrathin silicon-on-insulator substrates are investigated and compared with reference Si channel devices. The total thickness of the fully depleted Si/SiGe(C)/Si body structure is similar to 25 nm. All devices demonstrated a near ideal subthreshold behavior, and the drive current and mobility were increased with more than 60% for SiGe and SiGeC channels. When comparing SIMOX and UNIBOND substrates, no significant difference could be detected.

  • 19. Konstantinov, A O
    et al.
    Ivanov, P A
    Nordell, N
    Karlsson, S
    Harris, C I
    High-voltage operation of field-effect transistors in silicon carbide1997In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 18, no 11, p. 521-522Article in journal (Refereed)
  • 20.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    500 degrees C Bipolar Integrated OR/NOR Gate in 4H-SiC2013In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 34, no 9, p. 1091-1093Article in journal (Refereed)
    Abstract [en]

    Successful operation of low-voltage 4H-SiC n-p-n bipolar transistors and digital integrated circuits based on emitter coupled logic is reported from -40 degrees C to 500 degrees C. Nonmonotonous temperature dependence (previously predicted by simulations but now measured) was observed for the transistor current gain; in the range -40 degrees C - 300 degrees C it decreased when the temperature increased, while it increased in the range 300 degrees C-500 degrees C. Stable noise margins of similar to 1 V were measured for a 2-input OR/NOR gate operated on -15 V supply voltage from 0 degrees C to 500 degrees C for both OR and NOR output.

  • 21.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of Passivation Oxide Thickness and Device Layout on the Current Gain of SiC BJTs2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 1, p. 11-13Article in journal (Refereed)
    Abstract [en]

    The effect of passivation oxide thickness and layout on the current gain of SiC bipolar junction transistors is reported. Different thicknesses of plasma enhanced chemical vapor deposited (PECVD) silicon dioxide in the range 50-150 nm were deposited prior to the same annealing process in N2O, and their effect on the transistor gain was investigated for different device layouts. For a fixed device layout, similar to 60% higher gains were observed for oxide thicknesses ranging between 100 and 150 nm with current gains of similar to 200 at room temperature and >100 at 300 degrees C. For each tested thickness of deposited oxide, device layout providing lower collector resistance achieved slightly higher gains.

  • 22.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lateral p-n-p Transistors and Complementary SiC Bipolar Technology2014In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 35, no 4, p. 428-430Article in journal (Refereed)
    Abstract [en]

    Lateral p-n-p transistors and a complementary bipolar technology have been demonstrated for analog integrated circuits. Besides vertical n-p-n's, this technology provides lateral p-n-p's at the cost of one additional lithographic and dry etching step. Both devices share the same epitaxial layers and feature topside contacts to all terminals. The influence on p-n-p current gain of contact topology (circular versus rectangular), effective base width, base/emitter doping ratio, and temperature was studied in detail. In the range -40 degrees C to 300 degrees C, the current gain of the p-n-p transistor shows a maximum of similar to 37 around 0 degrees C and decreases to similar to 8 at 300 degrees C, whereas in the same range, the gain of n-p-n transistors exhibits a negative temperature coefficient.

  • 23.
    Lee, Hyung-Seok
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Material Physics, Semiconductor Materials, HMA.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Allerstam, Fredrik
    Department of Microtechnology and Nanoscience, Chalmers University of Technology.
    Sveinbjörnsson, Einar Ö.
    Department of Microtechnology and Nanoscience, Chalmers University of TechnologyDepartment of Microtechnology and Nanoscience, Chalmers University of Technology.
    1200-V 5.2-m Omega center dot cm(2) 4H-SiC BJTs with a high common-emitter current gain2007In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 28, no 11, p. 1007-1009Article in journal (Refereed)
    Abstract [en]

    This letter presents fabrication of a power 4H-SiC bipolar junction transistor (BJT) with a high open-base breakdown voltage BVCEO approximate to 1200 V, a low specific ON-resistance R-SP_ON approximate to 5.2 m Omega . cm(2), and a high common-emitter current. gain beta approximate to 60. The high gain of the BJT is attributed to reduced surface recombination that has been obtained using passivation by thermal silicon dioxide grown in nitrous oxide (N2O) ambient. Reference BJTs with passivation by conventional dry thermal oxidation show a clearly lower current gain and a more pronounced emitter-size effect. BJTs with junction termination by a guard-ring-assisted junction-termination extension (JTE) show about 400 V higher breakdown voltage compared with BJTs with a conventional JTE.

  • 24.
    Lemme, Max C.
    et al.
    AMO GmbH, AMICA, Aachen, Germany.
    Echtermeyer, Tim J.
    Baus, Matthias
    Kurz, Heinrich
    A graphene field-effect device2007In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 28, no 4, p. 282-284Article in journal (Refereed)
    Abstract [en]

    In this letter, a top-gated field-effect device (FED) manufactured from monolayer graphene is investigated. Except for graphene deposition, a conventional top-down CMOS-compatible process flow is applied. Carrier mobilities in graphene pseudo-MOS structures are compared to those obtained from the top-gated Graphene-FEDs. The extracted values exceed the universal mobility of silicon and silicon-on-insulator MOSFETs.

  • 25.
    Li, Jiantong
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhibin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Contact-electrode insensitive rectifiers based on carbon nanotube network transistors2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, p. 500-502Article in journal (Refereed)
    Abstract [en]

    This letter presents rectifiers based on the diode connection of carbon nanotube network (CNN) transistors. Despite a low density of carbon nanotubes in the CNNs, the devices can achieve excellent performance with a forward/reverse current ratio reaching 10(5). By casting nanotube suspension on oxidized Si substrates with predefined electrodes, CNN-based field-effect transistors are readily prepared. By short-circuiting the source and gate terminals, CNN-based rectifiers are realized with the rectification characteristics independent of whether Pd or Al is employed as the contact electrodes. This independence is especially attractive for applications of CNN-based transistors/rectifiers in flexible electronics with various printing techniques.

  • 26.
    Liu, Zhiying
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Qiu, Zhijun
    Zhang, Z B
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, S L
    Mobility Extraction for Nanotube TFTs2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 7, p. 913-915Article in journal (Refereed)
    Abstract [en]

    An extensive investigation of carrier mobility is presented for thin-film transistors (TFTs) with single-walled carbon nanotube (SWCNT) networks as the semiconductor channel. For TFTs particularly with low-density SWCNTs in the networks, the extracted mobility using the standard method for Si metal-oxide-semiconductor field-effect transistors is erroneous, mainly resulting from use of a parallel-plate capacitor model and assumption of the source-drain current being inversely proportional to the channel length. Large hysteresis in the transfer characteristics further complicates the extraction. By properly addressing all these challenges in this letter, a comprehensive methodology is established, leading to the extraction of mobility values that are independent of geometrical parameters.

  • 27. Liu, Zhiying
    et al.
    Zhang, Zhi-Bin
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhang, Shi-Li
    Solution-Processable Nanotube/Polymer Composite for High-Performance TFTs2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 9, p. 1299-1301Article in journal (Refereed)
    Abstract [en]

    Thin-film field-effect transistors (TFTs) are readily fabricated using a semiconductor composite that is solution processed under ambient conditions for the conduction channel. The composite comprises single-walled carbon nanotubes (SWCNTs) embedded in poly-9,9' dioctyl-fluorene-co-bithiophene. Carrier mobility values approaching 10 cm(2)V(-1)s(-1) are obtained for the composite with relatively high SWCNT concentrations. When the SWCNT concentration is reduced for a large ON/OFF current ratio > 10(6), the mobility remains decent around 0.3 cm(2)V(-1)s(-1). The resultant TFTs display remarkable environmental and operational reliability. Nanotube-based composites are therefore of significance in printed electronics owing to their simplicity in device fabrication and competitiveness in device performance.

  • 28.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    Zhang, David Wei
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östrling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effect of carbon on Schottky barrier heights of NiSi modified by dopant segregation2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 6Article in journal (Refereed)
    Abstract [en]

    The presence of carbon at the interface between NiSi and Si has been found to participate in the process of modification of effective Schottky barrier heights using the dopant segregation (DS) method. Carbon alone results in an increased ∅bn from 0.7 to above 0.9 eV. Boron diffusion in NiSi is inhibited by carbon, and no B-DS at the NiSi/Si interface occurs below 600°C. Above this temperature, B-DS at this interface is evident thus keeping φbn high. The presence of interfacial carbon leads to an increased interfacial As concentration resulting in beneficial effects in tuning ∅bp above 1.0 eV by As-DS.

  • 29.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Qiu, Zhi-Jun
    Zhang, David Wei
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    Effects of Carbon on Schottky Barrier Heights of NiSi Modified by Dopant Segregation2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 6, p. 608-610Article in journal (Refereed)
    Abstract [en]

    The presence of carbon at the interface between NiSi and Si has been found to participate in the process of modification of effective Schottky barrier heights using the dopant segregation (DS) method. Carbon alone results in an increased phi(bn) from 0.7 to above 0.9 eV. Boron diffusion in NiSi is inhibited by carbon, and no B-DS at the NiSi/Si interface occurs below 600 degrees C. Above this temperature, B-DS at this interface is evident thus keeping phi(bn) high. The presence of interfacial carbon leads to an increased interfacial As concentration resulting in beneficial effects in tuning phi(bn) above 1.0 eV by As-DS.

  • 30.
    Malm, B. Gunnar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Haralson, E.
    Suvar, E.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Wang, Yong-Bin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Base resistance scaling for SiGeC HBTs with a fully nickel-silicided extrinsic base2005In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 26, no 4, p. 246-248Article in journal (Refereed)
    Abstract [en]

    A novel SiGeC HBT process with a quasi-self-aligned emitter-base architecture and a fully nickel-silicided extrinsic base region has been developed. A very low total base resistance R-B was achieved along with simultaneous NiSi formation on the polycrystalline emitter and collector regions. Uniform silicide formation was obtained across the wafer, and the resistivity. of the Ni(SiGe:C) silicide layer was 24 mu Omega (.) cm. About 50-100 nm of lateral growth of silicide,. underneath the emitter pedestal was observed. DC and HF results with balanced f(T)/f(MAX) values of 41/42 GHz were demonstrated for 0.5 X 10 mu m(2) transistors.

  • 31.
    Malm, B. Gunnar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Ge-profile design for improved linearity of SiGe double HBTs2002In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 23, no 1, p. 19-21Article in journal (Refereed)
    Abstract [en]

    The influence of Ge-profile design on SiGe HBT linearity-harmonic distortion has been quantified using finite element physical device simulation. It was demonstrated that proper Ge-profile tailoring allows the linearity to be improved for both low- and high-current operation. High injection heterojunction barrier effects are shown to have a significant influence on the higher order harmonies. The influence of the Ge-profile design on linearity was found to be comparable to the influence from the epitaxial collector doping profile.

  • 32. Mehr, Wolfgang
    et al.
    Dabrowski, Jarek
    Scheytt, J. Christoph
    Lippert, Gunther
    Xie, Ya-Hong
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lupina, Grzegorz
    Vertical Graphene Base Transistor2012In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 33, no 5, p. 691-693Article in journal (Refereed)
    Abstract [en]

    We present a novel graphene-based-device concept for a high-frequency operation: a hot-electron graphene base transistor (GBT). Simulations show that GBTs have high current on/off ratios and high current gain. Simulations and small-signal models indicate that it potentially allows terahertz operation. Based on energy-band considerations, we propose a specific material solution that is compatible with SiGe process lines.

  • 33. Moschetti, Giuseppe
    et al.
    Nilsson, Per-Åke
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Desplanque, Ludovic
    Wallart, Xavier
    Grahn, Jan
    Planar InAs/AlSb HEMTs With Ion-Implanted Isolation2012In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 33, no 4, p. 510-512Article in journal (Refereed)
    Abstract [en]

    The fabrication and performance of planar InAs/AlSb high-electron-mobility transistors (HEMTs) based on ion-implantation isolation technology are reported. Ar atoms have been implanted at an energy of 100 keV and with a dose of 2 x 10(15) cm(-2) in order to induce device isolation. The InAs/AlSb HEMT exhibited a maximum drain current of 900 mA/mm, a peak transconductance of 1180 mS/mm, and an f(T)/f(max) ratio of 210 GHz/180 GHz at a low drain bias of 0.3 V. The combination of excellent stability against oxidation with the high device isolation demonstrated by the implantation technique can dramatically improve the suitability of InAs/AlSb HEMTs for high-frequency and ultralow-power MMIC applications.

  • 34.
    Olyaei, Maryam
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Low-frequency noise characterization in ultra-low equivalent-oxide-thickness thulium silicate interfacial layer nMOSFETs2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 12, p. 1355-1358Article in journal (Refereed)
    Abstract [en]

    Low-frequency noise measurements were performed on n-channel MOSFETs with a novel ultra-low 0.3nm EOT interfacial layer (TmSiO) and two different bulk high-k dielectrics (Tm2O3 and HfO2). The MOSFETs were fabricated in a gate-last process and the total gate stack EOT was 1.2 nm and 0.65 nm for the Tm2O3 and HfO2 samples respectively. In general both gate stacks resulted in 1/f type of noise spectra and noise levels comparable to conventional SiO2/HfO2 devices with similar EOTs. The extracted average effective oxide trap density was 2.5×1017 cm-3eV-1 and 1.5×1017 cm-3eV-1 for TmSiO/HfO2 and TmSiO/Tm2O3 respectively. Therefore the best noise performance was observed for the gate stack with Tm2O3 bulk high-k layer and we suggest that the interface free single layer ALD fabrication scheme could explain this.

  • 35. Qu, Minni
    et al.
    Qiu, Zhi-Jun
    Zhang, Zhi-Bin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Li, Hui
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    Charge-Injection-Induced Time Decay in Carbon Nanotube Network-Based FETs2010In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 31, no 10, p. 1098-1100Article in journal (Refereed)
    Abstract [en]

    A voltage-pulse method is utilized to investigate the charge-injection-induced time decay of the source-drain current of field-effect transistors with randomly networked single-walled carbon nanotubes (CNTs) as the conduction channel. The relaxation of trapped carriers in the CNT networks can be accounted for by assuming two exponential decays occurring simultaneously. The slow decay is characterized by a time constant comparable to literature data obtained for a carrier recombination in the semiconducting CNTs. The faster decay with a time constant that has a smaller order of magnitude is attributed to the annihilation of trapped carriers in metallic CNTs or at metal-CNT contacts. Both time constants are gate-bias dependent.

  • 36. Rohner, M.
    et al.
    Willen, Bo G.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jackel, H.
    Velocity-modulation and transit-time effects in InP/InGaAs HBTs2001In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 22, no 9, p. 417-419Article in journal (Refereed)
    Abstract [en]

    The base-collector capacitance C-bc and the collector transit time delay tau

  • 37.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Jacobs, Keijo
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    15 kV-Class Implantation-Free 4H-SiC BJTs With Record High Current Gain2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 1, p. 63-66Article in journal (Refereed)
    Abstract [en]

    Implantation-free mesa-etched ultra-high-voltage (0.08 mm(2)) 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured, and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension is utilized to obtain a high and stable breakdown voltage without ion implantation. The open-base blocking voltage of 15.8 kV at a leakage current density of 0.1 mA/cm(2) is achieved. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared.

  • 38.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    15 kV-Class implantation-Free 4H-SiC BJTs with Record High Current Gain2016In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal (Other academic)
    Abstract [en]

    Implantation-free mesa-etched ultra-high-voltage 4H-SiC bipolar junction transistors (BJTs) with record current gain of 139 are fabricated, measured and analyzed by device simulation. High current gain is achieved by optimized surface passivation and optimal cell geometries. The area-optimized junction termination extension (O-JTE) is utilized in order to obtain a high and stable breakdown voltage without ion implantation. Different cell geometries (single finger, square, and hexagon cell geometries) are also compared. The base size effect is investigated in order to improve current gain.

  • 39.
    Salemi, Arash
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 10, p. 1069-1072Article in journal (Refereed)
    Abstract [en]

    Three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance (R-ON), current density (J(C)), and temperature performance for the first time. Emitter size effect and surface recombination are investigated. Due to a better utilization of the base area, optimal emitter cell geometry significantly increases the current density about 42% and reduces the ON-resistance about 21% at a given current gain, thus making the device more efficient for high-power and high-temperature applications.

  • 40. Sanden, M.
    et al.
    Marinov, O.
    Deen, M. J.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Modeling the variation of the low-frequency noise in polysilicon emitter bipolar junction transistors2001In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 22, no 5, p. 242-244Article in journal (Refereed)
    Abstract [en]

    The variation of the low-frequency noise in polysilicon emitter bipolar junction transistors (BJTs) was investigated as a function of emitter area (A(E)) For individual BJTs with submicron-sized As, the low-frequency noise strongly deviated from a 1/f-dependence. The averaged noise varied as 1/f, with a magnitude proportional to A(E)(-1), while the variation in the noise level was found to vary as A(E)(-1.5). A new expression that takes into account this deviation is proposed for SPICE modeling of the the low-frequency noise, The traps responsible for the noise were located to the thin SiO2 interface between the polysilicon and monosilicon emitter, The trap's energy level, areal concentration and capture cross-section were estimated to 0.31 eV, 6 x 10(8) cm(-2) and 2 x 10(-19) cm(2), respectively.

  • 41.
    Usman, Muhammad
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radiation-Hard Dielectrics for 4H-SiC: A Comparison Between SiO(2) and Al(2)O(3)2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 12, p. 1653-1655Article in journal (Refereed)
    Abstract [en]

    Ion implantation effects at SiO(2)/SiC and Al(2)O(3)/SiC interfaces have been investigated by implanting Ar ions at the interface of oxide and SiC. Capacitance-voltage relation and breakdown properties for these dielectrics are studied before and after implantation. The results indicate that the SiO(2)/SiC interface is sensitive to ion fluences higher than 1 x 10(11) cm(-2), while Al(2)O(3) on SiC can sustain higher fluences. In addition, the breakdown of the Al(2)O(3) is found to be less sensitive to the ion implantation.

  • 42.
    Willen, Bo G.
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Rohner, M.
    Jackel, H.
    Unilateral power gain limitations due to dynamic base widening effects2001In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 22, no 8, p. 370-372Article in journal (Refereed)
    Abstract [en]

    It is shown that the maximum frequency of oscillation of an InP-HBT may be limited by the low velocity of the holes when operated in the base push-out regime since modulation of the extended base will be delayed by the hole transit time, having an effect also on the electron current. The resulting delay of the current response causes a peaking of the unilateral power gain followed by a -40 dB/decade roll-off, being a source for a strong overestimation of the extrapolated cut-off frequency when neglected,An extended equivalent small-signal circuit is proposed that takes these effects into account.

  • 43.
    Willen, Bo G.
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Rohner, M.
    Schwarz, V.
    Jackel, H.
    Experimental evaluation of the InP-InGaAs-HBT power-gain resonance2002In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 23, no 10, p. 579-581Article in journal (Refereed)
    Abstract [en]

    An InP-InGaAs HBT has been evaluated that exhibits resonant hole modulation effects at a sufficiently low frequency for the resonance to be completely characterized by network analyzer measurements. It is shown that the frequency dependence of both the unilateral power gain and the current gain are modified by this effect, thus affecting the associated cutoff frequencies f(max) and f(T). A new power gain expression G(P) based on measured small-signal parameters is introduced to circumvent the ambiguity in the unilateral power gain. Finding f(max) and f(T) by means of extrapolation of G(P) and h(21), respectively, from a region below the,resonance frequency is proposed to yield appropriate estimates of the figures-of-merit for device applications.

  • 44. Wu, D.
    et al.
    Lindgren, A. C.
    Persson, S.
    Sjoblom, G.
    von Haartman, M.
    Seger, J.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, J.
    Blom, H. O.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Vainonen-Ahlgren, E.
    Li, W. M.
    Tois, E.
    Tuominen, A.
    A novel strained Si0.7Ge0.3 surface-channel pMOSFET with an ALD TiN/Al2O3/HfAlOx/Al2O3 gate stack2003In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 24, no 3, p. 171-173Article in journal (Refereed)
    Abstract [en]

    Proof-of-concept pMOSFETs with a strained-Si0.7Ge0.3 surface-channel deposited by selective epitaxy and a TiN/Al2O3/HfAIO(x)/Al2O3 gate stack grown by atomic layer chemical vapor deposition (ALD) techniques were fabricated. The Si0.7Ge0.3 pMOSFETs exhibited more than 30% higher current drive and peak transconductance than reference Si pMOSFETs with the same gate stack. The effective mobility for the Si reference coincided with the universal hole mobility curve for Si. The presence of a relatively low density of interface states, determined as 3.3x10(11) cm(-2) eV(-1), yielded a subthreshold slope of 75 mV/dec. for the Si reference. For the Si0.7Ge0.3 pMOSFETs, these values were 1.6x10(12) cm(-2) eV(-1) and 110 mV/dec., respectively.

  • 45.
    Wu, Donping
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Lu, J
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, SL
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Vainonen-Ahlgren, E
    Tois, E
    Tuominen, M
    Influence of surface treatment prior to ALD high-kappa dielectrics on the performance of SiGe surface-channel pMOSFETs2004In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 25, no 5, p. 289-291Article in journal (Refereed)
    Abstract [en]

    Compressively strained Si0.7Ge0.3 surface-channel pMOSFETs with atomic layer deposition (ALD) Al2O3/HfO2/Al2O3 nanolaminate and low-pressure chemical vapor deposition p(+) poly-SiGe gate electrode were fabricated. Surface treatment with either hydrogen fluoride (HF) clean, or HF clean followed by water rinse was performed prior to the ALD processing. The devices with water rinse show a good control of interfacial layer and device reproducibility, while the devices without water rinse lack a clearly observable interfacial layer and show scattered electrical characteristics and distorted mobility curve. A similar to20% increase in hole mobility compared to the Si universal mobility and a similar to0.6-nm-thick continuous interfacial layer are obtained for the pMOSFETs with water rinse.

  • 46.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Performance fluctuation of FinFETs with Schottky barrier source/drain2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 5, p. 506-508Article in journal (Refereed)
    Abstract [en]

    A considerable performance fluctuation of FinFETs featuring PtSi-based Schottky barrier source/drain is found. The Fin-channels measure 27-nm tall and 35-nm wide. Investigation of similarly processed transistors of broad gate-widths reveals a large variation in the position of the PtSi/Si interface with reference to the gate edge along the gate width. This variation suggests an uneven underlap between the PtSi and the gate from device to device for the FinFETs, since essentially only one silicide grain would be in contact with each Fin-channel at the PtSi/Si interface. The size of the underlap is expected to sensitively affect the performance of the FinFETs.

  • 47.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Olsson, Jörgen
    The Ångström Laboratory, Uppsala University.
    Lu, Jun
    Uppsala University, Ångström Laboratory.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SB-MOSFETs in UTB-SOI featuring PtSi source/drain with dopant segregation2008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 1, p. 125-127Article in journal (Refereed)
    Abstract [en]

    MOSFETs of both polarities with PtSi-based Schottky-barrier source/drain (S/D) have been fabricated in ultrathin-body Si-on-insulator. The PtSi is formed in the S/D regions without lateral silicide growth under the gate spacers. This design leads to a 30-nm underlap between the PtSi-Si contacts and the gate edges resulting in low drive currents. Despite the underlap, excellent performance is achieved for both types of MOSFETs with large drive currents and low leakage by means of dopant segregation through As and B implantation into the PtSi followed by drive-in annealing at low temperatures.

  • 48.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhijun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Liu, Ran
    State Key Laboratory of ASIC and System, School of Microelectronics, Fudan University.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schottky-barrier height tuning by means of ion implantation into preformed silicide films followed by drive-in anneal2007In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 28, no 7, p. 565-568Article in journal (Refereed)
    Abstract [en]

    An experimental study on Schottky-barrier height (SBH) tuning using ion implantation followed by drive-in anneal of As, B, In, and P in preformed NiSi and PtSi films is presented. Measured on B-implanted NiSi and PtSi Schottky diodes, the effective SBH on n-type Si is altered to similar to 1.0 eV. For As- and P-implanted diodes, the SBH on p-type Si can be tuned to around 0.9 eV The process window for the most pronounced SBH modification is dopant dependent.

  • 49.
    Zhang, Zhibin
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Qu, Minni
    Cabezas, Ana Lopez
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zhang, Shi-Li
    Photo-Activated Interaction Between P3HT and Single-Walled Carbon Nanotubes Studied by Means of Field-Effect Response2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 12, p. 1302-1304Article in journal (Refereed)
    Abstract [en]

    It is shown in this letter that the field-effect electrical response of transistors with their channel made of networks of single-walled carbon nanotubes (SWNTs) embedded in a poly(3-hexylthiophene) (P3HT) matrix can be significantly altered by light illumination. The experimental results indicate a photo-activated electron transfer from P3HT selectively to the semiconducting SWNTs. This finding points to a potential optoelectronic application of such a field-effect device as a photo-triggered electronic switch.

1 - 49 of 49
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf