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  • 1. Adiseno,
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Olsson, Håkan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 9, p. 1162-1168Article in journal (Refereed)
    Abstract [en]

    A wide-band radio-frequency (RF) front-end is designed with a balanced combined low-noise amplifier and a switching mixer (a low-noise converter) in RF Si-bipolar process with an f(T) of 25 GHz. The circuit achieves 20-dB conversion gain, higher than -4.5-dBm RF-to-IF IIP3 (+15.5-dBm OIP3) and less than 3.8-dB double-side-band noise figure in 900-MHz (e.g., GSM) and 1.9-GHz (e.g., WCDMA) frequency bands. The -1-dB compression point is -20 dBm at 13-mA dc current consumption from a single 5-V supply. The local-oscillator leakage to the input is less than -56 dBm in the 900-MHz band and less than -63 dBm in the 1.9-GHz band. The -3-dB bandwidth of the amplifier is larger than 3 GHz and a wide-band matching at the input with - 10 to -41-dB S-11 is achieved in the frequency bands of interest by applying a dual-loop wide-band active feedback. The die area is 0.69 x 0.9 mm(2). The circuit is suitable for area-efficient multiband multistandard low-IF receivers.

  • 2. Alzaher, H. A.
    et al.
    Elwan, H. O.
    Ismail, Mohammed
    A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers2002In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 37, no 1, p. 27-37Article in journal (Refereed)
    Abstract [en]

    A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm(2) in a 0.5-mum chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54),89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.

  • 3. Badaroglu, M.
    et al.
    Donnay, S.
    De Man, H. J.
    Zinzius, Y. A.
    Gielen, G. G. E.
    Sansen, W.
    Fonden, T.
    Signell, Svante
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Modeling and experimental verification of substrate noise generation in a 220-Kgates WLAN system-on-chip with multiple supplies2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 7, p. 1250-1260Article in journal (Refereed)
    Abstract [en]

    Substrate noise is a major obstacle for mixed-signal integration. While the power consumption scales linearly with the clock frequency, substrate noise does not have thin scaling due to the resonances in the transfer function of the supply current to the substrate. This paper addresses a practical technique to estimate the substrate noise frequency spectrum of a large mixed-mode System-on-Chip (SoC) with multiple supplies and embedded memories. The results have been verified with substrate noise measurements on a 60-MHz 220-Kgates telecom SoC implemented in a 0.3 mum CMOS process on an EPI-type substrate. We compute a linear chip-level substrate model together with the single-cycle representation of piecewise-linear noise sources of three. supply regions used in this ASIC. Based on this model we accurately estimate the four major resonances in the substrate poise spectrum and their relative magnitudes with 2 dB relative error at the major resonance with respect to measurements. We also present substrate noise measurements at different operating modes of the WLAN receiver. These measurements show that output I/O buffers generate significant substrate noise where an increase of 44% is measured for substrate noise peak-to-peak value due to the additional simultaneous switching of six output I/O buffers with already fully switching datapath and two output I/Os.

  • 4. Bao, Dongxuan
    et al.
    Zou, Zhuo
    Nejad, Majid Baghaei
    Qin, Yajie
    Zheng, Li-rong
    KTH.
    A Wirelessly Powered UWB RFID Sensor Tag With Time-Domain Analog-to-Information Interface2018In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 53, no 8, p. 2227-2239Article in journal (Refereed)
    Abstract [en]

    This paper presents a wirelessly powered radio frequency identification sensor tag with an analog-to-information interface. A time-domain interface, incorporating an ultra-lowpower impulse radio ultra-wideband (IR-UWB) transmitter (TX), is employed. The analog signal from the sensor is compared with a triangular waveform, resulting in a pulse-position modulation signal to trigger UWB pulses. Thanks to the high time-resolution IR-UWB radio, time intervals of the impulses can be used to represent the original input value, which is measured remotely on the reader side by a time-of-arrival estimator. This approach not only eliminates the analog-to-digital converter (ADC) but also significantly reduces the number of bits to be transmitted for power saving. The proposed tag is fabricated in a 0.18-mu m CMOS process with an active area of 2.5 mm(2). The measurement results demonstrate that a 300-kS/s sampling rate with a 6.7-bit effective number of bits (ENOB) is obtained via a UWB receiver with a sensitivity of -93 dBm and an integration window of 10 ns. The ENOB is improved to 7.3 bits when the integration window is reduced to 2 ns. The tag can be powered up by a -18-dBm UHF input signal. The power consumption of the proposed tag is 41.5 mu W yielding a 1.3-pJ/conv.step figure of merit, offering 9x and 67x improvements compared with the state of the art based on an ADC and a backscattering TX, and the tag based on an ADC and a narrowband TX, respectively.

  • 5.
    Chen, Jian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Rong, Liang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yang, Geng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    The Design of All-Digital Polar Transmitter based on ADPLL and Phase Synchronized Delta Sigma Modulator2012In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 47, no 5, p. 1154-1164Article in journal (Refereed)
    Abstract [en]

    An improved architecture of polar transmitter (TX) is presented. The proposed architectureis digitally-intensive and mainly composed of an all-digital PLL (ADPLL) for phasemodulation, a 1-bit low-pass delta sigma (Delta Sigma) modulator for envelop modulation, and aH-bridge class-D power amplifier (PA) for differential signaling. The (Delta Sigma) modulator isclocked using the phase modulated RF carrier to ensure phase synchronization between theamplitude and phase path, and to guarantee the PA is switching at zero crossings of theoutput current.An on chip pre-filter is used to reduce the parasitic capacitance from packages at theswitch stage output. The high over sampling ratio of the (Delta Sigma) modulator move quantizationnoise far away from the carrier frequency, ensuring good in-band performance and relax filterrequirements. The on-chip filter also acts as impedance matching and differential to singleended conversion. The measured digital transmitter consumes 58 mW from a 1 V at 6.8 dBm output power.

  • 6. Dielacher, Franz
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Special issue on the 2002 European Solid State Circuits Conference (Esscirc): Guest editorial2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 7, p. 1095-1097Article in journal (Refereed)
  • 7.
    Jonsson, Fredrik
    et al.
    Spirea AB.
    et al.,
    A single-chip CMOS transceiver for 802.11a/b/g wireless LANs2004In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 39, no 12, p. 2250-2258Article in journal (Refereed)
    Abstract [en]

    A dual-band trimode radio fully compliant with the IEEE 802.11a, b, and g standards is implemented in a 0.18-mum CMOS process and packaged in a 48-pin QFN package. The transceiver achieves a receiver noise figure of 4.9/5.6 dB for the 2.4-GHz/5-GHz bands, respectively, and a transmit error vector magnitude (EVM) of 2.5% for both bands. The transmit output power is digitally controlled, allowing per-packet power control as required by the forthcoming 802.11 h standard. A quadrature accuracy of 0.3degrees in phase and 0.05 dB in amplitude is achieved through careful analysis and design of the I/Q generation parts of the local oscillator. The local oscillators achieve a total integrated phase noise of better than -34 dBc. Compatibility with multiple baseband chips is ensured by flexible interfaces toward the A/D and D/A converters, as well as a calibration scheme not requiring any baseband support. The chip passes +/-2 kV human body model ESD testing on all pins, including the RF pins. The total die area is 12 mm(2). The power consumption is 207 mW in the receive mode and 247 mW in the transmit mode using a 1.8-V supply.

  • 8.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Dual-Output Thermoelectric Energy Harvesting Interface with 86.6% Peak Efficiency at 30 μW and Total Control Power of 160 nW2016In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173XArticle in journal (Refereed)
    Abstract [en]

    A thermoelectric energy harvesting interface based on a single-inductor dual-output (SIDO) boost converter is presented. A system-level design methodology combined with ultra-low power circuit techniques reduce the power consumption and minimize the losses within the converter. Additionally, accurate zero-current switching (ZCS) and zero-voltage switching (ZVS) techniques are employed in the control circuit to ensure high conversion efficiency at μW input power levels. The proposed SIDO boost converter is implemented in a 0.18 μm CMOS process and can operate from input voltages as low as 15 mV. The measurement results show that the converter achieves a peak conversion efficiency of 86.6% at 30 μW input power.

    Download full text (pdf)
    EH_Interface
  • 9. Li, S. G.
    et al.
    Kipnis, I.
    Ismail, Mohammed
    10-GHz CMOS quadrature LC-VCO for multirate optical applications2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 10, p. 1626-1634Article in journal (Refereed)
    Abstract [en]

    A 10-GHz quadrature LC-VCO (QVCO) fabricated in a 0.13-mum CMOS process for 10-Gb/s multirate optical applications is described. Bimodal oscillation behavior (or phase ambiguity) inherent to quadrature LC-VCOs is analyzed theoretically and a cascode-based coupling method is proposed which effectively eliminates bimodal oscillation. Digitally controlled capacitor arrays are used in this design to extend the tuning range of the QVCO to cover multirate operations. The QVCO achieves a jitter generation of only 32 mUI(pp) at 10 GHz and a phase poise of -95 dBc/Hz at 1-MHz frequency offset with only 8 mA of current consumption in the QVCO core.

  • 10. Radiom, Soheil
    et al.
    Baghaei Nejad, Majid
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Mohammadpour-Aghdam, Karim
    Vandenbosch, Guy A. E.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Gielen, Georges G. E.
    Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink/UWB Uplink RFID Tag in 0.18-mu m Standard CMOS2010In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 45, no 9, p. 1746-1758Article in journal (Refereed)
    Abstract [en]

    This paper discusses two antennas monolithically integrated on-chip to be used respectively for wireless powering and UWB transmission of a tag designed and fabricated in 0.18-mu m CMOS technology. A multiturn loop-dipole structure with inductive and resistive stubs is chosen for both antennas. Using these on-chip antennas, the chip employs asymmetric communication links: at downlink, the tag captures the required supply wirelessly from the received RF signal transmitted by a reader and, for the uplink, ultra-wideband impulse-radio (UWB-IR), in the 3.1-10.6-GHz band, is employed instead of backscattering to achieve extremely low power and a high data rate up to 1 Mb/s. At downlink with the on-chip power-scavenging antenna and power-management unit circuitry properly designed, 7.5-cm powering distance has been achieved, which is a huge improvement in terms of operation distance compared with other reported tags with on-chip antenna. Also, 7-cm operating distance is achieved with the implemented on-chip UWB antenna. The tag can be powered up at all the three ISM bands of 915 MHz and 2.45 GHz, with off-chip antennas, and 5.8 GHz with the integrated on-chip antenna. The tag receives its clock and the commands wirelessly through the modulated RF powering-up signal. Measurement results show that the tag can operate up to 1 Mb/s data rate with a minimum input power of -19.41 dBm at 915-MHz band, corresponding to 15.7 m of operation range with an off-chip 0-dB gain antenna. This is a great improvement compared with conventional passive RFIDs in term of data rate and operation distance. The power consumption of the chip is measured to be just 16.6 mu W at the clock frequency of 10 MHz at 1.2-V supply. In addition, in this paper, for the first time, the radiation pattern of an on-chip antenna at such a frequency is measured. The measurement shows that the antenna has an almost omnidirectional radiation pattern so that the chip's performance is less direction-dependent.

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