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  • 1. Abermann, S.
    et al.
    Efavi, J. K.
    Sjoblom, G.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Olsson, J.
    Bertagnolli, E.
    Processing and evaluation of metal gate/high-kappa/Si capacitors incorporating Al, Ni, TiN, and Mo as metal gate, and ZrO2 and HfO2 as high-kappa dielectric2007In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 84, no 5-8, p. 1635-1638Article in journal (Refereed)
    Abstract [en]

    We evaluate various metal gate/high-K/Si capacitors by their resulting electrical characteristics. Therefore, we process MOS gate stacks incorporating aluminium (Al), nickel (Ni), titanium-nitride (TiN), and molybdenum (Mo) as the gate material, and metal organic chemical vapour deposited (MOCVD) ZrO2 and HfO2 as the gate dielectric, respectively. The influence of the processing sequence - especially of the thermal annealing treatment - on the electrical characteristics of the various gate stacks is being investigated. Whereas post metallization annealing in forming gas atmosphere improves capacitance-voltage behaviour (due to reduced interface-, and oxide charge density), current-voltage characteristics degrade due to a higher leakage current after thermal treatment at higher temperatures. The Flatband-voltage values for the TiN-, Mo-, and Ni-capacitors indicate mid-gap pinning of the metal gates, however, Ni seems to be thermally unstable on ZrO2, at least within the process scheme we applied.

  • 2. Baus, M
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Chmielus, S
    Sittig, R
    Spangenberg, B
    Kurz, H
    Fabrication of monolithic bidirectional switch devices2004In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 73-4, p. 463-467Article in journal (Refereed)
    Abstract [en]

    The fabrication scheme of a novel MOS-based power device, a monolithic bidirectional switch (MBS), is presented. This concept allows the integration of a bidirectional switch with the advantages of low power consumption, small package size, and low fabrication costs. Furthermore, device simulations predict a performance benefit for power applications such as matrix converters. In an MBS, the field effect is used to control carrier concentrations in elevated structures made up of nearly intrinsic silicon. A CMOS-compatible nano-fabrication process for the MBS is proposed, employing local oxidation of silicon for self-aligned contact formation. First electrical results are presented. (C) 2004 Elsevier B.V. All rights reserved.

  • 3.
    Chubarova, Elena
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Nilsson, Daniel
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Lindblom, Magnus
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Reinspach, Julia
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Birch, Jens
    Department of Physics, Chemistry, and Biology, Linköping University.
    Vogt, Ulrich
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Hertz, Hans M.
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Holmberg, Anders
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Platinum zone plates for hard X-ray applications2011In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 88, no 10, p. 3123-3126Article in journal (Refereed)
    Abstract [en]

    We describe the fabrication and evaluation of platinum zone plates for 5–12 kV X-ray imaging and focusing. These nano-scale circular periodic structures are fabricated by filling an e-beam generated mold with Pt in an electroplating process. The plating recipe is described. The resulting zone plates, having outer zone widths of 100 and 50 nm, show good uniformity and high aspect ratio. Their diffraction efficiencies are 50–70% of the theoretical, as measured at the European Synchrotron Radiation Facility. Platinum shows promise to become an attractive alternative to present hard X-ray zone plate materials due to its nano-structuring properties and the potential for zone-plate operation at higher temperatures.

  • 4. Efavi, J K
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T
    Wahlbrink, T
    Bobek, T
    Wang, D
    Gottlob, H D B
    Kurz, H
    Investigation of NiAlN as gate-material for submicron CMOS technology2004In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 76, no 1-4, p. 354-359Article in journal (Refereed)
    Abstract [en]

    Nickel-Aluminium-Nitride (NiAlN) is investigated as gate material for submicron CMOS technology for the first time. The MAIN films have been reactively sputtered from a Ni0.5Al0.5 target in a mixture of argon and nitrogen gas. The influence of the reactive gas content and process temperatures on the work function is presented. Electrical properties are extracted from high and low frequency capacitance-voltage measurements (QSCV, HFCV). Resistivity measurements are shown for various process conditions. Interface properties are observed by transmission electron microscopy. Primarily results show NiAlN's suitability for use as gate material in a CMOS replacement gate technology. Fabrication of n-type metal-oxide-semiconductor field effect transistors with a MAIN gates activated at 900 degreesC is demonstrated.

  • 5.
    Garidis, Konstantinos
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Pret, A. V.
    Gronheid, R.
    Mask roughness impact on extreme UV and 193 nm immersion lithography2012In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 98, p. 138-141Article in journal (Refereed)
    Abstract [en]

    The contribution of mask absorber line edge roughness on printed resist lines is studied for extreme UV and 193 nm immersion lithography. Programmed roughness modules were designed for roughness transfer function evaluation on 88 nm pitch line space patterns. The tested modules were designed applying variations of roughness amplitude and spatial frequency. Power spectral density analysis was performed on top-down SEM images. The effect of frequency roughness filtering by the lithographic optical system was studied with different illumination settings. It was found that, except for the degradation of the aerial image due to the filtering effect, less performing illuminations show an increased deterioration of the aerial image quality and thus contribute further to line edge roughness. A comparison with previous work was completed on different mask architectures and photoresist platforms. Resist performance can attenuate the roughness transfer from mask but at the cost of worse chemical gradient at the edges of the exposed regions.

  • 6. Gottlob, H. D. B.
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Schmidt, M.
    Echtermeyer, T. J.
    Mollenhauer, T.
    Kurz, H.
    Cherkaoui, K.
    Hurley, P. K.
    Newcomb, S. B.
    Gentle FUSI NiSi metal gate process for high-k dielectric screening2008In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 85, no 10, p. 2019-2021Article in journal (Refereed)
    Abstract [en]

    In this paper, a process flow well suited for screening of novel high-k dielectrics is presented. In vacuo silicon capping of the dielectrics excludes process and handling induced influences especially if hygroscopic materials are investigated. A gentle, low thermal budget process is demonstrated to form metal gate electrodes by turning the silicon capping into a fully silicided nickel silicide. This process enables the investigation of rare earth oxide based high-k dielectrics and specifically their intrinsic material properties using metal oxide semiconductor (MOS) capacitors. We demonstrate the formation of nickel monosilicide electrodes which show smooth interfaces to the lanthanum- and gadolinium-based high-k oxide films. The dielectrics have equivalent oxide thicknesses of EOT = 0.95 nm (lanthanum silicate) and EOT = 0.6 nm (epitaxial gadolinium oxide).

  • 7. Gottlob, H. D. B.
    et al.
    Schmidt, M.
    Stefani, A.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Mitrovic, I. Z.
    Davey, W. M.
    Hall, S.
    Werner, M.
    Chalker, P. R.
    Cherkaoui, K.
    Hurley, P. K.
    Piscator, J.
    Engström, O.
    Newcomb, S. B.
    Scaling potential and MOSFET integration of thermally stable Gd silicate dielectrics2009In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 86, no 7-9, p. 1642-1645Article in journal (Refereed)
    Abstract [en]

    We investigate the potential of gadolinium silicate (GdSiO) as a thermally stable high-k gate dielectric in a gate first integration scheme. There silicon diffuses into gadolinium oxide (Gd(2)O(3)) from a silicon oxide (SiO(2)) interlayer specifically prepared for this purpose. We report on the scaling potential based on detailed material analysis. Gate leakage current densities and EOT values are compatible with an ITRS requirement for low stand by power (LSTP). The applicability of this GdSiO process is demonstrated by fully functional silicon on insulator (SOI) metal oxide semiconductor field effect transistors (MOSFETs).

  • 8.
    Gudmundson, Peter
    et al.
    KTH, Superseded Departments, Solid Mechanics.
    Wikström, Adam
    KTH, Superseded Departments, Solid Mechanics.
    Stresses in thin films and interconnect lines2002In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 60, no 1-2, p. 17-29Article in journal (Refereed)
    Abstract [en]

    The mechanical behavior of thin films and interconnect lines is investigated. Firstly, theoretical models of thermal stress evolution in thin films and passivated or unpassivated lines are considered. Secondly, the effect of texture in a copper thin film with a columnar grain structure is studied from a theoretical point of view. The film consists of three different constituents with (111), (100) and randomly oriented texture. Global properties as well as local stress distributions are considered in detail within a thermoelastic framework. The results are in qualitative agreement with available experimental results. Implications with regards to plastic behavior are briefly discussed. Finally, the potential of the curvature measurement technique for experimental stress evaluation in thin films is considered for initially flat and curved substrate/film systems.

  • 9. Hansson, B. A. M.
    et al.
    Rymell, L.
    Berglund, M.
    Hertz, Hans M.
    KTH, Superseded Departments, Physics.
    A liquid-xenon-jet laser-plasma X-ray and EUV source2000In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 53, no 04-jan, p. 667-670Article in journal (Refereed)
    Abstract [en]

    We describe a laser-plasma soft-x-ray source based on a cryogenic-xenon liquid-jet target. The source is suitable for extreme ultraviolet (EUV) projection lithography and proximity x-ray lithography (PXL). Absolute calibrated spectra in the 1-2 nm range and uncalibrated spectra in the 9-15 nm range are obtained using a free-standing transmission grating and a CCD-detector.

  • 10. Heuser, M
    et al.
    Baus, M
    Hadam, B
    Winkler, O
    Spangenberg, B
    Granzner, R
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H
    Fabrication of wire-MOSFETs on silicon-on-insulator substrate2002In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 61-2, p. 613-618Article in journal (Refereed)
    Abstract [en]

    This paper describes the simulation and fabrication of N-type wire-MOSFETs with a multigate structure fabricated on silicon-on-insulator (SOI) material. Both simulations as well as experiments show that short channel effects (SCE) can be reduced by decreasing the channel width of the transistors below 100 nm. The triple-sided gate generates principally higher potential barriers in the channel, suppressing punch through effects significantly. (C) 2002 Elsevier Science B.V. All rights reserved.

  • 11.
    Holmberg, Anders
    et al.
    KTH, Superseded Departments, Physics.
    Rehbein, Stefan
    KTH, Superseded Departments, Physics.
    Hertz, Hans M.
    KTH, Superseded Departments, Physics.
    Nano-fabrication of condenser and micro zone plates for compact X-ray microscopy2004In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 73/74, p. 639-643Article in journal (Refereed)
    Abstract [en]

    We demonstrate nano-fabrication of high-aspect ratio and high-spatial frequency diffractive X-ray optics with high uniformity for use in a laser-plasma-based compact water-window X-ray microscope. The structures are fabricated on 50 nm thin Si3N4-membranes using a three-layer resist scheme and 30 keV e-beam lithography in combination with reactive ion etching and nickel electroplating. The process is developed on solely commercially available resists and instruments. As examples, we demonstrate fabrication of micro-zone plates with outermost linewidths of 30 nm and an uniform zone height of 160 nm, and a 4.5 mm diameter condenser zone plate with 50-60 nm lines, fabricated by using stitched fields.

  • 12.
    Hållstedt, Julius
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Zhen
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Edholm, Jonas
    Lu, J.
    Uppsala University, Ångström Laboratory.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A robust spacer gate process for deca-nanometer high-frequency MOSFETs2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 3, p. 434-439Article in journal (Refereed)
    Abstract [en]

    This paper, presents a robust spacer technology for definition of deca-nanometer gate length MOSFETs. Conformal deposition, selective anisotropic dry-etching and selective removal of sacrificial layers enabled patterning of an oxide hard mask with deca-nanometer lines combined with structures defined with I-line lithography on a wafer. The spacer gate technology produces negligible topographies on the hard mask and no residual particles could be detected on the wafer. The line-width roughness of 40 nm poly-Si gate lines was 4 nm and the conductance of 200 pm long lines exhibited a standard deviation of 6% across a wafer. nMOSFETs with 45 nm gate length exhibited controlled short-channel effects and the average maximum transconductance in saturation was 449 mu S/mu m with a standard deviation of 3.7% across a wafer. The devices exhibited a cut-off frequency above 100 GHz at a drain current of 315 mu A/mu m. The physical and electrical results show that the employed spacer gate technology is robust and can define deca-nanometer nMOSFETs with high yield and good uniformity.

  • 13.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Utilizing the superior etch stop quality of HfO 2 in the front end of line wafer scale integration of silicon nanowire biosensors2019In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 212, p. 13-20Article in journal (Refereed)
    Abstract [en]

    Silicon nanowire (SiNW) biosensors have received a special attention from the research community due to its ability to detect a range of species. The nano feature size of the SiNW has been exploited to fabricate small, low-cost, robust, portable, real-time read-out biosensors. These sensors are manufactured by two methods – top-down or bottom-up. Instead of the bottom-up method, the top-down approach is widely used due to its compatibility with complementary metal-oxide semiconductor (CMOS) process and scope of mass production. However, in the top-down method, the post fabrication microfluidic channel integration to access the SiNW test site remains complex and challenging. Since the nanosensor is expected to operate in a bio environment, it is essential to passivate the metal electrodes while pathways have to be made to access the test site. In this paper, we present a relatively easier method to access the SiNW test site without employing complex microfluidic channels while achieving leakage free passivation of metal electrodes and preserving the integrity of the nanosensor. This is accomplished in the last step of the manufacturing process by employing a lithography mask and reactive ion etching (RIE). HfO 2 integrated crystalline silicon nanosensors are manufactured using novel top-down front end of line (FEOL) sidewall transfer lithography (STL) process. HfO 2 acts as an etch stop layer while performing RIE in the last step to access the sensor test site. The 100 mm wafer scale results of 20 nm × 60 nm × 6 μm (H x W x L) p-type nanosensors shows an average I on /I off ≥ 10 5 with maximum turn-on voltage of −4 V and uniform subthreshold slope of 70 mV/dec. In comparison with sensors encapsulated with SiO 2 , the HfO 2 integrated nanosensors were found to improve the threshold voltage variation by 50%. Based on this work, the HfO 2 integrated SiNW demonstrates good stability for biosensing application.

  • 14.
    Juhasz, Robert
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Linnros, Jan
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Silicon nanofabrication by electron beam lithography and laser-assisted electrochemical size-reduction2002In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 61-62, p. 563-568Article in journal (Refereed)
    Abstract [en]

    Laser-assisted electrochemical size-reduction has been carried out on silicon nanostructures produced by electron beam lithography and reactive ion etching. We demonstrate the ability to reduce nanopillars down to 10 nm diameter while preserving shape, but also the possibility of preferential etching of different parts of the pillar by varying the applied bias voltage. Furthermore, the origin of the carriers responsible for the etching is discussed, and we note the presence of a 'dark' etching mechanism working in parallel with the normal dissolution reaction. Finally, the etching of shallow Si dots on a Si surface shows further localization of etching, with a different etching reaction taking place in the vicinity of the structures as opposed to the planar surface, far from the structures.

  • 15. Koliopoulou, S
    et al.
    Dimitrakis, P
    Goustouridis, D
    Chatzandroulis, S
    Normand, P
    Tsoukalas, D
    Radamson, Henry
    A Si/SiGe MOSFET utilizing low-temperature wafer bonding2005In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 78-79, p. 244-247Article in journal (Refereed)
    Abstract [en]

    A process scheme for the fabrication of a low temperature SiGe V-groove MOSFET is demonstrated. The transfer and output characteristics show promising results for the device performance. The source/drain resistance and the quality of the gate insulator/SiGe channel must be optimized for device operation improvement.

  • 16. Koliopoulou, S
    et al.
    Dimitrakis, P
    Goustouridis, D
    Normand, P
    Pearson, Christopher
    KTH.
    Petty, M C
    Radamson, Henry H
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tsoukalas, D
    Metal nano-floating gate memory devices fabricated at low temperature2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 4-9, p. 1563-1566Article in journal (Refereed)
    Abstract [en]

    In this communication, we report on the realization of low-temperature processed Electrically Erasable Programmable Read-Only Memory (EEPROM) like device with embedded gold nanoparticles. The realization is based on the fabrication of a V-groove SiGe Metal Oxide Semiconductor Field Effect Transistor (MOSFET), the functionalization of a gate oxide followed by self-assembly of gold nanoparticles and finally, the deposition of an organic insulator by Langmuir-Blodgett (LB) technique. Such structures were processed at a temperature lower than 400 degrees C. The electrical characteristics of the final hybrid Metal Insulator Semiconductor FET (MISFET) memory cells were evaluated in terms of memory window and program/erase voltage pulses. A model describing the memory characteristics, based on the electronic properties of the gate stack materials, is presented.

  • 17. Korkishko, Y. N.
    et al.
    Fedorov, V. A.
    Kostritskii, S. M.
    Alkaev, A. N.
    Maslennikov, E. I.
    Paderin, E. M.
    Apraksin, D. V.
    Laurell, Fredrik
    KTH, Superseded Departments, Physics.
    Proton exchanged LiNbO3 and LiTaO3 optical waveguides and integrated optic devices2003In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 69, no 04-feb, p. 228-236Article in journal (Refereed)
    Abstract [en]

    We show that proton exchanged LiNbO3 waveguides exhibit very complex structural chemistry. Seven HxLi1-xNbO3 and six HxLi1-xTaO3 crystallographic phases have been identified in PE LiNbO3 and LiTaO3 waveguides, respectively. A correlation is done between the electrooptical, nonlinear and photorefractive properties, the processing conditions and the refractive index changes of the waveguides. Some integrated optical devices have been realized.

  • 18. Lee, S. K.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Palmquist, J. P.
    Jansson, U.
    Low resistivity ohmic contacts on 4H-silicon carbide for high power and high temperature device applications2002In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 60, no 02-jan, p. 261-268Article in journal (Refereed)
    Abstract [en]

    We investigated titanium based ohmic contacts using co-evaporated epitaxial titanium carbide (TiC) on highly doped n(+)- and p(+)-type epilayers as well as Al ion implanted layers for high power and high temperature device application. Epitaxially grown TiC ohmic contacts on epilayers as well as Al implanted layers of 4H-SiC were formed by UHV co-evaporation with Ti and C-60 at low substrate temperature. The specific contact resistance (rho(C)) was as low as 5 x 10(-6), 2 x 10(-5), and 2 x 10(-5) Omegacm(2) for TiC contacts on n(+), on p(+) epilayer, and on Al implanted layer, respectively, using a linear TLM measurement. In addition to TiC, we also investigated TiW (weight ratio 30:70) ohmic contacts to p- and n-type 4H-SiC for the purpose of long-term reliability tests at high temperature. The average rho(C) of sputtered TiW contacts was 4 x 10(-5) for p(+) and n(+) epilayer. We also found that an evaporated top layer (Au or Pt) helps to protect from degradation of the contacts under long-term reliability tests with temperatures of up to 600degreesC in a vacuum chamber.

  • 19.
    Lemme, Max C.
    et al.
    AMO GmbH, AMICA, Aachen, Germany.
    Efavi, J. K.
    Mollenhauer, T.
    Schmidt, M.
    Gottlob, H. D. B.
    Wahlbrink, T.
    Kurz, H.
    Nanoscale TiN metal gate technology for CMOS integration2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 4-9, p. 1551-1554Article in journal (Refereed)
    Abstract [en]

    A TiN metal gate technology including essential natiostructuring process steps is investigated. Complex interdependencies of material deposition, nanolithography, nanoscale etching and post fabrication annealing are taken into account. First, a reactive sputter process has been optimized for plasma damage and stoichiometry. Then, a two step etch process that yields both anisotropy and selectivity has been identified. Finally, MOS-capacitors with TiN/SiO2 gate stacks fabricated with this technology have been exposed to rapid thermal annealing steps. TiN/SiO2 interfaces are chemically stable up to 800 degrees C and yield excellent CV and IV characteristics.

  • 20.
    Lemme, Max C.
    et al.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T.
    Gottlob, H.
    Henschel, W.
    Efavi, J.
    Welch, C.
    Kurz, H.
    Highly selective HBr etch process for fabrication of Triple-Gate nano-scale SOI-MOSFETs2004In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 73-74, no SI, p. 346-350Article in journal (Refereed)
    Abstract [en]

    New three-dimensional device concepts are considered necessary for the ultimate scaling of the gate length of metal-oxide-semiconductor field effect transistors (MOSFETs). Both Triple-Gate field effect transistors and FinFETs require a gate etch process with excellent selectivity over the gate oxide material. In this work, a highly selective, anisotropic gate etch process using HBr and O-2 as the reactive gases in an inductively coupled plasma reactive ion etch tool is described. Polysilicon thickness measurements have been taken to calculate etch rate and uniformity. Polysilicon wafers for each experimental condition were given different overetch times and SiO2 losses were plotted against time, with the gradient yielding the SiO2 etch rate. The optimized etch process yields excellent results for nanoscale polysilicon gates.

  • 21.
    Lemme, Max C.
    et al.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T
    Henschel, W
    Wahlbrink, T
    Heuser, M
    Baus, M
    Winkler, O
    Spangenberg, B
    Granzner, R
    Schwierz, F
    Kurz, H
    Influence of channel width on n- and p-type nano-wire-MOSFETs on silicon on insulator substrate2003In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 67-8, p. 810-817Article in journal (Refereed)
    Abstract [en]

    The fabrication and characterization of nanoscale n- and p-type multi-wire metal-oxide semiconductor field effect transistors (MOSFETs) with a triple gate structure on silicon-on-insulator material (SOI) is described in this paper. Experimental results are compared to simulation with special emphasis on the influence of channel width on the subthreshold behavior. Experiment and simulation show that the threshold voltage depends strongly on the wire width at dimensions below 100 urn. It is further shown that the transition from partial to full channel depletion is dependent on channel geometry. Finally, an increased on-current per chip area is demonstrated for triple-gate SOI MOSFETs compared to planar SOI devices. (C) 2003 Elsevier Science B.V. All rights reserved.

  • 22.
    Lindblom, Magnus
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Hertz, Hans M.
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Holmberg, Anders
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    SU8 plating mold for high aspect-ratio nickel zone plates2007In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 84, p. 1136-Article in journal (Refereed)
    Abstract [en]

    Nickel zone plates are fabricated by electrodeposition into a mold with high aspect ratio and narrow line width. This process requires high-mechanical stability of the mold to avoid pattern collapse in the plating bath. In the present paper we demonstrate how SU-8 can be used as plating mold material in a tri-layer resist to fabricate 35-nm half-pitch nickel gratings with an aspect ratio exceeding 11:1. To attain sufficient stability of the mold the SU-8 was cured by e-beam exposure with a dose of 25 mC/cm2 at 5-keV electron energy.

  • 23. Liu, Qingbo
    et al.
    Wang, Guilei
    Guo, Yiluan
    Ke, Xingxing
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Liu, Hong
    Zhao, Chao
    Luo, Jun
    Effects of carbon pre-germanidation implant into Ge on the thermal stability of NiGe films2015In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 133, p. 6-10Article in journal (Refereed)
    Abstract [en]

    In this work, the effects of carbon pre-germanidation implant into Ge on the properties of NiGe films were systematically investigated. NiGe films with carbon pre-germanidation implant to doses varying from 0 to 6 x 10(15) cm(-2) were characterized by means of sheet resistance measurement, X-ray diffraction (XRD), scanning electron microscopy (SEM), cross-sectional transmission electron microscope (X-TEM) and secondary ion mass spectroscopy (SIMS). The presence of C atoms is proved to significantly enhance the thermal stability of NiGe by about 100 degrees C as well as to change the preferred orientations of polycrystalline NiGe. The homogenous redistribution of C atoms within NiGe films and the segregation of C atoms at the NiGe/Ge interface is responsible for the improved thermal stability of NiGe films.

  • 24. Lundqvist, N.
    et al.
    Aberg, J.
    Nygren, S.
    Bjormander, C. A.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Effects of substrate bias and temperature during titanium sputter-deposition on the phase formation in TiSi22002In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 60, no 02-jan, p. 211-220Article in journal (Refereed)
    Abstract [en]

    The formation of titanium disilicide (TiSi2,) from Ti deposited using ionized metal plasma under different deposition conditions has been investigated. It is shown that deposition at elevated substrate temperature (450degreesC) enhances the formation of the low-resistivity C54 TiSi2, especially in patterned narrow lines. Grain-boundary footprint pictures obtained by atomic force microscopy indicate a larger grain-size distribution for the films deposited at higher substrate temperature. Deposition under substrate bias resulted in reduced contact resistivity. However, the use of substrate bias results in increased probability of bridging of silicide over the isolating spacers.

  • 25.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    Deng, Jian
    Zhao, Chao
    Li, Junfeng
    Wang, Wenwu
    Chen, Dapeng
    Wu, Dongping
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ye, Tianchun
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effects of carbon pre-silicidation implant into Si substrate on NiSi2014In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 120, p. 178-181Article in journal (Refereed)
    Abstract [en]

    In this work, the effects of carbon pre-silicidation implant into Si(1 0 0) substrate on NiSi were investigated. NiSi films with carbon pre-silicidation implant to different doses were characterized by means of sheet resistance measurements, X-ray diffraction, scanning electron microscopy (SEM), planar view transmission electron microscopy (TEM) and second ion mass spectroscopy (SIMS). The presence of C is found to indeed significantly improve the thermal stability of NiSi as well as tends to change the preferred orientations of polycrystalline NiSi. The homogeneously distributed C at NiSi grain boundaries and C peak at NiSi/Si interface is ascribed to the improved thermal stability of NiSi. More importantly, the dose of carbon pre-silicidation implant also plays a key role in the formation of NiSi, which is suggested not to exceed a critical value about 5 x 10(15) cm(-2) in practical application in accordance with the results achieved in this work.

  • 26.
    Luo, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Qiu, Zhi-Jun
    Deng, Jian
    Zhao, Chao
    Li, Junfeng
    Wang, Wenwu
    Chen, Dapeng
    Wu, Dongping
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ye, Tianchun
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Variation of Schottky barrier height induced by dopant segregation monitored by contact resistivity measurements2014In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 120, p. 174-177Article in journal (Refereed)
    Abstract [en]

    Change of contact resistivity (rho(c)) is monitored for evaluation of Schottky barrier height (SBH) variation induced by dopant segregation (DS). This method is particularly advantageous for metal-semiconductor contacts of small SBH, as it neither requires low-temperature measurement needed in current-voltage characterization of Schottky diodes nor is affected by reverse leakage current often troubling capacitance-voltage characterization. With PtSi contact to both n- and p-type diffusion regions, and the use of opposite or alike dopants implant into pre-formed PtSi films followed by drive-in anneal at different temperatures to induce DS at PtSi/Si interface, the formation of interfacial dipole is confirmed as the responsible cause for modification of effective SBHs thus the increase or decrease of rho(c). A tentative explanation for the change of contact resistivity based on interfacial dipole theory is provided in this work. Influences and interplay of interfacial dipole and space charge on effective SBH are also discussed.

  • 27.
    Marcinkevicius, Saulius
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Leon, R.
    Carrier capture and relaxation in quantum dot structures with different dot densities2000In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. feb-51, p. 79-83Article in journal (Refereed)
    Abstract [en]

    Carrier dynamics has been measured by time-resolved photoluminescence in self-assembled InGaAs/GaAs quantum dot structures with dot density of the order of 10(8) to 10(10) cm(2). The time of carrier transfer into a dot, which is in the region from 2 to 20 PS, has been found to decrease with increasing quantum dot density. The temperature and photoexcited carrier density dependencies of the carrier transfer times suggest that potential barriers at the barrier, wetting layer and quantum dot interfaces hinder carrier capture in low-density quantum dot structures.

  • 28. Mitrovic, I. Z.
    et al.
    Althobaiti, M.
    Weerakkody, A. D.
    Sedghi, N.
    Hall, S.
    Dhanak, V. R.
    Chalker, P. R.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interface engineering of Ge using thulium oxide: Band line-up study2013In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 109, p. 204-207Article in journal (Refereed)
    Abstract [en]

    This paper investigates the band line-up and optical properties (dielectric function) of Tm2O3/Ge gate stacks deposited by atomic layer deposition. X-ray photoelectron spectroscopy has been performed to ascertain the shallow core levels (Ge3d and Tm4d) in ultra-thin and bulk Tm2O3/Ge stacks as well as valence band maxima in Ge and bulk Tm2O3. The valence band offset of Tm2O3/Ge has been found to be 2.95 +/- 0.08 eV. Vacuum ultra violet variable angle spectroscopic ellipsometry studies reveal the indirect band gap nature of Tm2O3, with the value extracted from the Tauc method of 5.3 +/- 0.1 eV. A distinct absorption feature is observed at similar to 3.2 eV below the band gap of Tm2O3, and clearly distinguished from the Si and Ge critical points. A dielectric constant of 14 to 15 has been derived from the electrical measurements on 5 nm Tm2O3/epi Ge/Si gate stacks. The band line-up study of Tm2O3/Ge implies an acceptable barrier for holes (2.95 eV) and electrons (greater than 1.7 eV) for Ge MOSFET engineering.

  • 29. Moller, P.
    et al.
    Fredenberg, M.
    Dainese, M.
    Aronsson, C.
    Leisner, P.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Metal printing ECPR of copper interconnects down to 500 nm using - Electrochemical pattern replication2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 09-apr, p. 1410-1413Article in journal (Refereed)
    Abstract [en]

    Printing of copper patterns with dimensions from 100 mu m down to 500 nm lines and 280 run space was demonstrated using electrochemical pattern replication with a master electrode (template) having a pattern depth of 2500 nm. SEM measurements were done to measure the mean line width as well as CD variations on the master and the replicated copper lines. It was found that accurate replication of 500 nm thick metal patterns was enabled by the process and that CD variations in the master were dominating compared to the variations introduced by the electrochemical pattern transfer itself.

  • 30. Nazarov, A. N.
    et al.
    Gomeniuk, Y. V.
    Gomeniuk, Y. Y.
    Gottlob, H. D. B.
    Schmidt, M.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Czernohorsky, M.
    Osten, H. J.
    Charge trapping in ultrathin Gd2O3 high-k dielectric2007In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 84, no 9-10, p. 1968-1971Article in journal (Refereed)
    Abstract [en]

    Charge trapping in ultrathin high-k Gd2O3 dielectric leading to appearance of hysteresis in C-V curves is studied by capacitance-voltage and current-voltage techniques. It was shown that the large leakage current at a negative gate voltage causes the generation of the positive charge in the dielectric layer, resulting in the respective shift of the C-V curve. The capture cross-section of the hole traps is around 2 x 10(-20) cm(2). The distribution of the interface states was measured by conductance technique showing the concentration up to 7.5 x 10(12) eV(-1) cm(-2) near the valence band edge.

  • 31. Olsen, S. H.
    et al.
    Yana, L.
    Agaiby, R.
    Escobedo-Cousin, E.
    O'Neill, A. G.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lyutovich, K.
    Kasper, E.
    Claeys, C.
    Parker, E. H. C.
    Strained Si/SiGe MOS technology: Improving gate dielectric integrity2009In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 86, no 3, p. 218-223Article in journal (Refereed)
    Abstract [en]

    Strained Si is recognised as a necessary technology booster for the nanoelectronics regime. This work shows that high levels of stress attainable from globally strained Si/SiGe platforms can benefit gate leakage and reliability in addition to MOSFET channel mobility. Device self-heating due to the low thermal conductivity of SiGe is shown to be the dominating factor behind compromised performance against short channel strained Si/SiGe MOSFETs. Novel thin virtual substrates aimed at reducing self-heating effects are investigated. In addition to reducing self-heating effects, the thin Virtual substrates provide further improvements to gate oxide integrity, reliability and lifetime compared with conventional thick virtual substrates. This is attributed to tire lower surface roughness of the thin virtual substrates which arises due to the reduced interactions of strain-relieving misfit dislocations during thin Virtual substrate growth. Good agreement between experimental data and physical models is demonstrated, enabling gate leakage mechanisms to be identified. The advantages and challenges of using globally strained Si/SiGe to advance MOS technology are discussed.

  • 32.
    Parfeniukas, Karolis
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Rahomäki, Jussi
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Giakoumidis, Stylianos
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Seiboth, F.
    Wittwer, F.
    Schroer, C. G.
    Vogt, Ulrich
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Improved tungsten nanofabrication for hard X-ray zone plates2016In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 152, p. 6-9Article in journal (Refereed)
    Abstract [en]

    We present an improved nanofabrication method of high aspect ratio tungsten structures for use in high efficiency nanofocusing hard X-ray zone plates. A ZEP 7000 electron beam resist layer used for patterning is cured by a second, much larger electron dose after development. The curing step improves pattern transfer fidelity into a chromium hard mask by reactive ion etching using Cl2/O2 chemistry. The pattern can then be transferred into an underlying tungsten layer by another reactive ion etching step using SF6/O2. A 630 nm-thick tungsten zone plate with smallest line width of 30 nm was fabricated using this method and characterized. At 8.2 keV photon energy the device showed an efficiency of 2.2% with a focal spot size at the diffraction limit, measured at Diamond Light Source I-13-1 beamline.

  • 33. Persson, S.
    et al.
    Zhou, D.
    Zhang, Shi-Li
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Buffer design and insertion for global interconnections in 0.1 mu m technology2001In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 55, no 04-jan, p. 19-28Article in journal (Refereed)
    Abstract [en]

    This paper examines high-speed interconnection design in 0.1 mum technology from a simulation and modelling perspective. It is shown that using Cu metallisation in combination with a low-epsilon dielectric can reduce the minimum delay considerably, as compared to using Al metallisation with SiO2 as the inter-metal dielectric. Consequently, the use of Cu and a low-E dielectric leads to substantial saving of the surface area for buffers that are necessary to incorporate in order to maintain the improved performance when scaling down the device dimensions. As regard to buffer design and insertion, it is a good choice to allow the size of the cascaded inverters in each buffer to increase successively, and simultaneously to permit the size-ratio of two consecutive inverters to increase along the signal propagation direction in order to minimise power consumption and delay. Furthermore, in order to save the precious Si surface area, it is preferable not to drive an interconnection line at a speed unnecessarily higher than the specified speed. Therefore, in parallel with the search for better conductors and insulators as well as improved interconnection technologies, there is an urgent need to address the interconnection issue from the circuit design perspective.

  • 34. Qin, C.
    et al.
    Yin, H.
    Wang, G.
    Hong, P.
    Ma, X.
    Cui, H.
    Lu, Y.
    Meng, L.
    Zhong, H.
    Yan, J.
    Zhu, H.
    Xu, Q.
    Li, J.
    Zhao, C.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. University of Chinese Academy of Sciences, China.
    Study of sigma-shaped source/drain recesses for embedded-SiGe pMOSFETs2017In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 181, p. 22-28Article in journal (Refereed)
    Abstract [en]

    In this paper, the manufacturing process and formation mechanism study of sigma-shaped source/drain (S/D) recess in 28 nm node pMOSFETs and beyond have been presented. The mechanism of forming sigma-shaped recesses included a detailed analysis how to apply the dry and wet etching to shape the recess in a controlled way. The key factors in etching parameters were identified and optimized. Simulations of strain distributions in the channel region of the devices with selectively grown Si0.65Ge0.35 on different S/D recess shapes were carried out and the results were used as feedback to find out a trade-off between maximum strain in the channel region of the transistors and low short channel effect. Finally, guidelines for designing the shape of recess and for tuning the etching parameters for high mobility transistors have been proposed.

  • 35.
    Reinspach, Julia
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Lindblom, Magnus
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    von Hofsten, Olof
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Bertilson, Michael
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Hertz, Hans M.
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Holmberg, Anders
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Process development for improved soft X-ray zone plates2010In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 87, no 5-8, p. 1583-1586Article in journal (Refereed)
    Abstract [en]

    We demonstrate two nanofabrication methods which improve the diffraction efficiency of high-resolution soft X-ray nickel zone plates. First, pulse electroplating is shown to result in uniform diffraction efficiency over the entire zone-plate area. A resulting enhancement of the total efficiency of 20% compared to conventional DC plating was measured. Second, we demonstrate that a high-resolution cold development process can be combined with efficiency-enhancing dry etching into an underlying germanium film. We present 16 nm half-pitch gratings composed of 50 nm nickel on top of 50 nm germanium.

  • 36. Schmidt, M.
    et al.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Witters, T.
    Schram, T.
    Cherkaoui, K.
    Negara, A.
    Hurley, P. K.
    Impact of H-2/N-2 annealing on interface defect densities in Si(100)/SiO2/HfO2/TiN gate stacks2005In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 80, p. 70-73Article in journal (Refereed)
    Abstract [en]

    This paper reports on the influence of forming gas annealing (5%H-2/95%N-2) over the temperature range 350 degrees C-550 degrees C on the density of electrically active interface states in Si(100)/SiO2/HfO2/TiN gate stacks. Prior to forming gas annealing the distribution of interface states across the energy gap exhibits the electrical signature of the P-b0 dangling bond centre for the hydrogen free Si(100)/SiO2 interface. Forming gas annealing at 350 degrees C and 400 degrees C results in a reduction of the interface state density, with an increase in interface state density for forming gas anneals in the range 450 degrees C-550 degrees C. The effect of the cooling ambient for the forming gas anneal (N-2 or H-2/N-2) is also reported.

  • 37. Schmidt, M.
    et al.
    Mollenhauer, T.
    Gottlob, H. D. B.
    Wahlbrink, T.
    Efavi, J. K.
    Ottaviano, L.
    Cristoloveanu, S.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Nickel-silicide process for ultra-thin-body SOI-MOSFETs2005In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 82, no 3-4, p. 497-502Article in journal (Refereed)
    Abstract [en]

    A self-aligned nickel-silicide process to reduce parasitic source and drain resistances in ultra-thin-body silicon-on-insulator (UTB-SOI)-MOSFETs is investigated. An optimized nickel-silicide process sequence including nickel sputter deposition, rapid thermal diffusion and compatible silicon nitride (Si3N4) spacers is demonstrated in UTB-SOI n-MOSFETs. Transistor on-currents and source/drain-resistivity are extracted from output and transfer characteristics and compared for various device layer thicknesses from 80 nm down to 15 nm. On-currents are improved up to a factor of 100 for the thinnest transistors by the introduction of self-aligned NiSi. Front and back gate interface qualities are extracted to evaluate their potential impact on mobility and on-currents specifically for ultra-thin devices.

  • 38.
    Uhlén, Fredrik
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Nilsson, Daniel
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Rahomäki, Jussi
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Belova, Liubov
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics.
    Schroer, Christian G.
    Seiboth, Frank
    Holmberg, Anders
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Hertz, Hans M.
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Vogt, Ulrich
    KTH, School of Engineering Sciences (SCI), Applied Physics, Biomedical and X-ray Physics.
    Nanofabrication of tungsten zone plates with integrated platinum central stop for hard X-ray applications2014In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 116, p. 40-43Article in journal (Refereed)
    Abstract [en]

    We present a nanofabrication process for producing tungsten zone plates used in hard X-ray applications including a method of integrating a high-energy absorbing central stop with the optic. Tungsten zone plates are structured with electron-beam lithography and subsequent reactive ion etching. The central stop originates from a platinum wire. It is cut to dimension by focused ion beam etching, and afterwards attached to the zone plate center using ion beam induced deposition of platinum. A zone plate with integrated central stop will simplify alignment in hard X-ray scanning microscope arrangements where the 0th order light must be eliminated. The focusing performance of the zone plate device was investigated by scanning coherent diffraction imaging (ptychography) at 8 keV photon energy. We could demonstrate a diffraction-limited focus size of 53 nm diameter full-width-at-half-maximum. Tungsten zone plates with integrated central stops show promising results for use in hard X-ray microscopes at high-brightness facilities.

  • 39. Wagner, S.
    et al.
    Weisenstein, C.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kataria, S.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. University of Siegen, Germany.
    Graphene transfer methods for the fabrication of membrane-based NEMS devices2016In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 159, p. 108-113Article in journal (Refereed)
    Abstract [en]

    Graphene has extraordinary mechanical and electronic properties, making it a promising material for membrane based nanoelectromechanical systems (NEMS). Here, three methods for direct transfer of chemical vapor deposited graphene onto pre-fabricated micro cavity substrates were investigated and analyzed with respect to yield and quality of the free-standing membranes on a large-scale. An effective transfer method for layer-by-layer stacking of graphene was developed to improve the membrane stability and thereby increase the yield of completely covered and sealed cavities. The transfer method with the highest yield was used to fabricate graphene NEMS devices. Electrical measurements were carried out to successfully demonstrate pressure sensing as a possible application for these graphene membranes.

  • 40. Wahlbrink, T.
    et al.
    Kupper, D.
    Bolten, J.
    Moller, M.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Supercritical drying for high aspect-ratio HSQ nano-structures2007In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 84, no 5-8, p. 1045-1048Article in journal (Refereed)
    Abstract [en]

    The benefits of supercritical resist drying (SRD) technique using carbon dioxide (CO2) are investigated with respect to the resolution of dense patterns and the aspect ratio (AR) of nano-structures in rather thick HSQ layers. For double lines separated by a distance of 50 nm the maximum achievable AR is trebled using SRD processes compared to conventional nitrogen blow. The mechanical stability of resist structures is significantly improved by using SRI).

  • 41. Wahlbrink, T.
    et al.
    Kupper, D.
    Georgiev, Y. M.
    Bolten, J.
    Moller, M.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Supercritical drying process for high aspect-ratio HSQ nano-structures2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 4-9, p. 1124-1127Article in journal (Refereed)
    Abstract [en]

    Supercritical resist drying allows the fabrication of high aspect-ratio (AR) resist patterns. The potential of this drying technique to increase the maximum achievable AR and the resolution of the overall lithographic process is analyzed for hydrogen silsesquioxane (HSQ). The maximum achievable AR is doubled compared to conventional nitrogen blow drying. Furthermore, the resolution is improved significantly.

  • 42. Wahlbrink, T.
    et al.
    Mollenhauer, T.
    Georgiev, Y. M.
    Henschel, W.
    Efavi, J. K.
    Gottlob, H. D. B.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Niehusmann, J.
    Bolivar, P. H.
    Highly selective etch process for silicon-on-insulator nano-devices2005In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 78-79, no SI, p. 212-217Article in journal (Refereed)
    Abstract [en]

    Reactive ion etch (RIE) processes with HBr/O-2 chemistry are optimized for processing of functional nanostructures based on silicon and polysilicon. The etch rate, etch selectivity, anisotropy and sidewall roughness are investigated for specific applications. The potential of this process technology for nanoscale functional devices is demonstrated by MOSFETs with 12 nm gate length and optimized photonic devices with ultrahigh Q-factors.

  • 43. Wang, Guilei
    et al.
    Qin, Changliang
    Yin, Huaxiang
    Luo, Jun
    Duan, Ningyuan
    Yang, Ping
    Gao, Xingyu
    Yang, Tao
    Li, Junfeng
    Yan, Jiang
    Zhu, Huilong
    Wang, Wenwu
    Chen, Dapeng
    Ye, Tianchun
    Zhao, Chao
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Study of SiGe selective epitaxial process integration with high-k and metal gate for 16/14 nm nodes FinFET technology2016In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 163, p. 49-54Article in journal (Refereed)
    Abstract [en]

    In this study, the process integration of SiGe selective epitaxy on source/drain regions, for 16/14 nm nodes FinFET with high-k & metal gate has been presented. Selectively grown Si1-xGex (0.35 <= x <= 0.40) with boron concentration of 1 x 10(20) cm(-3) was used to elevate the source/drain of the transistors. The epi-quality, layer profile and strain amount of the selectively grown SiGe layers were also investigated by means of various characterizations. A series of prebaking experiments were performed for temperatures ranging from 740 to 825 degrees C in order to in situ clean the Si fins prior to the epitaxy. The results showed that the thermal budget needs to be limited to 780-800 degrees C in order to avoid any damages to the shape of Si fins but to remove the native oxide effectively which is essential for high epitaxial quality. The Ge content in SiGe layers on Si fins was determined from the strain measured directly by reciprocal space mappings using synchrotron radiation. Atomic layer deposition technique was applied to fill the gate trench with W using WF6 and B2H6 precursors. By such an AID approach, decent growth rate, low resistivity and excellent gap filling capability of W in pretty high aspect-ratio gate trench was realized. The as-fabricated FinFETs demonstrated decent electrical characteristics.

  • 44. Welch, C. C.
    et al.
    Goodyear, A. L.
    Wahlbrink, T.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T.
    Silicon etch process options for micro- and nanotechnology using inductively coupled plasmas2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 4-9, p. 1170-1173Article in journal (Refereed)
    Abstract [en]

    Silicon is an essential material in the fabrication of a continually expanding range of micro- and nano-scale opto-and microelectronic devices. The fabrication of many such devices requires patterning of the silicon but until recently exploitation of the technology has been restricted by the difficulty of forming the ever-smaller features and higher aspect ratios demanded. Plasma etching through a mask layer is a very useful means for fine-dimension patterning of silicon. In this work, several solutions are presented for the micro- and nano-scale etching of silicon using inductively coupled plasmas ICP.

  • 45.
    Wolborski, Maciej
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Bakowski, Mietek
    Schöner, Adolf
    Analysis of bulk and surface components of leakage current in 4H-SiC PiN MESA diodes2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 1, p. 75-78Article in journal (Refereed)
    Abstract [en]

    The leakage current in circular- and ring-shaped epitaxial 4H-SiC PiN mesa diodes with different size and periphery to area ratios was evaluated under the influence of the U-V irradiation and temperature in the range from room temperature (RT) to 250 degrees C. The surface leakage current component was found to dominate the reverse current characteristics and was found to be dependent on time and temperature both after reactive ion etching (RIE) of the diodes in the SF6/Ar gas mixture and after the UV irradiation. Charging of the surface states is believed to be responsible for the observed behavior. The LTV irradiation is believed to charge the surface positively. The drift of the I(V) characteristics is due to the trapping of the electrons neutralizing the positive donor states.

  • 46. Wu, D.
    et al.
    von Haartman, M.
    Seger, J.
    Tois, E.
    Tuominen, M.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ni-salicided CMOS with a poly-SiGe/Al2O3/HfO2/Al2O3 gate stack2005In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 77, no 1, p. 36-41Article in journal (Refereed)
    Abstract [en]

    Ni-salicided MOSFETs with a gate stack of ALD Al2O3/HfO2/Al2O3 high-x dielectric and poly-SiGe gate electrode were fabricated. The Si pMOSFETs with an EOT of 1.7 nm showed an expected gate leakage current reduction compared to SiO2 with the same EOT and a mobility around 20% lower than the universal curve. The strained SiGe surface-channel pMOSFETs with the same gate stack showed an enhanced current drive and hole mobility. The Si nMOSFETs, however, exhibited a degraded subthreshold slope and a lower current drive even compared with the Si pMOSFETs. Possible reasons for the degradation of Si nMOSFETs were discussed.

  • 47.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nickel-based contact metallization for SiGe MOSFETs: progress and challenges2003In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 70, no 04-feb, p. 174-185Article in journal (Refereed)
    Abstract [en]

    The Ni-based self-aligned silicide process has attracted a rapidly growing interest for contact metallization in Si technology, as the device dimensions are scaled down into the sub-100 nm regime. Incorporation of Ge in the electrodes of a MOSFET, i.e. gate and source/drain, in order to further enhance device performance, has made the study of Ni-Si1-xGex interactions a scientifically and technologically important issue. Among the different germanosilicides of Ni, NiSi1-uGeu (i.e. mono-germanosilicide, with u possibly different from x in the Si1 -xGex) is the most desirable phase due to its low specific resistivity of 12-25 muOmegacm. The focus of the present work is placed on issues concerning the phase and morphology stability of NiSi1-uGeu on single-crystal and polycrystalline Si1-xGex substrates. The related experimental data from our recent work are analysed with reference to two classics on the formation of silicides by d'Heurle [J. Mater. Res. 3 (1988) 167] and by d'Heurle and Gas [J. Mater. Res. 1 (1986) 205]. Influences of C and Pt on the stability of NiSi1-uGeu are also covered. The electrical properties of the NiSi1-uGeu-Si1-xGex contact are discussed referring to our latest experimental results.

  • 48.
    Zhang, Zhen
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT).
    Lu, Jun
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT).
    A novel self-aligned process for platinum silicide nanowires2006In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 83, no 11-12, p. 2107-2111Article in journal (Refereed)
    Abstract [en]

    Directly accessible, ultralong, uniform platinum silicide nanowires in PtSi and Pt2Si are mass-fabricated by combining a sidewall transfer lithography (STL) technology and a self-aligned silicide process. The STL technology is based on standard Si technology. The self-aligned platinum silicide (PtSix) process consists of two sequential steps in a single run: a silicidation step in N-2 to ensure a controllable silicide formation followed by an oxidation step in O-2 to form a reliable protective SiOx layer on top of the grown PtSix. The achieved nanowires are characterised by a low resistivity: 26 +/- 3 and 34 +/- 2 mu Omega cm for the Pt2Si- and PtSi-dominated nanowires.

  • 49. Zhou, J.
    et al.
    Li, P.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Huang, Y. P.
    Yang, P. Y.
    Bao, M. H.
    Ruan, G.
    Self-excited piezoelectric microcantilever for gas detection2003In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 69, no 1, p. 37-46Article in journal (Refereed)
    Abstract [en]

    Design, fabrication and results from theoretical and experimental studies on the self-excited piezoelectric microcantilever are presented in this paper. Theoretical studies have been carried out to design the microcantilever and have been extended to harmonic analysis using the finite element technique. Silicon microfabrication has been successfully completed to create microcantilever devices. Experimental studies have been performed to obtain the resonance frequencies. Applied as a mass-sensitive sensor, the microcantilever has a sensitivity of - 0.0024%/ppm and a minimum mass loading of 3.5 x 10(-9) g with the help of a zeolite sensitive layer to freon.

1 - 49 of 49
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