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  • 1.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Shah, Umer
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Somjit, Nutapong
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Oberhammer, Joachim
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires2015In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 5, no 1, p. 21-27Article in journal (Refereed)
    Abstract [en]

    In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.

  • 2. Halonen, E.
    et al.
    Viiru, T.
    Östman, K.
    Lopez Cabezas, Ana
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mantysalo, M.
    Oven sintering process optimization for inkjet-printed Ag Nanoparticle ink2013In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 3, no 2, p. 350-356Article in journal (Refereed)
    Abstract [en]

    This paper focuses on optimizing the oven sintering time and temperature for inkjet-printed silver nanoparticle ink on a polyimide substrate. Two basic aspects in fabricating conductor structures in printable electronics are conductivity and adhesion between the ink and the substrate material. Conductivity evolution during oven sintering is monitored with real-time resistance measurements at five different temperatures. Based on conductivity results, adhesion is evaluated at several time points at three temperatures. The higher the sintering temperature, the faster the structures reach their maximum conductivity values. The lowest conductor resistivity values are below 4 μΩcm. However, at each sintering temperature, it takes longer to reach the best adhesion values. In this paper, we aim to better understand oven sintering of silver nanoparticles and determine the best oven sintering conditions (temperature, time) for our particular ink-substrate combination. The results can be used to further define optimum sintering conditions for printed nanoparticle inks on polymer substrates.

  • 3.
    Zhang, Yafan
    et al.
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems. RISE Acreo AB, Sweden.
    Hammam, Tag
    Belov, Ilja
    Sjögren, Torsten
    Bakowski, Mietek
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
    Thermomechanical Analysis and Characterization of a Press-Pack Structure for SiC Power Module Packaging Applications2017In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 7, no 7, p. 1089-1100Article in journal (Refereed)
    Abstract [en]

    This paper presents an experimental methodology for the characterization of thermomechanical displacement and friction properties in a free-floating press-pack structure, and evaluation of the tensile stress on the semiconductor die through simulation of different mechanical and thermal loading conditions. The press-pack structure consists of a single silver-metallized (1 μm) silicon carbide die (400 μm) in contact with rhodium-coated (0.4 μm) molybdenum square plates. The thermomechanical displacements in the press-pack structure have been obtained using the digital image correlation technique, and the mean random error has been $± $0.1 μm, which is approximately 10 ppm of the measured length (10.5 mm). The developed experimental method has led to an analytical estimation of friction coefficients on the interfaces' silicon carbide-molybdenum and molybdenum-copper. The results demonstrate that the thin silver layer behaves as a solid film lubricant. A 2-D finite-element model representing the experimental setup has been implemented. The difference in displacement between measurement and simulation is less than 8%. Furthermore, the coinfluence of the design parameters on the thermomechanical performance of the stacked structure has been analyzed through simulations. Finally, design guidelines to reduce the tensile stress on the silicon carbide die have been proposed regarding free-floating press-pack power electronics packaging.

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