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  • 1. Andersson, J. Y.
    et al.
    Ericsson, P.
    Radamson, H. H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wissmar, Stanley
    Kolahdouz, Mohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    SiGe/Si quantum structures as a thermistor material for low cost IR microbolometer focal plane arrays2011In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 60, no 1, p. 100-104Article in journal (Refereed)
    Abstract [en]

    Uncooled microbolometer thermal infrared detector technology is presently revolutionizing the infrared technology field. Essential improvement of the cost/performance ratio would be achieved by microbolometer arrays with higher sensitivity, since this allows the use of simpler and less costly camera optics, which implies a lower cost of the complete IR camera. The sensitivity of the microbolometers depends critically on the signal-to-noise ratio of the integrated thermistor material, which is set by its temperature coefficient of resistance (TCR) and noise characteristics. In this work we have investigated the use of epitaxial silicon-germanium/silicon (SiGe/Si) quantum well (QW) structures as a thermistor material. Si0.68Ge0.32/Si QW structures typically give a TCR of 3.0%/K and low noise values. A calculation of the noise equivalent temperature NETD of a bolometer gives 25 mK using the following assumptions: f-number = 1, 30 Hz video frame rate for a 640 x 480 array, with a pixel size 25 x 25 mu m. Higher TCR values are foreseen for SiGe/Si quantum dot structures, and the noise is expected to be similar to the QW based structures.

  • 2. Ayala, Christopher L.
    et al.
    Grogg, Daniel
    Bazigos, Antonios
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fernandez-Bolanos, Montserrat
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Hagleitner, Christoph
    Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 113, p. 157-166Article in journal (Refereed)
    Abstract [en]

    Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

  • 3. Bertilsson, K.
    et al.
    Nilsson, H. E.
    Hjelm, M.
    Petersson, C. Sture
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kackell, P.
    Persson, Clas
    The effect of different transport models in simulation of high frequency 4H-SiC and 6H-SiC vertical MESFETs2001In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 45, no 5, p. 645-653Article in journal (Refereed)
    Abstract [en]

    A full band Monte Carlo (MC) study of the high frequency performance of a 4H-SiC short channel vertical MESFET is presented. The MC model used is based on data from a full potential band structure calculation using the local density approximation to the density functional theory. The MC results have been compared with simulations using state of the art drift-diffusion and hydrodynamic transport models. Transport parameters such as mobility, saturation velocity and energy relaxation time are extracted from MC simulations.

  • 4.
    Bertilsson, Kent
    et al.
    KTH, Superseded Departments, Electrum Laboratory.
    Harris, C
    Nilsson, H E
    Calculation of lattice heating in SiC RF power devices2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 12, p. 2103-2107Article in journal (Refereed)
    Abstract [en]

    Silicon carbide MESFET devices are suitable for high-speed and high-power applications. In this paper we are studying thermal effects in 4H-SiC RF power devices. The simulations are based on a combination of 2D device simulations for the electrical transport, and 3D thermal simulations for the lattice heating. We show that the method gives good accuracy, efficiency, flexibility and capacity dealing with tasks, where a 2D coupled electrical-thermal simulation is not sufficient. We also present an improvement of Roschke and Schwierz mobility model, based on Monte Carlo simulations for the temperature dependencies of the mobility parameters beta and v(sat).

  • 5.
    Bertilsson, Kent
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nilsson, Hans-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    The power of using automatic device optimization, based on iterative device simulations, in design of high-performance devices2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 10-11, p. 1721-1725Article in journal (Refereed)
    Abstract [en]

    An automatic optimization tool for semiconductor devices based on iterative device simulations is developed. The tool is used for optimization of different kinds of semiconductor devices using various performance measures. High performance optimization algorithms, both local and global, are used to achieve an efficient design in shortest possible time. In this paper the effects of different optimization algorithms, performance measures, and number of variables in the optimization are studied. Both the computational efficiency and the devices achieved with different performance measures are studied. We give a demonstration of the usefulness of this method in a comparison between different device topologies, which have been optimized for best performance.

  • 6.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Redjai Sani, Sohrab
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of GMR-based spin torque oscillators and CMOS circuitry2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 111, p. 91-99Article in journal (Refereed)
    Abstract [en]

    This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm2. The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies.

  • 7. Danielson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Forsberg, U.
    Janzen, E.
    Investigation of thermal properties in fabricated 4H-SiC high power bipolar transistors2003In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 47, no 4, p. 639-644Article in journal (Refereed)
    Abstract [en]

    Silicon carbide bipolar junction transistors have been fabricated and investigated. The transistors had a maximum current gain of approximately 10 times, and a breakdown voltage of 450 V. When operated at high power densities the device showed a clear self-heating effect, decreasing the current gain. The junction temperature was extracted during self-heating to approximately 150 degreesC, using the assumption that the current gain only depends on temperature. Thermal images of a device under operation were also recorded using an infrared camera, showing a significant temperature increase in the vicinity of the device. The device was also tested in a switched setup, showing fast turn on and turn off at 1 MHz and 300 V supply voltage. Device simulations have been used to analyze the measured data. The thermal conductivity is fitted against the self-heating, and the lifetime in the base is fitted against the measurement of the current gain.

  • 8. Danielsson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Linthicum, K.
    Thomson, D. B.
    Nam, O. H.
    Davis, R. F.
    The influence of band offsets on the IV characteristics for GaN/SiC heterojunctions2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 6, p. 827-835Article in journal (Refereed)
    Abstract [en]

    GaN/SiC heterojunctions can improve the performance considerably for bipolar transistors based on SiC technology. In order to fabricate such devices with a high current gain, the origin of the low turn-on voltage for the heterojunction has to be investigated, which is believed to decrease the minority carrier injection considerably. In this work heterojunction diodes are compared and characterized. For the investigated diodes, the GaN layers have been grown by molecular beam epitaxy (MBE), metal organic chemical vapor deposition, and hydride vapor phase epitaxy. A diode structure fabricated with MBE is presented here, whereas others are collected from previous publications. The layers were grown either with a low temperature buffer, AIN buffer, or without buffer layer. The extracted band offsets are compared and included in a model for a recombination process assisted by tunneling, which is proposed as explanation for the low turn-on voltage. This model was implemented in a device simulator and compared to the measured structures, with good agreement for the diodes with a GaN layer grown without buffer layer. In addition the band offset has been calculated from Schottky barrier measurements, resulting in a type II band alignment with a conduction band offset in the range 0.6-0.9 eV. This range agrees well with the values extracted from capacitance-voltage measurements.

  • 9.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 20-25Article in journal (Refereed)
    Abstract [en]

    This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.

  • 10.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 108, p. 24-29Article in journal (Refereed)
    Abstract [en]

    High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

  • 11.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Lutz, Josef
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Dynamic avalanche in Si power diodes and impact ionization at the nn(+) junction2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 3, p. 477-485Article in journal (Refereed)
    Abstract [en]

    The reverse recovery failure limit was measured with an optical technique for power diodes which sustain high levels of dynamic avalanche. Measurements and simulations indicate that these diodes withstand dynamic avalanche at the pn-junction and eventually fail as a result of a strongly inhomogeneous current distribution caused by the onset of impact ionisation at the diode nn(+) junction - a mechanism similar to the reverse bias second breakdown of bipolar transistors.

  • 12. Driussi, F.
    et al.
    Esseni, D.
    Selmi, L.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Grasby, T. J.
    Leadley, D. R.
    Mescot, X.
    On the electron mobility enhancement in biaxially strained Si MOSFETs2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 4, p. 498-505Article in journal (Refereed)
    Abstract [en]

    This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.

  • 13. Echtermeyer, T.
    et al.
    Gottlob, H. D. B.
    Wahlbrink, T.
    Mollenhauer, T.
    Schmidt, M.
    Efavi, J. K.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Investigation of MOS capacitors and SOI-MOSFETs with epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) electrodes2007In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 51, no 4, p. 617-621Article in journal (Refereed)
    Abstract [en]

    Electrical properties of metal oxide semiconductor (MOS) capacitors with gate stacks of epitaxial gadolinium oxide (Gd2O3) and titanium nitride (TiN) are studied. The influence of CMOS compatible rapid thermal annealing on these gate stacks is examined. Finally, n- and p-type MOS-field effect transistors (MOSFETs) on silicon on insulator (SOI) material with epitaxial Gd2O3 and TiN gate electrodes are presented.

  • 14. Engstrom, O.
    et al.
    Raeissi, B.
    Hall, S.
    Buiu, O.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Gottlob, H. D. B.
    Hurley, P. K.
    Cherkaoui, K.
    Navigation aids in the search for future high-k dielectrics: Physical and electrical trends2007In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 51, no 4, p. 622-626Article in journal (Refereed)
    Abstract [en]

    From experimental literature data on metal oxides combined with theoretical estimates, we present empirical relations for k-values and energy band offset values, that can be used in the search for gate dielectric materials fulfilling the needs of future CMOS generations. Only a few materials investigated so far have properties meeting the demands for k and energy band offset values in the development of CMOS down to 22 nm. (c) 2007 Elsevier Ltd. All rights reserved.

  • 15.
    Forsberg, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Wesström, Jan Olof
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Self-consistent simulations of mesoscopic devices operating under a finite bias2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 7, p. 1147-1154Article in journal (Refereed)
    Abstract [en]

    A novel numerical algorithm based on the solution of the two-dimensional effective mass equation for current-carrying scattering states in mesoscopic devices is developed. Using this while allowing for an energy dependent transmission matrix, the total charge density distribution based on all electrons injected into the device is calculated through integration over energy. By coupling this energy-resolved calculation of charge density distribution iteratively with a potential calculation a fully self-consistent calculation, which allows for accurate simulations of mesoscopic devices with arbitrary complex device geometries operating under a finite bias, is achieved. Thus it is possible to self-consistently study space charge effects in mesoscopic devices. The developed method is described and tested on a number of sample geometries.

  • 16. Gottlob, H. D. B.
    et al.
    Echtermeyer, T.
    Mollenhauer, T.
    Efavi, J. K.
    Schmidt, M.
    Wahlbrink, T.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Kurz, H.
    Czernohorsky, M.
    Bugiel, E.
    Osten, H. -J
    Fissel, A.
    CMOS integration of epitaxial Gd(2)O(3) high-k gate dielectrics2006In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 50, no 6, p. 979-985Article in journal (Refereed)
    Abstract [en]

    Epitaxial gadolinium oxide (Gd(2)O(3)) high-k dielectrics are investigated with respect to their CMOS compatibility in metal oxide semiconductor (MOS) capacitors and field effect transistors (MOSFETs). MOS capacitors with various gate electrodes are exposed to typical CMOS process steps and evaluated with capacitance voltage (CV) and current voltage (JV) measurements. The effects of high temperature processes on thermal stabilities of channel/dielectric and dielectric/gate electrode interfaces is studied in detail. A feasible CMOS process with epitaxial gate oxides and metal gate electrodes is identified and demonstrated by a fully functional n-MOSFET for the first time.

  • 17. Grahn, J. V.
    et al.
    Fosshaug, H.
    Jargelius, M.
    Jonsson, P.
    Linder, M.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Mohadjeri, B.
    Pejnefors, J.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Sanden, M.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Landgren, Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A low-complexity 62-GHz f(T) SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 3, p. 549-554Article in journal (Refereed)
    Abstract [en]

    A low-complexity SiGe heterojunction bipolar transistor process based on differential epitaxy and in situ phosphorus doped polysilicon emitter technology is described. Silane-based chemical vapor deposition at reduced pressure was used for low-temperature SiGe epitaxy. Following SiGe epitaxy, the process temperature budget was kept very low with 900 degrees C for 10 s as the highest temperature step. A very high current gain of almost 2000 and cut off frequency of 62 GHz were achieved for a uniform 12% Ge profile. The breakdown voltage BVCEO and forward Early voltage were equal to 2.9 and 6.5 V, respectively.

  • 18.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Palestri, P.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Selmi, L.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simulation of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo model2013In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 79, p. 172-178Article in journal (Refereed)
    Abstract [en]

    We present a simple and efficient approach to implement Schottky barrier contacts in a Multi-subband Monte Carlo simulator by using the subband smoothening technique to mimic tunneling at the Schottky junction. In the absence of scattering, simulation results for Schottky barrier MOSFETs are in agreement with ballistic Non-Equilibrium Green's Functions calculations. We then include the most relevant scattering mechanisms, and apply the model to the study of double gate Schottky barrier MOSFETs representative of the ITRS 2015 high performance device. Results show that a Schottky barrier height of less than approximately 0.15 eV is required to outperform the doped source/drain structure.

  • 19.
    Haralson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Device design for a raised extrinsic base SiGe bipolar technology2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 11-okt, p. 1927-1931Article in journal (Refereed)
    Abstract [en]

    The impact of emitter, inside spacer, and SIC lateral scaling on the AC and DC performance of a raised extrinsic base SiGe HBT has been investigated using the ISE TCAD simulation package and design of experiments methods. Strong first order effects for all three variables were observed while the interactions of the variables had a weaker effect. It was found that as the emitter size shrinks towards 0.1 mum the impact of changes to inside spacer and SIC width on the current gain increased. The response surface design led to an optimized simulated transistor featuring f(T) and f(MAX) values of 214 and 332 GHz, respectively.

  • 20.
    Hellberg, Per-Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, HH
    Kaplan, W
    Threshold voltage control for PMOSFETs using an undoped epitaxial Si channel and a p(+)-SixGe1-x gate2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 11, p. 2085-2088Article in journal (Refereed)
    Abstract [en]

    This paper examines experimentally the performance of PMOSFETs with an undoped epitaxial Si channel in combination with a p(+)-SixGe1-x gate electrode. The channel doping profiles were made using shallow As-implantation followed by selective epitaxy of undoped Si to different thicknesses of 40, 80 and 120 nm. The p(+)-SixGe1-x gate with different values of x was used to tailor the threshold voltage. The transconductance and saturation current were found to increase and the threshold voltage to decrease with increasing thickness of the undoped Si channel for the same gate material. Increasing Ge content in the p(+)-SixGe1-x gate resulted in an increased threshold voltage. Compared to the p(+)-Si gate, the threshold voltage was increased by 0.15 and 0.35 V with a p(+)-Si0.79Ge0.21 and p(+)-Si0.53Ge0.47 gate, respectively, independently of the Si channel thickness. Therefore, the use of a p(+)-SixGe1-x gate introduces an extra degree of freedom when designing the channel for high performance PMOSFETs.

  • 21.
    Henkel, Christoph
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Stoeger-Pollach, Michael
    Bethge, Ole
    Bertagnolli, Emmerich
    Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, p. 7-12Article in journal (Refereed)
    Abstract [en]

    The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3 x 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k LaxGeyOz, layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

  • 22. Henschel, W
    et al.
    Wahlbrink, T
    Georgiev, Y M
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T
    Vratzov, B
    Fuchs, A
    Kurz, H
    Kittler, M
    Schwierz, F
    Electrical characterization of 12 nm EJ-MOSFETs on SOI substrates2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 5, p. 739-745Article in journal (Refereed)
    Abstract [en]

    A dual gate metal oxide semiconductor field effect transistor (MOSFET) with electrically variable shallow junctions (EJ-MOSFET) has been fabricated on silicon on insulator (SOI) substrates. This kind of transistor allows testing the limits of scalability at relaxed process requirements. Transistor gate lengths down to 12 run have been structured by electron beam lithography (EBL) and specific etching processes. The coupling of the upper gate to the inner transistor is carefully investigated.

  • 23.
    Hillkirk, Leonardo M.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Dynamic surface temperature measurements in SiC epitaxial power diodes performed under single-pulse self-heating conditions2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 12, p. 2181-2189Article in journal (Refereed)
    Abstract [en]

    Semiconductor devices development, design and optimization require the use of computer simulation tools able to predict the entire device safe operating area (SOA), something that it is not always possible due to limitations in some of the physical models in predicting certain properties of device operation under extreme conditions (i.e. high carrier injection levels and high temperature). In order to improve our understanding of device operation under these extreme conditions experimental data of the dynamic IV characteristics and temperature time evolution and space distribution are required. The experimental data obtained are then used in the development of improved physical models and simulation tools. In this work, dynamic surface temperature measurements as a function of current pulse peak density and length were performed on SiC-PiN epitaxial power diodes. The measurements were carried out using an infrared (IR) microscope developed in our lab capable of measuring space and time surface temperature distributions in semiconductor devices operating under self-heating conditions [Solid State Electron 2001;45(12):2057]. The minimum detected spot size is 15 mum, while the signal raising time is detector limited to about 1 mus. The lowest detectable temperature increment is at least 10 degreesC over room temperature. Using this instrument, dynamic thermal phenomena in 4.5 kV SiC-PiN epitaxial power diodes [Mater Sci Forum 2001;353-356:727] subjected to I ms long 100-6000 A/cm(2) and 0.1-5 ms long 3000 A/cm(2) current pulses have been studied. The possibility of obtaining dynamic surface temperature information from SiC electronic devices operating under self-heating conditions with time constants in the order of ms is demonstrated.

  • 24.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon nanowires integrated with CMOS circuits for biosensing application2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 26-31Article in journal (Refereed)
    Abstract [en]

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  • 25.
    Johansson, Ted
    et al.
    KTH, School of Information and Communication Technology (ICT).
    Malin, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Norstrom, Hans
    Smith, Ulf
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of SOI-generated stress on BiCMOS performance2006In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 50, no 6, p. 935-942Article in journal (Refereed)
    Abstract [en]

    Two BiCMOS processes were adapted for SOI and the performance of the bipolar devices was studied. Differences in electrical parameters were observed, in particular the current gain, which processing or doping profiles could not explain, but correlated with observed stress in transistors. Simulation of the process flow with stress included revealed that stress was generated to a higher degree in the SOI wafers in the presence of deep trench isolation (DTI). Theoretical estimations and electrical simulations with and without stress yielded results consistent with observed data. Thus, we conclude that the observed differences are caused by process-induced in-plane biaxial stress.

  • 26.
    Kargarrazi, Saleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A study on positive-feedback configuration of a bipolar SiC high temperature operational amplifier2016In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 116, p. 33-37Article in journal (Refereed)
    Abstract [en]

    This paper reports on the design and implementation of an integrated operational amplifier in bipolar SiC, and elaborates on its operation in positive-feedback configuration. The opamp is studied in different feedback setups: closed-loop compensated amplifier, comparator with hysteresis (Schmitt trigger), and as a relaxation oscillator. Measurement results suggest a stable closed-loop opamp with similar to 40 dB gain, a Schmitt trigger with constant threshold levels over a wide temperature range, and a relaxation oscillator tested up to 540 kHz. All the setups were tested from 25 degrees C up to 500 degrees C.

  • 27.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Farniya, Ali Afshar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    The performance improvement evaluation for SiGe-based IR detectors2011In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 62, no 1, p. 72-76Article in journal (Refereed)
    Abstract [en]

    During recent years, single crystalline (Sc) SiGe has been recognized as a new low cost thermistor material for IR detection. In this study the effect of Ge content, pixel size and the Ni silicide on the performance of SiGe/Si thermistor material have been presented. The noise level was decreased for more than one order of magnitude when the Ni silicide layer was integrated below the metal contacts. The silicidation slightly improved TCR values for the detectors (+0.22%/K). However, increasing the Ge content had the most significant effect on the TCR. A statistical analysis was applied to evaluate the effect of each parameter. Using the factorial method, it was realized that decreasing the pixel size would enhance the TCR value.

  • 28.
    Kolahdouz, Mohammadreza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Maresca, Luca
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Riley, D.
    Wise, R.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    New method to calibrate the pattern dependency of selective epitaxy of SiGe layers2009In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 53, no 8, p. 858-861Article in journal (Refereed)
    Abstract [en]

    Selective epitaxial growth (SEG) of Si1-xGex layers on patterned substrates containing isolated, grouped and global chips has been investigated. The interaction between chips on a wafer was studied, and the results are explained by kinetic gas theory for CVD techniques. A test pattern was designed with a series of grouped chips to calibrate the pattern dependency of SEG (both growth rate and Ge content). The amount of exposed Si coverage on chips in the test pattern ranged between 0.05 and 37%. The layer profile of the calibration pattern was compared to profiles on wafers having a global chip design. A model was developed to estimate the Ge content on substrates with a global design.

  • 29. Koo, S. M.
    et al.
    Lee, S. K.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Electrical characteristics of metal-oxide-semiconductor capacitors on plasma etch-damaged silicon carbide2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 9, p. 1375-1380Article in journal (Refereed)
    Abstract [en]

    The characteristics of metal-oxide-semiconductor (MOS) capacitors formed on inductively coupled plasma (ICP) etch-damaged SiC have been investigated. MOS capacitors were prepared by dry-oxidation on ICP-etch-damaged n- and p-type. 6H- and 4H-SiC. The effect of a sacrificial oxidation treatment on the damaged surfaces has also been examined. Capacitance-voltage and current-voltage measurements of these capacitors were performed and referenced to those of simultaneously prepared control samples without etch damage. The effective interface densities (N-IT) and fixed oxide charges (Q(V)) of etch-damaged samples have been found to increase while the breakdown field strength (E-BD) of the oxide decreases. The barrier height (phib) at the SiC-SiO2, interface, determined from a Fowler-Nordheim analysis, decreased for MOS capacitors on etch-damaged surfaces. It has been found that a sacrificial oxidation treatment can improve the electrical characteristics of MOS capacitors on etch-damaged SiC.

  • 30. Lee, S. K.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Aberg, I.
    Magnusson, M. H.
    Deppert, K.
    Wernersson, L. E.
    Samuelson, L.
    Litwin, A.
    Reduction of the Schottky barrier height on silicon carbide using Au nano-particles2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 9, p. 1433-1440Article in journal (Refereed)
    Abstract [en]

    By the incorporation of size-selected Au nano-particles in Ti Schottky contacts on silicon carbide, we could observe considerably lower the barrier height of the contacts. This result could be obtained for both n- and p-type Schottky contacts using current-voltage and capacitance voltage measurements. For n-type Schottky contacts, we observed reductions of 0.19-0.25 eV on 4H-SiC and 0.15-0.17 eV on 6H-SiC as compared with particle-free Ti Schottky contacts. For p-type SiC, the reduction was a little lower with 0.02-0.05 eV on 4H- and 0.10-0.13 eV on 6H-SiC. The reduction of the Schottky barrier height is explained using a model with enhanced electric field at the interface due to the small size of the circular patch and the large difference of the barrier height between Ti and Au.

  • 31. Lee, S. K.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Palmquist, J. P.
    Hogberg, H.
    Jansson, U.
    Low resistivity ohmic titanium carbide contacts to n- and p-type 4H-silicon carbide2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 7, p. 1179-1186Article in journal (Refereed)
    Abstract [en]

    Low resistivity Ohmic contacts of epitaxial titanium carbide to highly doped n- (1.3 x 10(19) cm(-3)) and p- (>10(20) cm(-3)) type epilayer on 4H-SiC were investigated. The titanium carbide contacts were epitaxially grown using coevaporation with an e-beam for Ti and a Knudsen cell for C-60 in a UHV system. A comparison of epitaxial evaporated Ti Ohmic contacts on p(+) epilayer of 4H-SiC is also given. The as-deposited TiC Ohmic contacts showed a good Ohmic behavior and the lowest contact resistivity (rho(C)) was 7.4 x 10(-7) Ohm cm(2) at 200 degrees C for n-type, and 1.1 x 10(-4) Ohm cm(2) at 25 degrees C for p-type contacts. Annealing at 950 degrees C did not improve the Ohmic contact to n-type 4H-SiC, but instead resulted in an increase in rho(C) to 4.01 x 10(-5) Ohm cm(2) at 25 degrees C. In contrast to n-type, after annealing at 950 degrees C the specific rho(C) for p-type SiC reached its lowest value of 1.9 x 10(-5) Ohm cm(2) at 300 degrees C. Our results indicate that co-evaporated TiC contacts to n- and p-type epilayers of 4H-SiC should not require a higher post-annealing temperature, contrary to earlier works. Material characteristics, utilizing X-ray diffraction, Low energy electron diffraction, Rutherford backscattering spectrometry, transmission electron microscopy, and X-ray photoelectron spectroscopy measurements are also discussed.

  • 32.
    Lemme, Max C.
    et al.
    AMO GmbH, AMICA, Aachen, Germany.
    Echtermeyer, T. J.
    Baus, M.
    Szafranek, B. N.
    Bolten, J.
    Schmidt, M.
    Wahlbrink, T.
    Kurz, H.
    Mobility in graphene double gate field effect transistors2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 4, p. 514-518Article in journal (Refereed)
    Abstract [en]

    In this work, double-gated field effect transistors manufactured from monolayer graphene are investigated. Conventional top-down CMOS-compatible processes are applied except for graphene deposition by manual exfoliation. Carrier mobilities in single- and double-gated graphene field effect transistors are compared. Even in double-gated graphene FETs, the carrier mobility exceeds the universal mobility of silicon over nearly the entire measured range. At comparable dimensions, reported mobilities for ultra-thin body silicon-on-insulator MOSFETs cannot compete with graphene FET values. (c) 2007 Elsevier Ltd. All rights reserved.

  • 33.
    Lemme, Max C.
    et al.
    AMO GmbH, AMICA, Aachen, Germany.
    Mollenhauer, T.
    Henschel, W.
    Wahlbrink, T.
    Baus, M.
    Winkler, O.
    Granzner, R.
    Schwierz, F.
    Spangenberg, B.
    Kurz, H.
    Subthreshold behavior of triple-gate MOSFETs on SOI material2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 4, p. 529-534Article in journal (Refereed)
    Abstract [en]

    The fabrication of n-type multi-wire MOSFETs on SOI material with triple-gate structures is presented. The output and transfer characteristics of devices with a gate length of 70 nm and a MESA width of 22 nm demonstrate clearly the suppression of short channel effects (SCE). In addition, these triple-gate structures are compared with planar SOI devices of comparable dimensions. The influence of biasing the substrate (back gate) is analyzed and compared to simulation data.

  • 34. Linder, M.
    et al.
    Ingvarson, F.
    Jeppson, K. O.
    Grahn, J. V.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    On DC modeling of the base resistance in bipolar transistors2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 8, p. 1411-1418Article in journal (Refereed)
    Abstract [en]

    The total base resistance R-BTot constitutes a crucial parameter in modeling bipolar transistors. The significant physical effects determining R-BTot are current crowding and conductivity modulation in the base, both causing reduction of R-BTot With increasing base current I-B. In this paper, it is shown that the reduction of R-BTot(I-B) With increasing I-B is directly related to the physical effect dominating in the base. A new model for R-BTot(I-B) is presented where a parameter alpha is introduced to account for the contributions of current crowding and conductivity modulation in the base. Theoretically, alpha is equal to 0.5 when conductivity modulation is dominant and close to 1.0 when current crowding is the most significant effect. This was verified by measurements and simulations using a distributed transistor model which accounts for the lateral distribution of the base current and the stored base charge. The model proposed for R-BTot(I-B) is very suitable for compact transistor modeling since it is given in a closed form expression handling both current crowding and conductivity modulation in the base. An accurate extraction procedure of the model parameters is also presented.

  • 35. Luryi, Serge
    et al.
    Semyonov, Oleg
    Subashiev, Arsen
    Abeles, Joseph
    Chan, Winston
    Shellenbarger, Zane
    Metaferia, Wondwosen
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Semiconductor Materials, HMA.
    Lourdudoss, Sebastian
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Semiconductor Materials, HMA.
    Effects of thermal treatment on radiative properties of HVPE grown InP layers2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 95, p. 15-18Article in journal (Refereed)
    Abstract [en]

    Radiative efficiency of highly luminescent bulk InP wafers severely degrades upon heat treatment involved in epitaxial growth of quaternary layers and fabrication of photodiodes on the surface. This unfortunate property impedes the use of bulk InP as scintillator material. On the other hand, it is known that thin epitaxial InP layers, grown by molecular beam epitaxy (MBE) or metal-organic chemical vapor deposition (MOCVD), do not exhibit any degradation. These layers, however, are too thin to be useful in scintillators. The capability of hydride vapor phase epitaxy (HVPE) process to grow thick bulk-like layers in reasonable time is well known, but the radiative properties of HVPE InP layers are not known. We have studied radiative properties of 21 mu m thick InP layers grown by HVPE and found them comparable to those of best luminescent bulk InP virgin wafers. In contrast to the bulk wafers, the radiative efficiency of HVPE layers does not degrade upon heat treatment. This opens up the possibility of implementing free-standing epitaxial InP scintillator structures endowed with surface photodiodes for registration of the scintillation. (C) 2014 Elsevier Ltd. All rights reserved.

  • 36. Ma, P. X.
    et al.
    Linder, M.
    Sanden, M.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Chang, M. C. F.
    An analytical model for space-charge region capacitance based on practical doping profiles under any bias conditions2001In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 45, no 1, p. 159-167Article in journal (Refereed)
    Abstract [en]

    An analytical model is presented For quasi-static capacitance of the space-charge region in a p-n junction. The model is valid for realistic junction doping profiles under any bias conditions. It consists of local models in three bias regions. For the high-reverse bias region, a novel analytical model is derived. For the moderate-bias region, an empirical model commonly used in SPICE is adopted. Finally, for the high-forward bias region, the junction profiles are approximated by linearly-graded junctions. Existing analytical models are then modified appropriately to characterize both high-injection and heavy-doping effects for advanced bipolar transistors. Compared to previously developed analytical models or existing empirical models, as well as numerical simulation results, the analytical model presented here shows an improved accuracy and therefore provides a better tool For both device and circuit simulations.

  • 37.
    Malm, B. Gunnar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grahn, J. V.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Influence of transient enhanced diffusion of the intrinsic base dopant profile on SiGeHBT DC and HF characteristics2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 10, p. 1747-1752Article in journal (Refereed)
    Abstract [en]

    The influence of transient enhanced boron out-diffusion from the intrinsic base, caused by excess silicon interstitials created during the extrinsic base implantation, has been investigated for a non-selective SiGe HBT process. Devices with different designs of the extrinsic base region were fabricated, where some designs allowed part of the epitaxial base to be implanted with a high boron dose, hereby increasing the number of silicon interstitials close to the intrinsic device. These devices showed a marked degradation of DC characteristics and HF performance. 2D-device simulations were used to investigate the sensitivity in DC and HF parameters to vertical base profile changes. Good agreement was obtained between measured and simulated DC and HF characteristics.

  • 38.
    Malm, B. Gunnar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Johansson, T.
    Arnborg, T.
    Norstrom, H.
    Grahn, J. V.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Implanted collector profile optimization in a SiGeHBT process2001In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 45, no 3, p. 399-404Article in journal (Refereed)
    Abstract [en]

    Optimization of implanted collector doping profiles for a high-speed, low-voltage SiGe HBT process has been investigated experimentally and by device simulations. A low-energy antimony implantation has been combined with a standard selectively implanted collector using phosphorous, to achieve improved control of the collector doping profile. The simulations indicate that the narrow n-type doping peak formed by the antimony implantation allows the cut-off frequency f(T) to be increased without degrading the collector emitter breakdown voltage BVCEO. The fabricated devices demonstrate a highest f(T) of 60 GHz. Depending on the collector profile BVCEO values between 1.5 and 2 V were obtained.

  • 39.
    Malm, B. Gunnar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Mixed mode circuit and device simulation of RF harmonic distortion for high-speed SiGeHBTs2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 10, p. 1567-1571Article in journal (Refereed)
    Abstract [en]

    Mixed mode circuit and device simulation has been used to investigate the linearity properties-harmonic distortion of high-speed low voltage SiGe heterojunction bipolar transistors (HBTs). The simulation test-circuit included the active device, modeled by finite element simulation, as well as passive elements in a SPICE circuit for DC-feed and AC-coupling of the RF-signal. Different Ge-profiles for reduced harmonic distortion have been investigated and compared to a conventional high-speed graded Ge-profile. To find an optimized Ge-profile for RF-applications other figure-of-merits, such as maximum cut-off frequency and minimum noise figure were also simulated. Using the same mixed mode simulation approach the design of the epitaxial collector doping profile for high breakdown voltage, high cut-off frequency and reduced harmonic distortion was investigated.

  • 40. Moschetti, G.
    et al.
    Abbasi, M.
    Nilsson, P. -Å
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Desplanque, L.
    Wallart, X.
    Grahn, J.
    True planar InAs/AlSb HEMTs with ion-implantation technique for low-power cryogenic applications2013In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 79, p. 268-273Article in journal (Refereed)
    Abstract [en]

    In this paper, we report the room-temperature and cryogenic properties of true planar 110 nm InAs/AlSb HEMTs fabricated with Ar-ion isolation technology. Device isolation is generally improved and is in particular increased by four orders of magnitude at 6 K compared to 300 K. This results in improved drain current saturation, lower gate leakage current and 23% higher peak transconductance. The RF performance is significantly improved as well, with 47% higher fT (162 GHz) and 72% higher fmax (155 GHz) at the low drain voltage of 0.1 V, compared to room temperature. The overall performance of the fabricated devices shows the suitability of ion implantation for the device isolation at cryogenic temperature. Furthermore, the excellent stability against oxidation and truly planar structure of these devices demonstrate great potential for highly integrated cryogenic millimeter-wave circuits in InAs/AlSb technology with ultra-low power consumption.

  • 41.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    ALD high-k layer grating couplers for single and double slot on-chip SOI photonics2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, p. 58-63Article in journal (Refereed)
    Abstract [en]

    State of the art grating couplers for horizontal single and double slot waveguides are presented; in these devices the input signal is transmitted from a single mode optical fiber to silicon on insulator slot waveguide. In the waveguides, atomic layer deposited (ALD) high-k dielectrics form the low refractive index slot. It is demonstrated that a fully etched design combined with precision of ALD result in highly reproducible devices with theoretical efficiency variations less than 1%. Devices have a peak calculated coupling efficiency of 24% at 1.55 mu m. In order to achieve an optimal design, optical properties of high-k films are studied by spectroscopic ellipsometry. Measured refractive indices show variations from reference values, originated from film variation in densities. Chips with a test slot material are fabricated and the optical efficiency of the couplers is characterized. The maximum measured coupling efficiency of the couplers is 18.5%.

  • 42.
    Olyaei, Maryam
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Low-Frequency Noise in High-k LaLuO3/TiN MOSFETs2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 78, no SI, p. 51-55Article in journal (Refereed)
    Abstract [en]

    Low-frequency noise (LFN) characterization of high-k LaLuO3/TiN nMOS transistors is presented. The experimental results including the noise spectrum and normalized power noise density and mobility are reported. The noise results were successfully modeled to the correlated number and mobility fluctuation noise equation. High-k dielectric devices show lower mobility and roughly one to two orders of magnitude higher low-frequency noise which is comparable to the hafnium based oxide layers. The implementation of higher-k LaLuO3 seems to be a suitable candidate to the trade-off between equivalent oxide thickness scaling and low frequency noise.

  • 43. Persson, Clas
    et al.
    Lindefelt, U.
    Sernelius, B. E.
    Plasma-induced band edge shifts in 3C-, 2H-, 4H-, 6H-SiC and Si2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 3, p. 471-476Article in journal (Refereed)
    Abstract [en]

    Plasma-induced energy shifts of the conduction band minimum and of the valence band maximum have been calculated for 3C-, 2H-, 4H-, 6H-, 6H-SiC and Si. The resulting narrowing of the fundamental band gap and of the optical band gap are presented. The method utilized is based on a zero-temperature formalism within the random phase approximation. Electron-electron, hole-hole, electron-hole, electron-optical phonon and hole-optical phonon interactions have been taken into account. The calculations are based on band structure data from a relativistic, full-potential band structure calculation.

  • 44. Persson, S
    et al.
    Hellberg, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A charge sheet model for MOSFETs with an abrupt retrograde channel - Part I. Drain current and body charge2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 12, p. 2209-2216Article in journal (Refereed)
    Abstract [en]

    Analytical solutions to drain current, depletion and inversion charges for MOSFETs with an ideally abrupt retrograde doping profile in the channel are derived based on the charge sheet model. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations; the modeling and simulation results are in excellent agreement. It is shown that the inclusion of an intrinsic surface layer in the channel causes a voltage shift in the drain current, in accordance with experimental observations. For the depletion charge, an analytical expression principally identical to that for the uniformly doped body case is found with a simple replacement of the surface potential, psi(s), by the potential at the interface between the intrinsic surface layer and the doped substrate, psi(xi).

  • 45. Persson, S
    et al.
    Hellberg, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A charge sheet model for MOSFETs with an abrupt retrograde channel - Part II. Charges and intrinsic capacitances2002In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 46, no 12, p. 2217-2225Article in journal (Refereed)
    Abstract [en]

    The 16 intrinsic capacitance components related to the gate, source, drain and depletion charges are examined for MOSFETs with an ideally abrupt retrograde doping profile in the channel, based on the analytical solutions for the drain current and body charge in the preceding paper. Though lengthy and complex in their final mathematical expressions, analytical solutions for the capacitances can be obtained. The validity of the analytical solutions is confirmed by comparing the modeling results with simulation data obtained using numerical calculations. The inclusion of an intrinsic surface layer in the channel merely causes a simple voltage shift for the capacitances that are not associated with the depletion charge or body bias, similarly to the variation of the drain current shown in the preceding paper. For the capacitances that are related to the depletion charge or body bias, there is not only a parallel voltage shift with an amount commensurate to the shift in drain current as well as in the other capacitances, but also a decrease in their values. This decrease depends on the thickness of the intrinsic surface layer and it amounts to 25% for a surface layer of 30 nm thickness.

  • 46. Persson, S.
    et al.
    Wu, D.
    Hellström, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Quantifying hole mobility degradation in pMOSFETs with a strained-Si0.7Ge0.3 surface-channel under an ALD TiN/Al2O3/HfAlOx/Al2O3 gate stack2004In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 48, no 5, p. 721-729Article in journal (Refereed)
    Abstract [en]

    An appreciable mobility enhancement up to 35% is found in p-channel MOSFETs with a stramed-Si0.7Ge0.3 surface-channel under an ALD TiN/Al2O3/HfAlOchi/Al2O3 gate stack, as compared to a Si-channel reference transistor under an identical gate stack. A distorted effective mobility curve with a slow mobility roll-off at low vertical electric field is however extracted for the Si0.7Ge0.3 devices following the standard split-CV measurement procedure. A high density of interface traps on the order of 10(12) cm(-2) eV(-1) is found in these Si0.7Ge0.3 devices using charge-pumping measurements. Thus, this distortion is attributed partly to trapping of a significant fraction of the inversion carriers at the interface between the high-kappa dielectrics and the Si0.7Ge0.3 channel, thus defeating the validity of the usual formulation for mobility extraction. By taking into account the trapped carriers that are detectable by the split-CV measurement but do not contribute to the drain conductance, a corrected effective mobility curve is obtained. The distortion of the effective mobility curve is nonetheless mainly due to mobility degradation as a result of Coulomb scattering of the mobile channel carriers by the charged interface defects, i.e. charged traps or trapped carriers that remain charged.

  • 47. Qin, Changliang
    et al.
    Wang, Guilei
    Hong, Peizhen
    Liu, Jinbiao
    Yin, Huaxiang
    Yin, Haizhou
    Ma, Xiaolong
    Cui, Hushan
    Lu, Yihong
    Meng, Lingkuan
    Xiang, Jinjuan
    Zhong, Huicai
    Zhu, Huilong
    Xu, Qiuxia
    Li, Junfeng
    Yan, Jian
    Zhao, Chao
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22 nm all-last high-k/metal-gate pMOSFETs2016In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 123, p. 38-43Article in journal (Refereed)
    Abstract [en]

    In this paper, the technology of recessed embedded SiGe (e-SiGe) source/drain (S/D) module is optimized for the performance enhancement in 22 nm all-last high-k/metal-gate (HK/MG) pMOSFETs. Different Si recess-etch techniques were applied in S/D regions to increase the strain in the channel and subsequently, improve the performance of transistors. A new recess-etch method consists of a two-step etch method is proposed. This process is an initial anisotropic etch for the formation of shallow trench followed by a final isotropic etch. By introducing the definition of the upper edge distance (D) between the recessed S/D region and the channel region, the process advantage of the new approach is clearly presented. It decreases the value of D than those by conventional one-step isotropic or anisotropic etch of Si. Therefore, the series resistance is reduced and the channel strain is increased, which confirmed by the simulation results. The physical reason of D reducing is analyzed in brief. Applying this recess design, the implant conditions for S/D extension (SDE) are also optimized by using a two-step implantation of BF2 in SiGe layers. The overlap space between doping junction and channel region has great effect on the device's performance. The designed implantation profile decreases the overlap space while keeps a shallow junction depth for a controllable short channel effect. The channel resistance as well as the transfer ID-VG curves varying with different process conditions are demonstrated. It shows the drive current of the device with the optimized SDE implant condition and Si recess-etch process is obviously improved. The change trend of on-off current distributions extracted from a series of devices confirmed the conclusions. This study provides a useful guideline for developing high performance strained PMOS SiGe technology.

  • 48. Qin, Changliang
    et al.
    Wang, Guilei
    Kolahdouz, M.
    Luo, Jun
    Yin, Huaxing
    Yang, Ping
    Li, Junfeng
    Zhu, Huilong
    Chao, Zhao
    Ye, Tianchun
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Impact of pattern dependency of SiGe layers grown selectively in source/drain on the performance of 14 nm node FinFETs2016In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 124, p. 10-15Article in journal (Refereed)
    Abstract [en]

    A complete mapping of 14 nm FinFETs performance over 200 mm wafers was performed and the pattern dependency of SiGe selective growth was calculated using an empirical kinetic molecule model for the reactant precursors. The transistor structures were analyzed by conventional characterization tools and their performance was simulated by considering the process related variations. The applied model presents for the first time a powerful tool for transistor community to predict the SiGe profile and strain modulating over a processed wafer, independent of wafer size.

  • 49. Raeissi, B.
    et al.
    Piscator, J.
    Engstroem, O.
    Hall, S.
    Buiu, O.
    Lemme, Max C.
    AMO GmbH, AMICA, Aachen, Germany.
    Gottlob, H. D. B.
    Hurley, P. K.
    Cherkaoui, K.
    Osten, H. J.
    High-k-oxide/silicon interfaces characterized by capacitance frequency spectroscopy2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 9, p. 1274-1279Article in journal (Refereed)
    Abstract [en]

    Electron capture into insulator/silicon interface states is investigated for high-k dielectrics of Gd2O3 prepared by molecular beam epitaxy (MBE) and atomic layer deposition (ALD), and for HfO2 prepared by reactive sputtering, by measuring the frequency dependence of Metal Oxide Semiconductor (MOS) capacitance. The capture cross sections are found to be thermally activated and to increase steeply with the energy depth of the interface electron states. The methodology adopted is considered useful for increasing the understanding of high-k-oxide/silicon interfaces.

  • 50. Schmidt, M.
    et al.
    Lemme, Max C.
    Department of Physics, Harvard University.
    Gottlob, H. D. B.
    Driussi, F.
    Selmi, L.
    Kurz, H.
    Mobility extraction in SOI MOSFETs with sub 1 nm body thickness2009In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 53, no 12, p. 1246-1251Article in journal (Refereed)
    Abstract [en]

    In this work we discuss limitations of the split-CV method when it is used for extracting carrier mobilities in devices with thin silicon channels like FinFETs, ultra thin body silicon-on-insulator (UTB-SOI) transistors and nanowire MOSFETs. We show that the high series resistance may cause frequency dispersion during the split-CV measurements, which leads to underestimating the inversion charge density and hence overestimating mobility. We demonstrate this effect by comparing UTB-SOI transistors with both recessed-gate UTB-SOI devices and thicker conventional SOI MOSFETs. In addition, the intrinsic high series access resistance in UTB-SOI MOSFETs can potentially lead to an overestimation of the effective internal source/drain voltage, which in turn results in a severe underestimation of the carrier mobility. A specific MOSFET test structure that includes additional 4-point probe channel contacts is demonstrated to circumvent this problem, Finally, we accurately extract mobility in UTB-SOI transistors down to 0.9 nm silicon film thickness (four atomic layers) by utilizing the 4-point probe method and carefully choosing adequate frequencies for the split-CV measurements. It is found that in Such thin silicon film thicknesses quantum mechanical effects shift the threshold voltage and degrade mobility.

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