Change search
Refine search result
1 - 6 of 6
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Castañeda Lozano, Roberto
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Software and Computer systems, SCS. RISE SICS (Swedish Institute of Computer Science).
    Schulte, Christian
    KTH, School of Electrical Engineering and Computer Science (EECS), Software and Computer systems, SCS.
    Survey on Combinatorial Register Allocation and Instruction Scheduling2018In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341Article in journal (Refereed)
    Abstract [en]

    Register allocation (mapping variables to processor registers or memory) and instruction scheduling (reordering instructions to increase instruction-level parallelism) are essential tasks for generating efficient assembly code in a compiler. In the last three decades, combinatorial optimization has emerged as an alternative to traditional, heuristic algorithms for these two tasks. Combinatorial optimization approaches can deliver optimal solutions according to a model, can precisely capture trade-offs between conflicting decisions, and are more flexible at the expense of increased compilation time.

    This paper provides an exhaustive literature review and a classification of combinatorial optimization approaches to register allocation and instruction scheduling, with a focus on the techniques that are most applied in this context: integer programming, constraint programming, partitioned Boolean quadratic programming, and enumeration. Researchers in compilers and combinatorial optimization can benefit from identifying developments, trends, and challenges in the area; compiler practitioners may discern opportunities and grasp the potential benefit of applying combinatorial optimization.

  • 2.
    Eslami Kiasari, Abbas
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mathematical formalisms for performance evaluation of networks-on-chip2013In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 45, no 3, p. 38-Article in journal (Refereed)
    Abstract [en]

    This article reviews four popular mathematical formalisms-queueing theory, network calculus, schedulability analysis, anddataflow analysis-and how they have been applied to the analysis of on-chip communication performance in Systems-on-Chip. The article discusses the basic concepts and results of each formalism and provides examples of how they have been used in Networks-on-Chip (NoCs) performance analysis. Also, the respective strengths and weaknesses of each technique and its suitability for a specific purpose are investigated. An open research issue is a unified analytical model for a comprehensive performance evaluation of NoCs. To this end, this article reviews the attempts that have been made to bridge these formalisms.

  • 3.
    Giraldo, Jairo
    et al.
    Univ Texas Dallas, Erik Jonsson Sch Engn & Comp Sci, 800 W Campbell Rd, Richardson, TX 75080 USA..
    Urbina, David
    Univ Texas Dallas, Erik Jonsson Sch Engn & Comp Sci, 800 W Campbell Rd, Richardson, TX 75080 USA..
    Cardenas, Alvaro
    Univ Texas Dallas, Erik Jonsson Sch Engn & Comp Sci, 800 W Campbell Rd, Richardson, TX 75080 USA..
    Valente, Junia
    Univ Texas Dallas, Erik Jonsson Sch Engn & Comp Sci, 800 W Campbell Rd, Richardson, TX 75080 USA..
    Faisal, Mustafa
    Univ Texas Dallas, Erik Jonsson Sch Engn & Comp Sci, 800 W Campbell Rd, Richardson, TX 75080 USA..
    Ruths, Justin
    Univ Texas Dallas, Erik Jonsson Sch Engn & Comp Sci, 800 W Campbell Rd, Richardson, TX 75080 USA..
    Tippenhauer, Nils Ole
    Singapore Univ Technol & Design, Informat Syst Technol & Design Pillar, 8 Somapah Rd, Singapore 487372, Singapore..
    Sandberg, Henrik
    KTH, School of Electrical Engineering and Computer Science (EECS), Automatic Control.
    Candell, Richard
    NIST, Networked Control Syst Grp, 100 Bur Dr, Gaithersburg, MD 20899 USA..
    A Survey of Physics-Based Attack Detection in Cyber-Physical Systems2018In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 51, no 4, article id 76Article in journal (Refereed)
    Abstract [en]

    Monitoring the "physics" of cyber-physical systems to detect attacks is a growing area of research. In its basic form, a security monitor creates time-series models of sensor readings for an industrial control system and identifies anomalies in these measurements to identify potentially false control commands or false sensor readings. In this article, we review previous work on physics-based anomaly detection based on a unified taxonomy that allows us to identify limitations and unexplored challenges and to propose new solutions.

  • 4. Gomes, Claudio
    et al.
    Thule, Casper
    Broman, David
    KTH, School of Electrical Engineering and Computer Science (EECS), Software and Computer systems, SCS.
    Larsen, Peter Gorm
    Vangheluwe, Hans
    Co-Simulation: A Survey2018In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 51, no 3, article id 49Article in journal (Refereed)
    Abstract [en]

    Modeling and simulation techniques are today extensively used both in industry and science. Parts of larger systems are, however, typically modeled and simulated by different techniques, tools, and algorithms. In addition, experts from different disciplines use various modeling and simulation techniques. Both these facts make it difficult to study coupled heterogeneous systems. Co-simulation is an emerging enabling technique, where global simulation of a coupled system can be achieved by composing the simulations of its parts. Due to its potential and interdisciplinary nature, cosimulation is being studied in different disciplines but with limited sharing of findings. In this survey, we study and survey the state-of-the-art techniques for co-simulation, with the goal of enhancing future research and highlighting the main challenges. To study this broad topic, we start by focusing on discrete-event-based co-simulation, followed by continuous-time-based co-simulation. Finally, we explore the interactions between these two paradigms, in hybrid co-simulation. To survey the current techniques, tools, and research challenges, we systematically classify recently published research literature on co-simulation, and summarize it into a taxonomy. As a result, we identify the need for finding generic approaches for modular, stable, and accurate coupling of simulation units, as well as expressing the adaptations required to ensure that the coupling is correct.

  • 5.
    Malik, Jamshaid Sarwar
    et al.
    KTH.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Elektronics.
    Gaussian Random Number Generation: A Survey on Hardware Architectures2016In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 49, no 3, article id 53Article in journal (Refereed)
    Abstract [en]

    Some excellent surveys of the Gaussian random number generators (GRNGs) from the algorithmic perspective exist in the published literature to date (e.g., Thomas et al. [2007]). In the last decade, however, advancements in digital hardware have resulted in an ever-decreasing hardware cost and increased design flexibility. Additionally, recent advances in applications like gaming, weather forecasting, and simulations in physics and astronomy require faster, cheaper, and statistically accurate GRNGs. These two trends have contributed toward the development of a number of novel GRNG architectures optimized for hardware design. A detailed comparative study of these hardware architectures has been somewhat missing in the published literature. This work provides the potential user a capsulization of the published hardware GRNG architectures. We have provided the method and theory, pros and cons, and a comparative summary of the speed, statistical accuracy, and hardware resource utilization of these architectures. Finally, we have complemented this work by describing two novel hardware GRNG architectures, namely, the CLT-inversion and the multihat algorithm, respectively. These new architectures provide high tail accuracy (6 sigma and 8 sigma, respectively) at a low hardware cost.

  • 6. Radetzki, Martin
    et al.
    Feng, Chaochao
    Zhao, Xueqian
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Methods for Fault Tolerance in Networks-on-Chip2013In: ACM Computing Surveys, ISSN 0360-0300, E-ISSN 1557-7341, Vol. 46, no 1, p. 8-Article in journal (Refereed)
    Abstract [en]

    Networks-on-Chip constitute the interconnection architecture of future, massively parallel multiprocessors that assemble hundreds to thousands of processing cores on a single chip. Their integration is enabled by ongoing miniaturization of chip manufacturing technologies following Moore's Law. It comes with the downside of the circuit elements' increased susceptibility to failure. Research on fault-tolerant Networks-on-Chip tries to mitigate partial failure and its effect on network performance and reliability by exploiting various forms of redundancy at the suitable network layers. The article at hand reviews the failure mechanisms, fault models, diagnosis techniques, and fault-tolerance methods in on-chip networks, and surveys and summarizes the research of the last ten years. It is structured along three communication layers: the data link, the network, and the transport layers. The most important results are summarized and open research problems and challenges are highlighted to guide future research on this topic.

1 - 6 of 6
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf