In Network-on-Chip (NoC) based multi-core platforms, Distributed Shared Memory (DSM) preferably uses virtual addressing in order to hide the physical locations of the memories. However, this incurs performance penalty due to the Virtual-to-Physical (V2P) address translation overhead for all memory accesses. Based on the data property which can be either private or shared, this paper proposes a hybrid DSM which partitions a local memory into a private and a shared part. The private part is accessed directly using physical addressing and the shared part using virtual addressing. In particular, the partitioning boundary can be configured statically at design time and dynamically at runtime. The dynamic configuration further removes the V2P address translation overhead for those data with changeable property when they become private at runtime. In the experiments with three applications (matrix multiplication, 2D FFT, and H.264/AVC encoding), compared with the conventional DSM, our techniques show performance improvement up to 37.89%.
We present a single-cycle output buffered router based on layered switching for networks on chips (NoCs). Different from state-of-the-art NoC routers, the router has three important characteristics: (1) It employs layered switching, which implements wormhole on top of virtual cut-through (VCT) switching; (2) In contrast to input buffered architectures, it adopts an output buffered architecture; (3) It is single cycle, meaning that the router pipeline takes only one cycle for all flits. Experimental results show that the router achieves up to 80% of ideal network throughput under uniform random traffic pattern. Compared with wormhole switching, layered switching achieves up to 36.9% latency reduction for 12-flit packets under uniform random traffic with an injection rate of 0.5 flit/cycle/node. Under 65 nm technology synthesized results show that its critical path has only 20 logic gates, and it reduces 11% area compared to the input virtual-channel router with the same buffer capacity.
Due to high latency and high power consumption in long hops between operational cores of Network-on-Chips (NoCs), the performance of such architectures has been limited. Billions of transistors available on a single chip present opportunities for new levels of computing capability. In order to fill the gap between computing requirements and efficient communications, a new technology called Wireless NoC has been emerged. Employing wireless communication links between cores, wireless NoC has reasonably increased the performance of NoC. However, wireless transceivers along with associated antenna impose considerable area and power overheads in wireless NoCs. Thus, in this paper, we introduce a hybrid wireless NoC called Hierarchical Wireless-based Architecture (HiWA) to use the wireless resources optimally. In the proposed approach the network is divided into subnets where intra-subnet nodes communicate through wire links while inter-subnet communications are handled almost by single-hop wireless links. Simulation results show that HiWA efficiently reduces power consumption by 39% in comparison with a traditional wireless NoC, called WiNoC, while still achieves 16% lower packet latency than conventional NoC.
A distributed control system, controlling the motion of a mechanical system, consists of several intelligent modules, one for each degree of freedom. Each module contains one actuator, one or more sensors and a microelectronics subsystem. The modules together execute the control engineering solution of the actual control theory problem. Typical motion control applications which could benefit from distributed control include industrial robots, vehicles, and tunnel drilling machines. By way of introduction the characteristics of motion control applications are described. Reasons for and trends towards distributing intelligence to actuators and sensors are presented. Due to harsh environments the microelectronic subsystems must be compact and robust. Technical trends facilitating integration of mechanics and microelectronics are described. The following issues are identified as critical when designing distributed control systems:Specification and verification methods for real-time systems; the view of time; consistency constraints; communication system architectures; predictable behaviour and debugging. A state of the art survey is given. Finally the question of how to map the control engineering solution of the actual control theory problem to the intelligent actuators is treated, i.e. choice of suitable allocation strategies, scheduling algorithms and communication system architectures. Fundamental static allocation strategies include master slave application systems (ranging from distributed low level I/O handling to distributed servo functions) and fully distributed application systems (ranging from distributed servo and superior control functions to a fully replicated global servo function).