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  • 1.
    Daneshtalab, Masoud
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.
    Bagherzadeh, Nader
    Sarbazi-Azad, Hamid
    On-chip parallel and network-based systems Preface2015In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, p. 137-138Article in journal (Refereed)
  • 2.
    Jiang, Shuyan
    et al.
    University of Electronic Science and Technology of China, Chengdu, China.
    Wu, Qiong
    University of Electronic Science and Technology of China, Chengdu, China.
    Chen, Shuyu
    University of Electronic Science and Technology of China, Chengdu, China.
    Zhan, Junkai
    University of Electronic Science and Technology of China, Chengdu, China.
    Wang, Junshi
    University of Electronic Science and Technology of China, Chengdu, China.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Huang, Letian
    University of Electronic Science and Technology of China, Chengdu, China.
    Testing aware dynamic mapping for path-centric network-on-chip test2019In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 67, p. 134-143Article in journal (Refereed)
    Abstract [en]

    With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the primary goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle paths are identified, and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from the time when the application leaves the platform to the time when a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping, which leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF(Fiexitrst Free), NN(Nearest Neighbor), CoNA(Contiguous Neighborhood Allocation), and WeNA(Weighted-based Neighborhood Allocation).

  • 3.
    Ma, Ning
    et al.
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
    Design and Implementation of Multi-mode Routers for Large-scale Inter-core Networks2016In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 53, p. 1-13Article in journal (Other academic)
    Abstract [en]

    Constructing on-chip or inter-silicon (inter-die/inter-chip) networks to connect multiple processors extends the system capability and scalability. It is a key issue to implement a flexible router that can fit into various application scenarios. This paper proposes a multi-mode adaptable router that can support both circuit and wormhole switching with supplying flexible working strategies for specific traffic patterns in diverse applications. The limitation of mono-mode switched routers is shown at first, followed by algorithm exploration in the proposed router for choosing the proper working strategy in a specific network. We then present the performance improvement when applying the mixed circuit/wormhole switching mode to different applications, and analyze the image decoding as a case study. The multi-mode router has been implemented with different configurations in a 65 nm CMOS technology. The one with 8-bit flit width is demonstrated together with a multi-core processor to show the feasibility. Working at 350 MHz, the average power consumption of the whole system is 22 mW.

  • 4.
    Pamunuwa, Dinesh
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Millberg, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A study on the implementation of 2-D mesh-based networks-on-chip in the nanometre regime2004In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 38, no 1, p. 3-17Article in journal (Refereed)
    Abstract [en]

    On-chip packet-switched networks have been proposed for future giga-scale integration in the nanometre regime. This paper examines likely architectures for such networks and considers trade-offs in the layout, performance, and power consumption based on full-swing, voltage-mode CMOS signalling. A study is carried out for a future technology with parameters as predicted by the International Technology Roadmap for Semiconductors to yield a quantitative comparison of the performance and power trade-off for the network. Important physical level issues are discussed.

  • 5. Wang, Xiaohang
    et al.
    Zhao, Baoxin
    Mak, Terrence
    Yang, Mei
    Jiang, Yingtao
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.
    An efficient runtime power allocation scheme for many-core systems inspired from auction theory2015In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 50, p. 147-157Article in journal (Refereed)
    Abstract [en]

    Design of future many-core chips is experiencing a paradigm shift to the so-called power-budgeting design, due to the widening gap between instantaneous power consumption and the allowed maximum power, referred as the power budget. Critical to these many-core chips is the runtime power allocation mechanism which can help optimizing the overall system performance under a limited power budget constraint. In this paper, the power allocation problem (i.e., maximizing the system performance under a power budget) is modeled by a combinatorial auction. The problem can be transformed to a knapsack problem and the optimal solution reaches a Walrasian equilibrium. To solve the problem efficiently in a decentralized way, a Hierarchal MultiAgent based Power allocation (HiMAP) method is proposed with an optimal bound. In HiMAP, tiles bid for the opportunity to become active based on the chip's total power budget. Upon finishing an auction process, certain tiles will be power gated and/or frequency scaled according to the power allocation decision. Experimental results have confirmed that HiMAP can reduce the execution time by as much as 45% compared to four competing methods. The runtime overhead and cost of HiMAP are also small, which makes it scale well with many-core systems.

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