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  • 1.
    Almström, Erland
    KTH, Superseded Departments, Electronic Systems Design.
    Reconfigurable and transparent wavelength division multiplexed optical transport networks1999Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    This thesis is about reconfigurable and transparentwavelength division multiplexed (WDM) networks.Reconfigurability is used to achieve higher surveillance andthroughput in the network. This is done by wavelength selectiveand independent network elements. These network elements canaccomplish bypass and protection switching ofthe traffic.Transparency in the optical layer enables the transport networkto accept new bit rates, codes and formats of the clients. Theenabling technologies to achieve a reconfigurable andtransparent network are integrated tuneable devices andswitches. In this thesis some of these devices have beenexperimentally evaluated according to theirs cascadability andcrosstalk performance.

    A unidirectional self-healing wavelength divisionmultiplexed ring was designed, assembled and evaluated. Byutilising WDM, logical networks could be constructed withoptical add drop multiplexers (OADM) to support communicativeand distributive services. The main transmission limitation ofthe ring was homogenous broadening of the opticalamplifiers.

    The second network element investigated, was the opticalcrossconnect (OXC). The OXC was comprised of optical InP andLiNbO3 switches and tuneable filters, which were experimentallyevaluated. Two OXCs and an OADM were installed in the Stockholmgigabit network (SGN) with fault and configurationmanagement.

    The cascadability of OXCs with reshaping repeaters andoptical or electrical switches was investigated. The jitter ofthe OXC with electrical switches limited its performance, whilethe OXC with optical switch was limited by its crosstalk.Crosstalk especially intra-band crosstalk, which beats with thesignal, is a severe limitation of optical networks. Experimentsand simulations were performed on the time dependence of theintra-band crosstalk. It was shown and experimentally confirmedthat the quasi-correlated intra-band crosstalk could be theworst case.

    In the next phase of the network five OADMs and one OXC,which interconnected a unidirectional and a bidirectionalprotected ring, were integrated into SGN with a web basedmanagement system.

    The OADMs were evaluated in a recirculating loop toinvestigate the cascadability of the nodes. The nodes could bedivided into optical channel or fibre protection and notch ordemultiplex filtering. An optimum of loss of the cascadedoptical amplifiers were found, which maximised the gainflatness and the signal to noise ratio. The OXC utilising fixedWDMs and polymer switches was designed and evaluated takinginto account the configuration, fault handling and performancemonitoring of the optical layer. Data services were evaluatedas clients to the optical layer, especially to provide opticalprotection without interfering with its client.

    Keywords:Optical Network, Wavelength DivisionMultiplexing, Reconfigurable Network, Optical Cross Connect,Optical Add Drop Multiplexer, Transparency, Crosstalk,Cascading, Protection, Optical Switch, Electrical Switch,Tuneable Filter, Self-Healing Ring, Logical Network, StockholmGigabit Network, Internetworking

  • 2. Ben Dhaou, I.
    et al.
    Ismail, Mohammed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Current mode, low-power, on-chip signaling in deep-submicron CMOS technology2003In: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, no 3, 397-406 p.Article in journal (Refereed)
    Abstract [en]

    qThis paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10% Experimental results on a set of benchmark signaling problems implemented in a 0.25-mum 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a twofold reduction in the power and a reduction of 1.4 times the area.

  • 3. Ben Dhaou, I.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Efficient library characterization for high-level power estimation2004In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 12, no 6, 657-661 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes LP-DSM, which is an algorithm used for efficient library characterization in high-level power estimation. LP-DSM characterizes the power consumption of building blocks using the entropy of primary inputs and primary outputs. The experimental results showed that over a wide range of benchmark circuits implemented using full custom design in 0.35-mum 3.3 V CMOS process the statistical performance (mean and maximum error) of LP-DSM is comparable or sometimes better than most of the published algorithms. Moreover, it was found that LP-DSM has the lowest prediction sum of squares, which makes it an efficient tool for power prediction. Furthermore, the complexity of the LP-DSM is linear in relation to the number of primary inputs (O(NI)), whereas state of the art published library characterization algorithms have a complexity of O(NI2).

  • 4.
    Ben Dhaou, Imed
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Comparison of OFDM and WPM for fourth generation broadband WLAN2000In: European Signal Processing Conference, 2000, no MarchConference paper (Refereed)
    Abstract [en]

    In this paper, we propose a qualitative comparison between OFDM (Orthogonal Frequency Division Multiplexing), and WPM (Wavelet Packet Modulation). The comparison is done for two separate cases. Firstly, the efficiency of the two signaling systems will be compared. Secondly, the requirements for hardware implementation will be performed. From the performance and the VLSI implementation viewpoint, we found that WPM outperforms OFDM. However, the out-of-band radiation and peak-to-average-power for the case of OFDM is better compared to the WPM. The extensive simulation results, show that the average increase of peak-to-average-power is approximately 0.98dB compared to the OFDM. The increase of the adjacent channel power ratio channel is approximately 12.41dBc compared to the OFDM.

  • 5.
    Bremberg, Dan
    KTH, Superseded Departments, Electronic Systems Design.
    Experimental investigation of energy transfer upconversion in densely Er+ doped silica fibres1999Licentiate thesis, comprehensive summary (Other scientific)
  • 6.
    Bueno, Fermin
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    Kumar, Anshul
    Torkelsson, Mats
    Ericsson AB.
    High-Level Synthesis of a 1 Mbps Direct-Sequence Spread-Spectrum RAKE Receiver1996In: Workshop on Synthesis And System Integration, 1996, 170-177 p.Conference paper (Refereed)
  • 7.
    Cardenas, Juan
    KTH, Superseded Departments, Electronic Systems Design.
    The applications of secondary ion mass spectrometry for the investigation of dopant and matrix elements in CoSi<sub>2</sub>/Si structures1998Doctoral thesis, comprehensive summary (Other scientific)
  • 8.
    Cijvat, Ellie
    KTH, Superseded Departments, Electronic Systems Design.
    A study of CMOS receiver architechtures in mobile communication handsets GSM2000Licentiate thesis, monograph (Other scientific)
  • 9.
    Dhaou, I. Ben
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Dubrova, Elena
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Power Efficient Inter-Mode Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology2001In:  , 2001, 61-66 p.Conference paper (Refereed)
  • 10. Dielacher, Franz
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Special issue on the 2002 European Solid State Circuits Conference (Esscirc): Guest editorial2003In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, no 7, 1095-1097 p.Article in journal (Refereed)
  • 11.
    Doyle, James P.
    KTH, Superseded Departments, Electronic Systems Design.
    Copper germanide schottky contacts to silicon and electrically active defects in n-type 6H-SiC and 4H-SiC epitaxial layers1997Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Metallization for contacts to silicon devices presents amajor challenge as the linewidths are further reduced into thesub-micron regime. Copper germanide due to its relatively lowroom temperature resistivity ( ~ 10 µΩ - cm) has beenexamined as a potential contact metallixation. In addition, dueto the growing interest in silicon carbide as a potentialwide-bandgap semiconductor candidate for high voltage, power,and frequency devices, a characterization of electricallyactive deep levels was conducted on as-grown and electron andion irradiated layers as such defects can influence theelectrical behaviour of active devices. N-type 6H- and 4H-SiChave been characterized by deep level transient spectroscopy(DLTS) in conjunction with MeV electron beam irradiation andkeV hydrogen and deuterium implantation. Intrinsic levels havebeen identified in both polytypes through an examination ofas-grown and irradiated samples.

    It is demonstrated that silicon outdiffusion into the coppergermanide contact causes an increase in the electricalresistivity. Additionally, deviation from ideal behaviour isobserved in current-voltage (IV) measurements an indicationthat this outdiffusion of silicon produces recombinationcenters primarily in the upper part of the bandgap near to thecontact-semiconductor interface. Additionally, copper germanideis found to be morphologically unstable during theamorphous-to-crystalline transformation. The high diffusivityof copper in amorphous germanium at temperatures as low as 200°C coupled with the independence of the barrier height onthe germanium fraction used during contact formation indicatesthat the interface between copper germanide and silicon issimilar to that of copper silicide and silicon.

    A number of electrically active deep levels have beencharacterized in both the 4H- and 6H-SiC polytypes. In 6H-SIC,many of the defects are found to be intrinsic as they areobserved to grow as a function of increasing irradiation dose.In contrast, as-grown 4H-SiC epitaxial layers, exhibit only asingle acceptor-like level at 0.70 eV below the conduction bandedge (Ec). After irradiation the level is not observed toincrease in concentration, but two new levels are found. Theselevels are found to be unstable at room temperature in contrastto the 6H-SiC defects. In 6H-SiC, the defect concentration isfound to limit the average carrier lifetime. Through the use ofthermal annealing, SIMS, and electron irradiation, a model oftheir Origin is proposed.

    Keywords:Deep level transient spectroscopy (DLTS),secondary ion mass spectrometry (SIMS), amorphous germanium,electron irradiation, ion irradiation, wide-bandgap

  • 12.
    Dubrova, Elena
    KTH, Superseded Departments, Electronic Systems Design.
    A polynomial time algorithm for non-disjoint decomposition of multiple-valued functions2004In: 34th International Symposium On Multiple-Valued Logic, Proceedings, 2004, 309-314 p.Conference paper (Refereed)
    Abstract [en]

    This paper addresses the problem of non-disjoint decomposition of multiple-valued functions. First, we show that the problem of computing non-disjoint decompositions of a multiple-valued function is related to the problem of finding multiple-vertex dominators of a logic circuit, representing the function. Second, we present an O(n(k)) algorithm for computing all multiple-vertex dominators of a fixed size k, where n is the number of gates of the logic circuit. Our result is important because no polynomial-time algorithm for finding all possible non-disjoint decompositions of multiple-valued functions is known. The presented approach allows us computing a certain subset of non-disjoint decompositions (all reflected in a given circuit structure) in polynomial time. A set of experiments on benchmark circuits illustrates the efficiency of our approach.

  • 13.
    Dubrova, Elena
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, P.
    Miller, D. M.
    Muzio, J. C.
    Sullivan, A. J.
    TOP: an algorithm for three-level combinational logic optimisation2004In: IEE Proceedings - Circuits Devices and Systems, ISSN 1350-2409, E-ISSN 1359-7000, Vol. 151, no 4, 307-314 p.Article in journal (Refereed)
    Abstract [en]

    Three-level logic is shown to have a potential for reducing the area over two-level implementations, as well as for a gain in speed over multilevel implementations. A heuristic algorithm TOP is presented, targeting a three-level logic expression of type g(1degrees)g(2), where g(1) and g(2) are sum-of-products expressions and '(degrees)' is a binary operation. For the first time, to the authors' knowledge, this problem is addressed for an arbitrary operation '(degrees)', although several algorithms for specified cases of '(degrees)' have been presented in the past. The experimental results show that, on average, the total number of product-terms in the expression obtained by TOP is about one third of the number of product-terms in the expression obtained by a two-level AND-OR minimiser.

  • 14.
    Dubrova, Elena
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Sack, H.
    Probabilistic equivalence checking of multiple-valued functions2004In: Journal of Multiple-Valued Logic and Soft Computing, ISSN 1542-3980, E-ISSN 1542-3999, Vol. 10, no 4, 395-414 p.Article in journal (Refereed)
    Abstract [en]

    This paper describes a probabilistic method for verifying the equivalence of two multiple-valued functions. Each function is hashed to an integer code by transforming it to a integer-valued polynomial and evaluating it for values of variables taken independently and uniformly at random from a finite field. Since the polynomial is unique for a given function, if two hash codes are different, then the functions are not equivalent. However, if two hash codes are the same, the functions may or may not be equivalent, because different polynomials may happen to hash to the same code. Thus, the method presented in this paper determines the equivalence of two functions with a known (small) probability of error, arising from collisions between inequivalent functions. Such a method seems to be an attractive alternative for verifying functions that are too large to be handled by deterministic equivalence checking methods.

  • 15.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Torikka, Tommi
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Ismail, Mohammed
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    On-chip versus off-chip passives in multi-band radio design2004In: ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE / [ed] Steyaert, M; Claeys, CL, NEW YORK: IEEE , 2004, 327-330 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents on-chip versus off-chip passives in multi-band radio design. The analysis is demonstrated through several multi-band low noise amplifiers designs in SiGe BiCMOS and GaAs PHEMT. Cost-performance trade-off analysis shows that when on-chip passives are moved off chip, performance of RF circuits is always improved. However, simple RF circuits do not show obvious cost-benefits, whereas complex RF circuits such as multi-band radio can have significant cost savings by using off-chip passives.

  • 16.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Torikka, Tommi
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Ismail, Muhammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Tjukanoff, Esa
    A DC-13GHz LNA for UWB RFID applications2004In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, 2004, 241-244 p.Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a 4-stage traveling wave lownoise amplifier for UWB RFID (ultra-wideband radiofrequency identification). This LNA covers a frequencyrange of DC - 13 CHz. The circuit is implemented with0.I5pm GaAs PHEMT chips embedded in flexible LCP(liquid crystal polymer) substrate. In the frequency range,the gain of the LNA is better than IO dB, fluctuation of thegain is less than 3dB, its noise figure is less than 4dB, SI 1and S22 are around -10 dB.

  • 17.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Ismail, Mohammed
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    On-chip versus off-chip passives analysis in radio and mixed-signal system-on-package design2004In: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), NEW YORK: IEEE , 2004, 109-116 p.Conference paper (Refereed)
    Abstract [en]

    Advances of VLSI and packaging technologies enable condensed integration of system level functions in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP, and eliminate constraints between chip and package, a complete solution is needed to co-design and co-optimize chip and package in a total design plan with precise trade-offs of on-chip versus off-chip passives. In this paper, we present a complete and systematic design methodology for RF SoP/SoC. This methodology includes early analysis and design implementation. This early analysis is to estimate the performance and cost of each solution quickly and quantitively. Then, the best solution is found and implemented. For a better presentation, the method and design techniques are demonstrated through the design of a common emitter low noise amplifier (LNA) for 5GHz wireless LAN (local area network). Analytical equations of noise figure and transducer gain for the LNA with lossy package are also developed.

  • 18.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Ismail, Muhammad
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    On-chip versus Off-chip Passives Trade-offs in Radio and Mixed-Signal System-on- PackageManuscript (preprint) (Other academic)
  • 19.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Ismail, Muhammed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Analysis of lossy packaging parasitics for common emitter LNA in system-on-package2004In: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, NEW YORK: IEEE , 2004, 75-78 p.Conference paper (Refereed)
    Abstract [en]

    Advances of VLSI and packaging technologies enable condensed integration of an RF system in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP for RF systems and their sub-systems, it is needed to predict and estimate performance of each solution. In this paper, analytical equations for noise figure and gain of inductively degenerated common-emitter low-noise amplifiers in SoP/SoC are deduced as functions of passives and packaging parasitics. They hence enable designers to evaluate overall performance of each solution quantitatively. As well, influence of lossy packaging parasitics on LNA is also analyzed.

  • 20.
    Duo, Xinzhong
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    RF robustness enhancement through statistical analysis of chip-package co-design2004In: 2004 IEEE International Symposium on Cirquits and Systems - Proceedings, IEEE , 2004, 988-991 p.Conference paper (Refereed)
    Abstract [en]

    In order to enhance robustness of RF circuits, a flow of statistical analysis for chip-package co-design of RF system-on-package (SoP) is presented in this work. Methods for improving the yield of RF modules are developed. On-chip passive components versus off-chip passive components trade-offs in SoP module were also analyzed in terms of performance and yield. The design methods were demonstrated through case studies of LNA (low noise amplifier) in SoP.

  • 21.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    High-level synthesis of control and memory intensive applications2000Doctoral thesis, monograph (Other scientific)
  • 22.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Anshul
    KTH, Superseded Departments, Electronic Systems Design.
    Svantesson, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Controller Synthesis in Control and Memory Centric High-level Synthesis System1996In: Proceedings of the Baltic Electronics Conference, 1996, 393-396 p.Conference paper (Refereed)
  • 23.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    Kumar, Anshul
    Svantesson, Bengt
    Öberg, Johnny
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Controller Synthesis in Control and Memory Centric High-Level Synthesis System1996In: 5th Biennial Baltic Electronic Conference, 1996, 393-396 p.Conference paper (Refereed)
  • 24.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Exploring ASIC Design Space at System Level with a Neural Network Estimator1994In: Proc. of IEEE ASIC-conference, 1994, 1994Conference paper (Refereed)
    Abstract [en]

    Estimators are critical tools in doing architectural level exploration of the design space. We present a novel approach to estimation based on the multilayer perceptron which builds the estimation function during the learning process and thus allows to describe arbitrary complex functions. We also describe how the control data flow graph is encoded for the neural network input and we present results of the first experiments made with realistic design examples.

  • 25.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Anshul
    KTH, Superseded Departments, Electronic Systems Design.
    Svantesson, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Internal Representation and behavioralsynthesis of control dominated applications1996In: Proceedings of the 14th Norchip Conference, 1996Conference paper (Refereed)
  • 26.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Anshul
    KTH, Superseded Departments, Electronic Systems Design.
    Svantesson, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Segment-Based Scheduling of Control Dominated Applications in High Level Synthesis1996In:  , 1996, 337-344 p.Conference paper (Refereed)
  • 27.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Shashi
    Indian Institute of Technology.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Comparison of four heuristic algorithms forunified allocation and binding in high-level synthesis1997In: Proc. of IEEE NORCHIP 1997, 1997Conference paper (Refereed)
  • 28.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Shashi
    Jantsch, Axel
    Hemani, Ahmed
    Svantesson, Bengt
    Öberg, Johnny
    Sander, Ingo
    KTH, Superseded Departments, Electronic Systems Design.
    IRSYD - An Internal Rep­resentation for System Description (Version 0.1)1997Report (Other academic)
  • 29.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    SpaceBall-1G: Instruction Set and Cache Modelling1995Report (Other academic)
  • 30.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    SpaceBall-1G: Thermal Investigation and Packaging problems1995Report (Other academic)
  • 31.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Area Estimation in the High Level Synthesis Using Neural Networks1994Conference paper (Refereed)
  • 32.
    Ellervee, Peeter
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    Tenhunen, Hannu
    Partitioning of a 1 GIPS Revolver Processor Architecture into a Tiled GaAs VLSI Implementation1995Conference paper (Refereed)
  • 33.
    Eriksson, Urban
    KTH, Superseded Departments, Electronic Systems Design.
    Technologies for monolithic indium phosphide optoelectronic integrated circuits1999Doctoral thesis, comprehensive summary (Other scientific)
  • 34.
    Fröjdh, Christer
    KTH, Superseded Departments, Electronic Systems Design.
    Schottky barriers and Schottky barrier based devices on Si and SiC1998Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    This work is devoted to a study of the formation andcharacterisation of Schottky Barriers on differentsemiconductors with an extension to the development of devicesbased on Schottky barriers. The major part of the work has beendone on 6H-SiC, but Si and SiGe alloys have also been used.

    Different metals have been deposited on p-type and n-type6H-SiC and the properties of the created barriers have beeninvestigated by CV, IV and photoelectric techniques. Data fromother research groups have been collected in order toinvestigate the correlation between the barrier height and themetal work function. The conclusion is that for a number ofmetals there is a strong correlation between the barrier heightand the metal work function, while other metals showsignificant deviation from the Schottky-Mott theory. Largescatter in the data exists between different investigationsindicating that the method of sample preparation is veryimportant for the results. This is not surprising since theSchottky Barrier is mainly a surface device, which makes itvery sensitive to variations in the surface conditions.

    Extensive work has been done in order to explain thebehaviour of Schottky diodes fabricated on SiC and to qualifythe measurement techniques in presence of different anomaliesin the devices. A highly resistive interfacial layer presentbetween the bulk wafer and the epitaxial top layer on certainp-type 6H-SiC wafers has been found.

    A process for fabrication of buried Schottky and ohmiccontacts in Silicon by wafer bonding has been developed usingCo as a buried metal layer. During the heat treatment the metalreacts with the Silicon and forms CoSi2. The processed contacts exhibit the sameproperties as similar contacts produced by other techniques.Schottky contacts formed by deposition of W and Ti on differentSiGe alloys have been characterised. The pinning of the Fermilevel in these alloys is stronger than in pure Si.

    The device work included fabrication of Schottky diodes foruse as photodetectors and Permeable Base Transistors (PBT).Grid shaped Ti based Schottky diodes were fabricated in 6H-SiC.Optical characterisation shows that the diodes are sensitive inthe UV-range with a peak sensitivity around 300 nm. The diodesare insensitive to visible light. Diodes on p-type materialshow higher sensitivity than diodes on n-type material. This isexpected due to the higher barriers on p-type and the highermobility of electrons, increasing the contribution fromdiffusion.

    A process for the fabrication of PBT:s on Silicon using selfaligned CoSi2contacts was developed. Devices were fabricatedand DC-characterised. The first PBT on 6H-SiC was fabricatedusing a process based on etching of epitaxial layers. Ni wasused as etch mask and ohmic contact. Ti was used as gatemetal.

  • 35.
    Gao, Yonghong
    KTH, Superseded Departments, Electronic Systems Design.
    Architecture and Implementation of Comb Filters and Digital Modulators for Oversampling A/D and D/A Converters2001Doctoral thesis, monograph (Other scientific)
  • 36. Gothenberg, A.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Performance analysis of sampling switches in voltage and frequency domains using Volterra series2004In: 2004 IEEE International Symposium on Circuits and Systems, Vol 1, Proceedings, IEEE , 2004, Vol. 1, 765-768 p.Conference paper (Refereed)
    Abstract [en]

    In any data converter system, the linearity of the sampling switch is a very critical parameter, especially for wideband sigma-delta modulators. Distortion introduced in the sampling instance directly degrades the quality of the input signal. In this paper we present analyses of a set of sampling switches in the frequency and voltage domains in order to find the most linear type for wide baseband excitation. Volterra series analysis is adopted to find the frequency behavior of the switches. The theoretical results are verified by circuit simulations in a 0.35mum CMOS process. It is found that the bootstrap sampling switch is a very attractive candidate, especially for frequencies near f(s)/2.

  • 37. Hellberg, L.
    et al.
    Hemani, A.
    Isoaho, J.
    Jantsch, A.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mokhtari, M.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    System Oriented VLSI Curriculum at KTH1997In:  , 1997Conference paper (Refereed)
  • 38. Hellberg, L.
    et al.
    Hemani, A.
    KTH, Superseded Departments, Electronic Systems Design.
    Isoaho, J.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Mokhtari, M.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Integration of Physical and Functional Electronic System Representations in Electronic Curriculum1997In:  , 1997Conference paper (Refereed)
  • 39.
    Hellberg, Lars
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Isoaho, Jouni
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Mokhtari, Mehran
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    System oriented VLSI curriculum at KTH1997In:  , 1997, 57-59 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the restructuring of VLSI education at the Royal Institute of Technology (KTH). Changing needs of industry, advances in technology and design methodology has required a significant reorganization of VLSI education with combined emphasis on system issues and associated physical constraints. We present here a course structure which will address, in parallel fashion, the key design issues for future system products

  • 40.
    Hellberg, Per-Erik
    KTH, Superseded Departments, Electronic Systems Design.
    Polycrystalline Si<sub>x</sub>Ge<sub>1-x</sub>as the gate electrode in CMOS technology2000Doctoral thesis, comprehensive summary (Other scientific)
  • 41. Hemani, A.
    et al.
    Svantesson, B.
    Ellervee, P.
    Postula, A.
    Öberg, J.
    Jantsch, A.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    High-level Synthesis of Control and Memory Intensive Communication Systems1995In:  , 1995Conference paper (Refereed)
  • 42.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Self-organisation and its application to binding1993In: The Sixth International Conference on VLSI Design, 1993. Proceedings, IEEE , 1993, 186-191 p.Conference paper (Refereed)
    Abstract [en]

    This paper presents Kohonen’s self-organisationalgorithm as an optimisation tool. Its application isillustrated by applying it to a high-level synthesis(HLS)problem - binding: the task of assigning operations to specijicinstances of functional units. It is a crucial problem,as it injluences the interconnect, wiring and register cost.This Self-Organising Binder (SOB) has a built-in hillclimbingmechanism, and being based on neural-networkit can be easily parallelised. We apply SOB to benchmarkexamples and show that the results are comparable to thebest reported in the field.

  • 43.
    Hemani, Ahmed
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Karlsson, Borje
    Bofors AB Missiles.
    Fredriksson, Mats
    Synthesia AB.
    Nordqvist, Kurt
    Synthesia AB.
    Fjellborg, Bjom
    Synthesia AB.
    Application of high-level synthesis in an industrial project1994In: VLSI Design, 1994., Proceedings of the Seventh International Conference on, 1994, 5-10 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the use of high-level synthesis in conjunction with logic synthesis for designing an industrial product specified at system-level in behavioral VHDL and realized in FPGAs. The designers’ experiences from using the high-level synthesis tool and its interaction with the other tools are analyzed. Important problems were the handling of precise timing constraints and feedback of adequate technology information to the high-level synthesis

  • 44.
    Hemani, Ahmed
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Mokhtari, Mehran
    KTH, Superseded Departments, Electronic Systems Design.
    Isoaho, Jouni
    Tampere University of Technology, Signal Processing Laboratory.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A structure of modern VLSI curriculum1994In:  , 1994, 204-208 p.Conference paper (Refereed)
    Abstract [en]

    This paper describes the restructuring of VLSI education at Royal Institute of Technology, Sweden. Changing needs of industry, advances in technology and design methodology has required a significant reorganisation of VLSI education with emphasis on system issues. This restructuring is not viewed as a one step process, rather as a continuous process including close interaction between education and research

  • 45.
    Hemani, Ahmed
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Svantesson, Bengt
    Ellervee, Peeter
    Postula, Adam
    Öberg, J.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Trade-offs in High-level Synthesis of Telecommunication Circuits1995In:  , 1995Conference paper (Refereed)
  • 46.
    Hemani, Ahmed
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Svantesson, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Postula, Adam
    Dept. of Electrical and Computer Engineering, University of Queensland.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    High-level synthesis of control and memory intensive communication systems1995In:  , 1995, 185-191 p.Conference paper (Refereed)
    Abstract [en]

    Communication sub-systems that deal with switching, routing and protocol implementation often have their functionality dominated by control logic and interaction with memory. Synthesis of such Control and Memory Intensive Systems (hereafter abbreviated to CMISTs) poses demands that in the past have not been met satisfactorily by general purpose high-level synthesis (HLS) tools and have led to several research efforts to address these demands. In this paper we: characterise CMISTs from the synthesis viewpoint; present a synthesis methodology adapted for CMISTs; present the Operation and Maintenance (OAM) Protocol of the ATM, its modelling in VHDL and synthesis aspects of the VHDL model; present the results of applying the synthesis methodology to the OAM as a test case-the results are compared to that obtained using the not adapted general purpose High-level synthesis tool; prove the efficacy of the proposed synthesis methodology by applying it to an industrial design and comparing our results to the results from two commercial HLS tools and to the results obtained by designing manually at register-transfer level

  • 47.
    Hemani, Ahmed
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Svantesson, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Postula, Adam
    Dept. of Electrical and Computer Engineering, University of Queensland.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Trade-offs in High-level Synthesis of Telecommunication Circuits1995Conference paper (Refereed)
  • 48.
    Holmström, Nils
    KTH, Superseded Departments, Electronic Systems Design.
    Optimal pacing with an implantable pO<SUB>2</SUB>sensor1999Doctoral thesis, comprehensive summary (Other scientific)
  • 49.
    Höijer, Magnus
    KTH, Superseded Departments, Electronic Systems Design.
    Spontaneous emission control1998Doctoral thesis, monograph (Other scientific)
  • 50.
    Isoaho, Jouni
    et al.
    Tampere University of Technology, Signal Processing Laboratory.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    High level synthesis in DSP ASIC optimization1994In:  Proc. of 7th IEEE ASIC Conference and Exhibit, 1994, 75-78 p.Conference paper (Refereed)
    Abstract [en]

    In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples

1234 1 - 50 of 196
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