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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density2016In: ECS Transactions, Electrochemical Society, 2016, no 8, p. 615-621Conference paper (Refereed)
    Abstract [en]

    Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

  • 2. Aldinucci, Marco
    et al.
    Brorsson, Mats
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    D'Agostino, Daniele
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Kilpatrick, Peter
    Leppanen, Ville
    Preface2017In: The international journal of high performance computing applications, ISSN 1094-3420, E-ISSN 1741-2846, Vol. 31, no 3, p. 179-180Article in journal (Refereed)
  • 3. Ali, Amjad
    et al.
    Jafri, Syeda I.
    Habib, Ayesha
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Engineering and Technology (UET), Pakistan.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    RFID Humidity Sensor Tag for Low-cost Applications2017In: APPLIED COMPUTATIONAL ELECTROMAGNETICS SOCIETY JOURNAL, ISSN 1054-4887, Vol. 32, no 12, p. 1083-1088Article in journal (Refereed)
    Abstract [en]

    This article presents a low-cost, flexible, chipless Radio Frequency Identification (RFID) tag for humidity monitoring applications. The tag exhibits moisture sensing feature within a compact geometrical dimension of 20mm x 17.6mm. The design is loaded with 12 resonators, where each resonator represents 1 bit in the frequency domain. For the designed 12-bit tag, 11 inverted C-shaped resonators are dedicated for encoding 11-bit information in their spectral signature. An integrated meandered-shaped resonator, covered with moisture sensitive Kapton (R) HN film, functions as a 1-bit moisture sensor. It is deployed for monitoring relative humidity (RH) levels, simultaneously. The passive RFID tag is realized on Taconic TLX-0 and has an operational bandwidth of 2.62 GHz. Furthermore, the design is modeled and analyzed for multiple substrates. The performance of the sensor tag for various humidity levels indicates that it is a potential solution for inexpensive sensing applications.

  • 4.
    Ali, Mai
    et al.
    Alfaisal Univ, Dept Elect Engn, Riyadh, Saudi Arabia..
    Gia, Tuan Nguyen
    Taha, Abd-Elhamid
    Alfaisal Univ, Dept Elect Engn, Riyadh, Saudi Arabia..
    Rahmani, Amir M.
    Univ Calif Irvine, Dept Comp Sci, Irvine, CA USA.;Vienna Univ Technol, Vienna, Austria..
    Westerlund, Tomi
    Univ Turku, Dept Future Technol, Turku, Finland..
    Liljeberg, Pasi
    Univ Turku, Dept Future Technol, Turku, Finland..
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Autonomous Patient/Home Health Monitoring powered by Energy Harvesting2017In: Globecom 2017 - 2017 IEEE Global Communications Conference, Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper (Refereed)
    Abstract [en]

    This paper presents the design of an autonomous smart patient/home health monitoring system. Both patient physiological parameters as well as room conditions are being monitored continuously to insure patient safety. The sensors are connected on an IoT regime, where the collected data is wirelessly transferred to a nearby gateway which performs preliminary data analysis, commonly referred to as fog computing, to make sure emergency personnel and healthcare providers are notified in case patient being monitored is at risk. To achieve power autonomy three energy harvesting sources are proposed, namely, solar, RF and thermal. The design of the RF energy harvesting system is demonstrated, where novel multiband antenna is fabricated as well as an efficient RF-DC rectifier achieving maximum conversion efficiency of 84%. Finally, the sensor node is tested with different type of sensors and settings while being solely powered by a Photovoltaic (PV) solar cell.

  • 5. Aslam, B.
    et al.
    Khan, U. H.
    Azam, M. A.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Elektronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Loo, J.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Elektronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Miniaturized decoupled slotted patch RFID tag antennas for wearable health care2017In: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 27, no 1, article id e21048Article in journal (Refereed)
    Abstract [en]

    In this article, a couple of two-layered RFID tag antenna designs exhibiting improved performance descriptors for on-body applications are presented. The antennas are designed to operate in the microwave band (2.4–2.48 GHz) ensuring high data transmission rates ideal for real-time subject monitoring applications. The radiating element of both the antennas is a slotted patch structure provisioned with a pair of T-shaped slots realized on a commercial FR4 substrate. The augmentation of a systematic sequence of narrow comb-like etchings into the design enhances the impedance bandwidth considerably. A high permittivity silicon layer embedded with the radiating patch provides resilience from the human body dielectric losses. A modified antenna design utilizing patch miniaturization technique, resulting in an overall footprint reduction by 32%, is also proposed. The designed tag antennas offer a gain of more than 1.8 dBi and an attractive read range greater than 6.8 m in the operating band.

  • 6. Aslam, Bilal
    et al.
    Khan, Umar Hasan
    Azam, Muhammad Awais
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronics. Univ Engn & Technol, Pakistan.
    Loo, Jonathan
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Univ Turku, Finland.
    A compact implantable RFID tag antenna dedicated to wireless health care2017In: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 27, no 5, article id e21094Article in journal (Refereed)
    Abstract [en]

    Implantable tag antennas are an integral component of contemporary pervasive patient monitoring setups envisioned to reduce the medical errors and improve the quality of health care facilities. These tags, embedded into the human body, transmit critical patient information to the external equipment via a wireless communication link. This research article presents an implantable compact folded dipole antenna of size 10 mm 3 15 mm 3 2 mm, designed to operate in the industrial-scientificmedical band (2.4-2.48GHz). A three-layered phantom representing the human arm is used to evaluate the subcutaneous antenna performance. The tag antenna embedded in the middle of the fat layer offers a maximum gain of 216.3 dBi. The tag antenna performance as a function of implant position and phantom dimensions is analyzed. Link budget calculations show that with the achieved antenna gain the link power exceeds the required power by 38.37 dBm, and hence wireless communication is viable.

  • 7. Attarzadeh-Niaki, S. -H
    et al.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Automatic construction of models for analytic system-level design space exploration problems2017In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 670-673, article id 7927074Conference paper (Refereed)
    Abstract [en]

    Due to the variety of application models and also the target platforms used in embedded electronic system design, it is challenging to formulate a generic and extensible analytic design-space exploration (DSE) framework. Current approaches support a restricted class of application and platform models and are difficult to extend. This paper proposes a framework for automatic construction of system-level DSE problem models based on a coherent, constraint-based representation of system functionality, flexible target platforms, and binding policies. Heterogeneous semantics is captured using constraints on logical clocks. The applicability of this method is demonstrated by constructing DSE problem models from different combinations of application and platforms models. Time-triggered and untimed models of the system functionality and heterogeneous target platforms are used for this purpose. Another potential advantage of this approach is that constructed models can be solved using a variety of standard and ad-hoc solvers and search heuristics.

  • 8. Ayedh, H. M.
    et al.
    Iwamoto, N.
    Nipoti, R.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Svensson, B. G.
    Formation of D-Center in p-type 4H-SiC epi-layers during high temperature treatments2017In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Inc., 2017, Vol. 897, p. 262-265Conference paper (Refereed)
    Abstract [en]

    The current work is devoted to studying the evolution of deep level defects in the lower half of the 4H-SiC bandgap after high temperature processing and ion implantation. Two as-grown and pre-oxidized 4H-SiC sets of samples have been thermally treated at temperatures up to 1950 °C for 10 min duration using RF inductive heating. Another set of as grown samples was implanted by 4.2 MeV Si ions at room temperature (RT) with different doses (1- 4×108 cm-2). The so-called “D-center” at EV+0.6 eV dominates and forms after the elevated heat treatments, while it shows no change after the ion implantations (EV denotes the valence band edge). In contrast, the concentration of the so-called HK4 level at EV+1.44 eV increases with the implantation dose, whereas it anneals out after heat treatment at ≥ 1700 °C.

  • 9. Ayedh, H. M.
    et al.
    Nipoti, R.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Svensson, B. G.
    Thermodynamic equilibration of the carbon vacancy in 4H-SiC: A lifetime limiting defect2017In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 122, no 2, article id 025701Article in journal (Refereed)
    Abstract [en]

    The carbon vacancy (V-C) is a prominent defect in as-grown 4H-SiC epitaxial layers for high power bipolar devices. V-C is electrically active with several deep levels in the bandgap, and it is an efficient "killer" of the minority carrier lifetime in n-type layers, limiting device performance. In this study, we provide new insight into the equilibration kinetics of the thermodynamic processes governing the V-C concentration and how these processes can be tailored. A slow cooling rate after heat treatment at similar to 2000 degrees C, typically employed to activate dopants in 4H-SiC, is shown to yield a strong reduction of the V-C concentration relative to that for a fast rate. Further, post-growth heat treatment of epitaxial layers has been conducted over a wide temperature range (800-1600 degrees C) under C-rich surface conditions. It is found that the thermodynamic equilibration of V-C at 1500 degrees C requires a duration less than 1 h resulting in a V-C concentration of only similar to 10(11) cm(-3), which is, indeed, beneficial for high voltage devices. In order to elucidate the physical processes controlling the equilibration of V-C, a defect kinetics model is put forward. The model assumes Frenkel pair generation, injection of carbon interstitials (C-i's) from the C-rich surface (followed by recombination with V-C's), and diffusion of V-C's towards the surface as the major processes during the equilibration, and it exhibits good quantitative agreement with experiment.

  • 10. Azarov, Alexander
    et al.
    Rauwel, Protima
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Monakhov, Edouard
    Svensson, Bengt G.
    Extended defects in ZnO: Efficient sinks for point defects2017In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 110, no 2, article id 022103Article in journal (Refereed)
    Abstract [en]

    Dopant-defect reactions dominate the defect formation in mono-crystalline ZnO samples implanted with Ag and B ions. This is in contrast to most other ion species studied and results in an enhanced concentration of extended defects, such as stacking faults and defect clusters. Using a combination of B and Ag implants and diffusion of residual Li atoms as a tracer, we demonstrate that extended defects in ZnO act as efficient traps for highly mobile Zn interstitials. The results imply that dynamic annealing involving interaction of point defects with extended ones can play a key role in the disorder saturation observed for ZnO and other radiation-hard semiconductors implanted with high doses.

  • 11.
    Badawi, Mohammad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture2017In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 54, p. 47-59Article in journal (Refereed)
    Abstract [en]

    Employing adaptable protocol processing architectures has shown a high potential in provisioning Quality-of-Service (QoS) while retaining efficient use of available energy budget. Nevertheless, successful QoS provisioning using adaptable protocol processing architectures requires adaption to be agile and to have low latency. That is, a long adaptation latency might lead to violating desired packet processing latency, desired throughput or loss of packets if the memory fails to accommodate packet accumulation. This paper presents an elastic management scheme to permit agile and QoS-aware adaptation of processing elements (PEs) within the protocol processing architecture, such that desired QoS is maintained. Moreover, our proposed scheme has the potential to reduce energy consumption since it employs the PEs upon demand. We quantify the latency required for PEs adaptation, the reduction in energy and the reduction in area that can be achieved using our scheme. We also consider two different real-life use cases to demonstrate the effectiveness of our proposed management scheme in maintaining QoS while conserving available energy.

  • 12.
    Banuazizi, Seyed Amir Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Sani, Sohrab R.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Naiini, Maziar M.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Mohseni, Seyed Majid
    Chung, Sunjae
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. Univ Gothenburg, Sweden.
    Durrenfeld, Philipp
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics. Univ Gothenburg, Sweden.
    Order of magnitude improvement of nano-contact spin torque nano-oscillator performance2017In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 9, no 5, p. 1896-1900Article in journal (Refereed)
    Abstract [en]

    Spin torque nano-oscillators (STNO) represent a unique class of nano-scale microwave signal generators and offer a combination of intriguing properties, such as nano sized footprint, ultrafast modulation rates, and highly tunable microwave frequencies from 100 MHz to close to 100 GHz. However, their low output power and relatively high threshold current still limit their applicability and must be improved. In this study, we investigate the influence of the bottom Cu electrode thickness (t(Cu)) in nano-contact STNOs based on Co/Cu/NiFe GMR stacks and with nano-contact diameters ranging from 60 to 500 nm. Increasing t(Cu) from 10 to 70 nm results in a 40% reduction of the threshold current, an order of magnitude higher microwave output power, and close to two orders of magnitude better power conversion efficiency. Numerical simulations of the current distribution suggest that these dramatic improvements originate from a strongly reduced lateral current spread in the magneto-dynamically active region.

  • 13.
    Banuazizi, Seyed
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Sani, S. R.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Naiini, Maziar Manouchehry
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Mohseni, S.
    Chung, S.
    Dürrenfeld, P.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Engineering Sciences (SCI), Applied Physics.
    Order of magnitude improvement of nano-contact spin torque nano-oscillator performance2017In: 2017 IEEE International Magnetics Conference, INTERMAG 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, article id 8007567Conference paper (Refereed)
    Abstract [en]

    Spin torque nano-oscillators [1,2] (STNO) represent a unique class of nano-scale microwave signal generators where spin transfer torque [3-5] (STT) from a direct spin-polarized current drives and controls the auto-oscillation of the local free layer magnetization, which through its oscillating magnetoresistance transforms the direct current into a tunable microwave voltage.

  • 14. Ben Dhaou, I.
    et al.
    Gia, T. N.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Low-latency hardware architecture for cipher-based message authentication code2017In: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Institute of Electrical and Electronics Engineers (IEEE), 2017, article id 8050840Conference paper (Refereed)
    Abstract [en]

    Cipher-based message authentication code, CMAC, is a NIST approved standard for checking message integrity and authentication. This work presents a low-latency AES architecture for CMAC. The architecture uses intensive parallel processing per round and takes advantage of the BRAM present in modern FPGA. Experimental results show that for typical IoT application, the proposed architecture has a latency of 10 clock cycles, consumes 1355 slices, 2 BRAMs and achieves a throughput of 3.8Gbps.

  • 15.
    Chaourani, Panagiotis
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Towards Monolithic 3D Integration: A Design Flow2016In: CDNLive2016, Cadence User Conference EMEA, Munich, Germany, May 2-4, 2016, 2016Conference paper (Refereed)
    Abstract [en]

    Monolithic 3D (M3D) integration is considered as a key enabling technology for thecontinuation of Moore’s Law. To facilitate the study of M3D circuits, a design flow isclearly needed. In this work we discuss the potentials and challenges of thistechnology and present a design flow for M3D circuits which includes a M3D ProcessDesign Kit (PDK) with parametric extraction capabilities.

  • 16.
    Chaourani, Panagiotis
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Onet, Raul
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Enabling Area Efficient RF ICs through Monolithic 3D Integration2017In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 610-613, article id 7927059Conference paper (Refereed)
    Abstract [en]

    The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

  • 17.
    Chen, Dejiu
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    A methodological framework for model-based self-management of services and components in dependable cyber-physical systems2017In: 12th International Conference on Dependability and Complex Systems, DepCoS-RELCOMEX 2017, Springer, 2017, Vol. 582, p. 97-105Conference paper (Refereed)
    Abstract [en]

    Modern automotive vehicles featuring ADAS (Advanced Driving Assistant Systems) and AD (Autonomous Driving) represent one category of dependable CPS (Cyber-Physical Systems). For such systems, the adaptation of generic purpose COTS (Commercial-Off-The-Shelf) services and components has been advocated in the industry as a necessary means for shortening the innovation loops and enabling efficient product evolution. This will however not be a trivial task due to the system safety- and time-criticality. This calls on one hand for formal specification of systems, and on the other hand for a systematic approach to module design, supervision and adaptions. Accordingly, we propose in this paper a novel method that emphasizes an integration of system models, formal contracts, and embedded services for effective self-management of COTS. The key modeling technologies include the EAST-ADL for formal system description and the A-G contract theory for module specification.

  • 18.
    Chen, DeJiu
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Embedded Control Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    A Model-based Approach to Dynamic Self-Assessment for Automated Performance and Safety Awareness of Cyber-Physical Systems2017In: Model-Based Safety and Assessment - 5th International Symposium, Trento, Italy, September 11–13, 2017 / [ed] Marco Bozzano, Yiannis Papadopoulos, Springer, 2017, Vol. LNCS 10437, p. 227-240Conference paper (Refereed)
    Abstract [en]

    Modern automotive vehicles represent one category of CPS (Cyber-Physical Systems) that are inherently time- and safety-critical. To justify the actions for quality-of-service adaptation and safety assurance, it is fundamental to perceive the uncertainties of system components in operation, which are caused by emergent properties, design or operation anomalies. From an industrial point of view, a further challenge is related to the usages of generic purpose COTS (Commercial-Off-The-Shelf) components, which are separately developed and evolved, often not sufficiently verified and validated for specific automotive contexts. While introducing additional uncertainties in regard to the overall system performance and safety, the adoption of COTS components constitutes a necessary means for effective product evolution and innovation. Accordingly, we propose in this paper a novel approach that aims to enable advanced operation monitoring and self-assessment in regard to operational uncertainties and thereby automated performance and safety awareness. The emphasis is on the integration of several modeling technologies, including the domain-specific modeling framework EAST-ADL, the A-G contract theory and Hidden Markov Model (HMM). In particular, we also present some initial concepts in regard to the usage performance and safety awareness for quality-of-service adaptation and dynamic risk mitigation.

  • 19.
    Chen, Xiamen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems. National University of Defense Technology, China.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Lei, Yuanwu
    Wang, Yaohua
    Chen, Shenggang
    Multi-bit Transient Fault Control for NoC Links Using 2D Fault Coding Method2016In: 2016 TENTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), IEEE, 2016Conference paper (Refereed)
    Abstract [en]

    In deep nanometer scale, Network-on-Chip (NoC) links are more prone to multi-bit transient fault. Conventional ECC techniques brings heavy area, power, and timing overheads when correcting and detecting multiple transient faults. Therefore, a cost-effective ECC technique, named 2D fault coding method, is adopted to overcome the multi-bit transient fault issue of NoC links. Its key innovation is that the wires of a link are treated as its matrix appearance and light-weight Parity Check Coding (PCC) is performed on the matrix's two dimensions (horizontal matrix rows and vertical matrix columns). Horizontal PCCs and vertical PCCs work together to find the faults' position and then correct them by simply inverting them. The procedure of using the 2D fault coding method to protect a NoC link is proposed, its correction and detection capability is analyzed, and its hardware implementation is carried out. Comparative experiments show that the proposal can largely reduce the ECC hardware cost, have much higher fault detection coverage, maintain almost zero silent fault percentages, and have higher fault correction percentages normalized under the same area, demonstrating that it is cost-effective and suitable to the multi-bit transient fault control for NoC links.

  • 20.
    Chen, Xiaowen
    et al.
    KTH, School of Electrical Engineering (EES).
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronics.
    Liu, S.
    Chen, S.
    Round-trip DRAM access fairness in 3D NoC-based many-core systems2017In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 16, no 5s, article id 162Article in journal (Refereed)
    Abstract [en]

    In 3D NoC-based many-core systems, DRAM accesses behave differently due to their different communication distances and the latency gap of different DRAM accesses becomes bigger as the network size increases, which leads to unfair DRAM access performance among different nodes. This phenomenon may lead to high latencies for some DRAM accesses that become the performance bottleneck of the system. The paper addresses the DRAM access fairness problem in 3D NoC-based many-core systems by narrowing the latency difference of DRAM accesses as well as reducing the maximum latency. Firstly, the latency of a round-trip DRAM access is modeled and the factors causing DRAM access latency difference are discussed in detail. Secondly, the DRAM access fairness is further quantitatively analyzed through experiments. Thirdly, we propose to predict the network latency of round-trip DRAM accesses and use the predicted round-trip DRAM access time as the basis to prioritize the DRAM accesses in DRAM interfaces so that the DRAM accesses with potential high latencies can be transferred as early and fast as possible, thus achieving fair DRAM access. Experiments with synthetic and application workloads validate that our approach can achieve fair DRAM access and outperform the traditional First-Come-First-Serve (FCFS) scheduling policy and the scheduling policies proposed by reference [7] and [24] in terms of maximum latency, Latency Standard Deviation (LSD)1 and speedup. In the experiments, the maximum improvement of the maximum latency, LSD, and speedup are 12.8%, 6.57%, and 8.3% respectively. Besides, our proposal brings very small extra hardware overhead (<0.6%) in comparison to the three counterparts.

  • 21.
    Chen, Xiaowen
    et al.
    KTH. National University of Defense Technology, KTH Royal Institute of Technology, China.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Liu, Sheng
    Chen, Shuming
    Round-trip DRAM Access Fairness in 3D NoC-based Many-core Systems2017In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 16, article id 162Article in journal (Refereed)
    Abstract [en]

    In 3D NoC-based many-core systems, DRAM accesses behave differently due to their different communication distances and the latency gap of different DRAM accesses becomes bigger as the network size increases, which leads to unfair DRAM access performance among different nodes. This phenomenon may lead to high latencies for some DRAM accesses that become the performance bottleneck of the system. The paper addresses the DRAM access fairness problem in 3D NoC-based many-core systems by narrowing the latency difference of DRAM accesses as well as reducing the maximum latency. Firstly, the latency of a round-trip DRAM access is modeled and the factors causing DRAM access latency difference are discussed in detail. Secondly, the DRAM access fairness is further quantitatively analyzed through experiments. Thirdly, we propose to predict the network latency of round-trip DRAM accesses and use the predicted round-trip DRAM access time as the basis to prioritize the DRAM accesses in DRAM interfaces so that the DRAM accesses with potential high latencies can be transferred as early and fast as possible, thus achieving fair DRAM access. Experiments with synthetic and application workloads validate that our approach can achieve fair DRAM access and outperform the traditional First-Come-First-Serve (FCFS) scheduling policy and the scheduling policies proposed by reference [7] and [24] in terms of maximum latency, Latency Standard Deviation (LSD) 1 and speedup. In the experiments, the maximum improvement of the maximum latency, LSD, and speedup are 12.8%, 6.57%, and 8.3% respectively. Besides, our proposal brings very small extra hardware overhead (< 0.6%) in comparison to the three counterparts.

  • 22. Chen, Y.
    et al.
    Praamsma, L.
    Ivanisevic, Nikola
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Leenaerts, D. M. W.
    A 40GHz PLL with -92.5dBc/Hz in-band phase noise and 104fs-RMS-jitter2017In: Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 31-32Conference paper (Refereed)
    Abstract [en]

    This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-μm SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise <-92.5dBc/Hz and an integrated RMS jitter of 104fs, a 25% improvement over conventional PFD. The reference spurs are <-73dBc across the whole locking range.

  • 23. Chulapakorn, T.
    et al.
    Primetzhofer, D.
    Sychugov, Ilya
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Suvanam, Sethu Saveda
    KTH, School of Information and Communication Technology (ICT).
    Linnros, Jan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Impact of H-uptake by forming gas annealing and ion implantation on photoluminescence of Si-nanoparticles2018In: Physica Status Solidi (a) applications and materials science, ISSN 1862-6300, E-ISSN 1862-6319, Vol. 215, no 3, article id 1700444Article in journal (Refereed)
    Abstract [en]

    Silicon nanoparticles (SiNPs) are formed by implanting 70 keV Si+ into a SiO2-film and subsequent thermal annealing. SiNP samples are further annealed in forming gas. Another group of samples containing SiNP is implanted by 7.5 keV H+ and subsequently annealed in N2-atmosphere at 450 °C to reduce implantation damage. Nuclear reaction analysis (NRA) is employed to establish depth profiles of the H-concentration. Enhanced hydrogen concentrations are found close to the SiO2surface, with particularly high concentrations for the as-implanted SiO2. However, no detectable uptake of hydrogen is observed by NRA for samples treated by forming gas annealing (FGA). H-concentrations detected after H-implantation follow calculated implantation profiles. Photoluminescence (PL) spectroscopy is performed at room temperature to observe the SiNP PL. Whereas FGA is found to increase PL under certain conditions, i.e., annealing at high temperatures, increasing implantation fluence of H reduces the SiNP PL. Hydrogen implantation also introduces additional defect PL. After low-temperature annealing, the SiNP PL is found to improve, but the process is not found equivalently efficient as conventional FGA.

  • 24. Chulapakorn, T.
    et al.
    Sychugov, Ilya
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Suvanam, Sethu Saveda
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Linnros, Jan T.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Primetzhofer, D.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    MeV ion irradiation effects on the luminescence properties of Si-implanted SiO2-thin films2016In: Physica Status Solidi (C) Current Topics in Solid State Physics, ISSN 1862-6351, Vol. 13, no 10-12, p. 921-926Article in journal (Refereed)
    Abstract [en]

    The effects of MeV heavy ion irradiation at varying fluence and flux on excess Si, introduced in SiO2 by keV ion implantation, are investigated by photoluminescence (PL). From the PL peak wavelength (λ) and decay lifetime (τ), two PL sources are distinguished: i) quasi-direct recombination of excitons of Si-nanoparticles (SiNPs), appearing after thermal annealing (λ &gt; 720 nm, τ ∼ μs), and ii) fast-decay PL, possibly due to oxide-related defects (λ ∼ 575-690 nm, τ ∼ ns). The fast-decay PL (ii) observed before and after ion irradiation is induced by ion implantation. It is found that this fast-decay luminescence decreases for higher irradiation fluence of MeV heavy ions. After thermal annealing (forming SiNPs), the SiNP PL is reduced for samples irradiated by MeV heavy ions but found to stabilize at higher level for higher irradiation flux; the (ii) band vanishes as a result of annealing. The results are discussed in terms of the influence of electronic and nuclear stopping powers.

  • 25.
    Colmenares, Juan
    et al.
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electric Power and Energy Systems.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Temperature Passive Components for Extreme Environments2016In: 2016 IEEE 4TH WORKSHOP ON WIDE BANDGAP POWER DEVICES AND APPLICATIONS (WIPDA), IEEE conference proceedings, 2016, p. 271-274Conference paper (Refereed)
    Abstract [en]

    Silicon carbide is an excellent candidate when high temperature power electronics applications are considered. Integrated circuits as well as several power devices have been tested at high temperature. However, little attention has been paid to high temperature passive components that could enable the full SiC potential. In this work, the high-temperature performances of different passive components have been studied. Integrated capacitors in bipolar SiC technology have been tested up to 300 degrees C and, three different designs of inductors have been tested up to 700 degrees C.

  • 26.
    Delekta, Szymon Sollami
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Smith, Anderson David
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Inkjet printed highly transparent and flexible graphene micro-supercapacitors2017In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 9, no 21, p. 6998-7005Article in journal (Refereed)
    Abstract [en]

    Modern energy storage devices for portable and wearable technologies must fulfill a number of requirements, such as small size, flexibility, thinness, reliability, transparency, manufacturing simplicity and performance, in order to be competitive in an ever expanding market. To this end, a comprehensive inkjet printing process is developed for the scalable and low-cost fabrication of transparent and flexible micro-supercapacitors. These solid-state devices, with printed thin films of graphene flakes as interdigitated electrodes, exhibit excellent performance versus transparency (ranging from a single-electrode areal capacitance of 16 mu F cm(-2) at transmittance of 90% to a capacitance of 99 mu F cm(-2) at transmittance of 71%). Also, transparent and flexible devices are fabricated, showing negligible capacitance degradation during bending. The ease of manufacturing coupled with their great capacitive properties opens up new potential applications for energy storage devices ranging from portable solar cells to wearable sensors.

  • 27. Dhaou, I. B.
    et al.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Design techniques of 5G mobile devices in the dark silicon era2016In: 5G Mobile Communications, Springer International Publishing , 2016, p. 381-400Chapter in book (Other academic)
    Abstract [en]

    In the internet of things age, future communication technologies should provide the necessary bandwidth and latency for the connection of billion devices and the development of ubiquitous applications to improve the quality of life. The design of the prospected mobile communication system needs wide skills in wireless communication, analog circuit design, embedded system, microwave technology, and so forth. System level analyses, design space exploration, performance tradeoffs are some key steps that enable the design of low-cost, energy efficient, ubiquitous and flexible transceiver. This chapter provides comprehensive design techniques for 5G mobile communication in the dark silicon era and using More than Moore technology (MtM). 

  • 28. Du, G.
    et al.
    Ma, S.
    Li, Z.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Ouyang, Y.
    Gao, M.
    Work-in-progress: SSS: Self-aware system-on-chip using static-dynamic hybrid method2017In: Proceedings of the 2017 International Conference on Compilers, Architectures and Synthesis for Embedded Systems Companion, CASES 2017, Association for Computing Machinery (ACM), 2017, article id 3125527Conference paper (Refereed)
    Abstract [en]

    Network on chip has become the de facto communication standard for multi-core or many-core system on chip, due to its scalability and flexibility. However, temperature is an important factor in NoC design, which affects the overall performance of SoC-decreasing circuit frequency, increasing energy consumption, and even shortening chip lifetime. In this paper, we propose SSS, a self-aware SoC using a static-dynamic hybrid method, which combines dynamic mapping and static mapping to reduce the hot-spots temperature for NoC based SoCs. First, we propose monitoring the thermal distribution for self-state sensoring. Then, in static mapping stage, we calculate the optimal mapping solutions under different temperature modes using discrete firefly algorithm to help self-decision making. Finally, in dynamic mapping stage, we achieve dynamic mapping through configuring NoC and SoC sentient unit for selfoptimizing. Experimental results show SSS can reduce the peak temperature by up to 30.64%. FPGA prototype shows the effectiveness and smartness of SSS in reducing hot-spots temperature. Self-awareness, SoC architecture, NoC.

  • 29.
    Ebrahimi, Masoumeh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Daneshtalab, Masoud
    MDH.
    EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks2017In: In Proceedings of ISCA ’17, ACM Press, 2017, p. 1-13Conference paper (Refereed)
    Abstract [en]

    Freedom from deadlock is one of the most important issues whendesigning routing algorithms in on-chip/off-chip networks. Manyworks have been developed upon Dally’s theory proving that a networkis deadlock-free if there is no cyclic dependency on the channeldependency graph. However, finding such acyclic graph has beenvery challenging, which limits Dally’s theory to networks with a lownumber of channels. In this paper, we introduce three theorems thatdirectly lead to routing algorithms with an acyclic channel dependencygraph.We also propose the partitioning methodology, enablinga design to reach the maximum adaptiveness for the n-dimensionalmesh and k-ary n-cube topologies with any given number of channels.In addition, deadlock-free routing algorithms can be derivedranging from maximally fully adaptive routing down to deterministicrouting. The proposed theorems can drastically remove thedifficulties of designing deadlock-free routing algorithms.

  • 30. Ebrahimi, P.
    et al.
    Kolahdouz, M.
    Iraj, M.
    Ganjian, M.
    Aghababa, H.
    Asl-Soleimani, E.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Systematic Optimization of Boron Diffusion for Solar Cell Emitters2017In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 46, no 7, p. 4236-4241Article in journal (Refereed)
    Abstract [en]

    To achieve p-n junctions for n-type solar cells, we have studied BBr3 diffusion in an open tube furnace, varying parameters of the BBr3 diffusion process such as temperature, gas flows, and duration of individual process steps, i.e., predeposition and drive-in. Then, output parameters such as carrier lifetime, sheet resistance, and diffusion profile were measured and statistically analyzed to optimize the emitter characteristics. Statistical analysis (factorial design) was finally employed to systematically explore the effects of the set of input variables on the outputs. The effect of the interactions between inputs was also evaluated for each output, quantified using a two-level factorial method. Temperature and BBr3 flow were found to have the most significant effect on different outputs such as carrier lifetime, junction depth, sheet resistance, and final surface concentration.

  • 31.
    Ekström, Mattias
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Khartsev, Sergiy
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Integration and High-Temperature Characterization of Ferroelectric Vanadium-Doped Bismuth Titanate Thin Films on Silicon Carbide2017In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 46, no 7, p. 4478-4484Article in journal (Refereed)
    Abstract [en]

    4H-SiC electronics can operate at high temperature (HT), e.g., 300A degrees C to 500A degrees C, for extended times. Systems using sensors and amplifiers that operate at HT would benefit from microcontrollers which can also operate at HT. Microcontrollers require nonvolatile memory (NVM) for computer programs. In this work, we demonstrate the possibility of integrating ferroelectric vanadium-doped bismuth titanate (BiTV) thin films on 4H-SiC for HT memory applications, with BiTV ferroelectric capacitors providing memory functionality. Film deposition was achieved by laser ablation on Pt (111)/TiO2/4H-SiC substrates, with magnetron-sputtered Pt used as bottom electrode and thermally evaporated Au as upper contacts. Film characterization by x-ray diffraction analysis revealed predominately (117) orientation. P-E hysteresis loops measured at room temperature showed maximum 2P (r) of 48 mu C/cm(2), large enough for wide read margins. P-E loops were measurable up to 450A degrees C, with losses limiting measurements above 450A degrees C. The phase-transition temperature was determined to be about 660A degrees C from the discontinuity in dielectric permittivity, close to what is achieved for ceramics. These BiTV ferroelectric capacitors demonstrate potential for use in HT NVM applications for SiC digital electronics.

  • 32.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Design Optimization and Realization of 4H-SiC Bipolar Junction Transistors2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    4H-SiC-based bipolar junction transistors (BJTs) are attractive devices for high-voltage and high-temperature operations due to their high current capability, low specific on-resistance, and process simplicity. To extend the potential of SiC BJTs to power electronic industrial applications, it is essential to realize high-efficient devices with high-current and low-loss by a reliable and wafer-scale fabrication process. In this thesis, we focus on the improvement of the 4H-SiC BJT performance, including the device optimization and process development.

    To optimize the 4H-SiC BJT design, a comprehensive study in terms of cell geometries, device scaling, and device layout is performed. The hexagon-cell geometry shows 42% higher current density and 21% lower specific on-resistance at a given maximum current gain compared to the interdigitated finger design. Also, a layout design, called intertwined, is used for 100% usage of the conducting area. A higher current is achieved by saving the inactive portion of the conducting area. Different multi-step etched edge termination techniques with an efficiency of >92% are realized.

    Regarding the process development, an improved surface passivation is used to reduce the surface recombination and improve the maximum current gain of 4H-SiC BJTs. Moreover, wafer-scale lift-off-free processes for the n- and p-Ohmic contact technologies to 4H-SiC are successfully developed. Both Ohmic metal technologies are based on a self-aligned Ni-silicide (Ni-SALICIDE) process.

    Regarding the device characterization, a maximum current gain of 40, a specific on-resistance of 20 mΩ·cm2, and a maximum breakdown voltage of 5.85 kV for the 4H-SiC BJTs are measured. By employing the enhanced surface passivation, a maximum current gain of 139 and a specific on-resistance of 579 mΩ·cm2 at the current density of 89 A/cm2 for the 15-kV class BJTs are obtained. Moreover, low-voltage 4H-SiC lateral BJTs and Darlington pair with output current of 1−15 A for high-temperature operations up to 500 °C were fabricated.

    This thesis focuses on the improvement of the 4H-SiC BJT performance in terms of the device optimization and process development for high-voltage and high-temperature applications. The epilayer design and the device structure and topology are optimized to realize high-efficient BJTs. Also, wafer-scale fabrication process steps are developed to enable realization of high-current devices for the real applications.

  • 33.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    A wafer-scale Ni-salicide contact technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. P197-P200Article in journal (Refereed)
    Abstract [en]

    A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

  • 34.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    A Wafer-Scale Self-Aligned Ni-Silicide (SALICIDE) Low-Ohmic Contact Technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. 197-200Article in journal (Refereed)
    Abstract [en]

    A self-aligned nickel (Ni) silicide process for n-type Ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5×10-6 Ω·cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale, which saves time and cost.

  • 35.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    500 °C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits2017In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563Article in journal (Refereed)
    Abstract [en]

    High-current 4H-SiC lateral BJTs for high-temperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (JC), lower on-resistance (RON), and more uniform current distribution. A maximum current gain (β) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs are measured from room temperature to 500 °C. An open-base breakdown voltage (VCEO) of >50 V is measured for the devices.

  • 36.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Kargarrazi, Saleh
    KTH, School of Information and Communication Technology (ICT).
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    500 degrees C High Current 4H-SiC Lateral BJTs for High-Temperature Integrated Circuits2017In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 38, no 10, p. 1429-1432Article in journal (Refereed)
    Abstract [en]

    High-current 4H-SiC lateral BJTs for hightemperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (J(C)), lower on-resistance (R-ON), and more uniform current distribution. A maximum current gain (beta) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs aremeasured fromroom temperature to 500 degrees C. An open-base breakdown voltage (V-CEO) of > 50 V is measured for the devices.

  • 37.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetteling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices2016In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 858, p. 978-981Article in journal (Other (popular science, discussion, etc.))
    Abstract [en]

    High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) are fabricated and optimized in terms of the length and remaining dose of JTEs. It is found that the JTE1 is the most effective one in spreading the electric field. Hence, for a given total termination length, a decremental JTE length from the innermost edge to the outermost mesa edge of the device results in better modification of the electric field. A breakdown voltage of 4.95 kV is measured for the modified device, which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches are fabricated. It is presented that the maximum current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

  • 38.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. Ascatron AB, Sweden.
    Thierry-Jebali, N.
    Reshanov, S. A.
    Kaplan, W.
    Zhang, A.
    Lim, J. -K
    Bakowski, M.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Schöner, A.
    Design optimization of a high temperature 1.2 kV 4H-SiC buried grid JBS rectifier2017In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Inc., 2017, Vol. 897, p. 455-458Conference paper (Refereed)
    Abstract [en]

    1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device behavior at temperatures ranging from 25 to 250ºC is analyzed and measured on wafer level. The forward voltage drop of 1.1 V at 100 A/cm2 and 3.8 V at 1000 A/cm2 is measured, respectively. At reverse voltage of 1 kV, a leakage current density below 0.1 μA/cm2 and below 0.1 mA/cm2 is measured at 25 and 250ºC, respectively. This proves the effective shielding effect of the BG-JBS design and provides benefits in high voltage applications, particularly for high temperature operation.

  • 39.
    Elgammal, Karim
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics. KTH, Centres, SeRC - Swedish e-Science Research Centre.
    Hugosson, Håkan W.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. Chalmers Institute of Technology, Sweden.
    Råsander, Mikael
    Bergqvist, Lars
    KTH, School of Engineering Sciences (SCI), Applied Physics. KTH, Centres, SeRC - Swedish e-Science Research Centre.
    Delin, Anna
    KTH, School of Engineering Sciences (SCI), Applied Physics. KTH, Centres, SeRC - Swedish e-Science Research Centre. Uppsala University, Sweden.
    Density functional calculations of graphene-based humidity and carbon dioxide sensors: effect of silica and sapphire substrates2017In: Surface Science, ISSN 0039-6028, E-ISSN 1879-2758, Vol. 663, p. 23-30Article in journal (Refereed)
    Abstract [en]

    We present dispersion-corrected density functional calculations of water and carbon dioxide molecules adsorption on graphene residing on silica and sapphire substrates. The equilibrium positions and bonding distances for the molecules are determined. Water is found to prefer the hollow site in the center of the graphene hexagon, whereas carbon dioxide prefers sites bridging carbon-carbon bonds as well as sites directly on top of carbon atoms. The energy differences between different sites are however minute - typically just a few tenths of a millielectronvolt. Overall, the molecule-graphene bonding distances are found to be in the range 3.1-3.3 (A) over circle. The carbon dioxide binding energy to graphene is found to be almost twice that of the water binding energy (around 0.17 eV compared to around 0.09 eV). The present results compare well with previous calculations, where available. Using charge density differences, we also qualitatively illustrate the effect of the different substrates and molecules on the electronic structure of the graphene sheet.

  • 40. Fakih, M.
    et al.
    Lenz, A.
    Azkarate-Askasua, M.
    Coronel, J.
    Crespo, A.
    Davidmann, S.
    Diaz Garcia, J. C.
    Romero, N. G.
    Grüttner, K.
    Schreiner, S.
    Seyyedi, R.
    Obermaisser, R.
    Maleki, A.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Mohammadat, Mohamed Tagelsir
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Pérez-Cerrolaza, J.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Söderquist, I.
    SAFEPOWER project: Architecture for safe and power-efficient mixed-criticality systems2017In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 52, p. 89-105Article in journal (Refereed)
    Abstract [en]

    With the ever increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible without regarding their criticality. Even safety critical domains like railway and avionics apply these paradigms under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such System on Chip (SoC) is to enhance the way the SoC handles its power resources. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power saving methods in safety critical domains yet. The EU project SAFEPOWER1.

  • 41.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. KTH Royal Institute of Technology.
    Elgammal, Karim
    KTH, Centres, SeRC - Swedish e-Science Research Centre. KTH, School of Engineering Sciences (SCI), Applied Physics.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Delin, Anna
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering. KTH, Centres, SeRC - Swedish e-Science Research Centre. Department of Physics and Astronomy, Materials Theory Division, Uppsala University, Box 516, SE-75120 Uppsala, Sweden.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. Department of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. KTH Royal Institute of Technology.
    Humidity and CO2 gas sensing properties of double-layer graphene2018In: Carbon, ISSN 0008-6223, E-ISSN 1873-3891, Vol. 127, p. 576-587Article in journal (Refereed)
    Abstract [en]

    Graphene has interesting gas sensing properties with strong responses of the graphene resistance when exposed to gases. However, the resistance response of double-layer graphene when exposed to humidity and gasses has not yet been characterized and understood. In this paper we study the resistance response of double-layer graphene when exposed to humidity and CO2, respectively. The measured response and recovery times of the graphene resistance to humidity are on the order of several hundred milliseconds. For relative humidity levels of less than ~ 3% RH, the resistance of double-layer graphene is not significantly influenced by the humidity variation. We use such a low humidity atmosphere to investigate the resistance response of double-layer graphene that is exposed to pure CO2 gas, showing a consistent response and recovery behaviour. The resistance of the double-layer graphene decreases linearly with increase of the concentration of pure CO2 gas. Density functional theory simulations indicate that double-layer graphene has a weaker gas response compared to single-layer graphene, which is in agreement with our experimental data. Our investigations contribute to improved understanding of the humidity and CO2 gas sensing properties of double-layer graphene which is important for realizing viable graphene-based gas sensors in the future.

  • 42.
    Grishin, Alexander M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics. Petrozavodsk State University, Russian Federation; NMATECH Intelligent Materials Technology, Sweden.
    Putrolaynen, V. V.
    Yuzvyuk, M. H.
    Ultra-hard amorphous AlMgB14 films RF sputtered onto curved substrates2017In: MATERIALS RESEARCH EXPRESS, ISSN 2053-1591, Vol. 4, no 3, article id 036406Article in journal (Refereed)
    Abstract [en]

    Recently, hard AlMgB14 (BAM) coatings were deposited for the first time by RF magnetron sputtering using a single stoichiometric ceramic target. High target sputtering power and sufficiently short target-to-substrate distance were found to be critical processing conditions. They enabled fabrication of stoichiometric in-depth compositionally homogeneous films with the peak values of nanohardness 88 GPa and Young's modulus 517 GPa at the penetration depth of 26 nm and, respectively, 35 GPa and 275 GPa at 200 nm depth in 2 mu m thick film (Grishin et al 2014 JETP Lett. 100 680). The narrow range of sufficiently short target-to-substrate distance makes impossible to coat non flat specimens. To achieve ultimate BAM films' characteristics onto curved surfaces we developed two-step sputtering process. The first thin layer is deposited as a template at low RF power that facilitates a layered Frank van der Merwe mode growth of smooth film occurs. The next layer is grown at high RF target sputtering power. The affinity of subsequent flow of sputtered atoms to already evenly condensed template fosters the development of smooth film surface. As an example, we made BAM coating onto hemispherical 5 mm in diameter ball made from a hard tool steel and used as a head of a special gauge. Very smooth (6.6 nm RMS surface roughness) and hard AlMgB14 films fabricated onto commercial ball-shaped items enhance hardness of tool steel specimens by a factor of four.

  • 43. Grüttner, K.
    et al.
    Görgen, R.
    Schreiner, S.
    Herrera, F.
    Peñil, P.
    Medina, J.
    Villar, E.
    Palermo, G.
    Fornaciari, W.
    Brandolese, C.
    Gadioli, D.
    Vitali, E.
    Zoni, D.
    Bocchio, S.
    Ceva, L.
    Azzoni, P.
    Poncino, M.
    Vinco, S.
    Macii, E.
    Cusenza, S.
    Favaro, J.
    Valencia, R.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rosvall, Kathrin
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Moghaddami Khalilzad, Nima
    KTH, School of Information and Communication Technology (ICT).
    Quaglia, D.
    CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties2017In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 51, p. 39-55Article in journal (Refereed)
    Abstract [en]

    The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).

  • 44. Habib, A.
    et al.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Engineering and Technology (UET), Pakistan.
    Azam, M. A.
    Loo, J.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Turku, Finland.
    Frequency signatured directly printable humidity sensing tag using organic electronics2017In: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 14, no 3Article in journal (Refereed)
    Abstract [en]

    In this paper chipless RFID tag, capable of carrying 9-bit data is presented. The tag is optimized for several flexible substrates. With growing information and communication technology, sensor integration with data transmission has gained significant attention. Therefore, the tag with the same dimension is then optimized using paper substrate. For different values of permittivity, the relative humidity is observed. Hence, besides carrying information bits, the tag is capable of monitoring and sensing the humidity. The overall dimension of the tag comprising of 9 ring slot resonators is 7 mm. Due to its optimization on the paper substrate, the tag can be an ideal choice for deploying in various low-cost sensing applications.

  • 45. Habib, A.
    et al.
    Asif, R.
    Fawwad, M.
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Engineering and Technology, Pakistan.
    Loo, J.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Turku, Finland.
    Directly printable compact chipless RFID tag for humidity sensing2017In: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 14, no 10Article in journal (Refereed)
    Abstract [en]

    In this letter, 8-bit paper based printable chipless tag is presented. The tag not only justifies the green electronic concept but also it is examined for sensing functionality. The compact tag structure comprises of seven L-shaped and one I-shaped dipole structure. These conducting tracks/dipole structures are of silver nano-particle based ink having a conductivity of 1.1 × 107 S/m. Each conducting track yields one bit corresponding to one peak. The tag design is optimized and analyzed for three different flexible substrates i.e. paper, Kapton® HN, and PET. The tag has ability to identify 28 = 256 objects, by using different binary combinations. The variation in length of particular conducting strip results in a shift of peak for that specific conducting track. This shift corresponds to logic state-1. The response of the tag for paper, Kapton® HN, and PET substrates is observed in the frequency band of 2.2-6.1 GHz, 2.4-6.3 GHz, and 2.5-6.5 GHz, respectively. The tag has an attractive nature because of its easy printability and usage of low-cost, flexible substrates. The tag can be deployed in various low-cost sensing applications.

  • 46. Habib, Ayesha
    et al.
    Ansar, Sohaira
    Akram, Adeel
    Azam, Muhammad Awais
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Engineering and Technology, Pakistan.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. University of Turku, Finland.
    Directly Printable Organic ASK Based Chipless RFID Tag for IoT Applications2017In: Radioengineering, ISSN 1210-2512, E-ISSN 1805-9600, Vol. 26, no 2, p. 453-460Article in journal (Refereed)
    Abstract [en]

    A chipless RFID tag with unique ASK encoding technique is presented in this paper. The coding efficiency is enhanced regarding tag capacity. The amplitude variations of the backscattered RFID signal is used for encoding data instead of OOK Strips of different widths are used to have amplitude variations. The ASK technique is applied using three different substrates of Kapton (R) HN, PET, and paper. To incorporate ASK technique, dual polarized rhombic shaped resonators are designed. These tags operate in the frequency range of 3.1-10.6 GHz with size of 70 x 42 mm(2). The presented tags are flexible and offer easy printability. The paper-based decomposable organic tag appears as an ultra low-cost solution for wide scale tracking. This feature enables them to secure a prominent position in the emerging fields of IoT and green electronics.

  • 47. Haghbayan, M. -H
    et al.
    Rahmani, A. M.
    Miele, A.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Online software-based self-testing in the dark silicon era2017In: The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era, Springer, 2017, p. 259-287Chapter in book (Refereed)
    Abstract [en]

    Aggressive technology scaling and intensive computations have caused acceleration in the aging and wear-out process of digital systems, hence leading to an increased occurrence of premature permanent faults. Online testing techniques are becoming a necessity in current and near future digital systems. However, state-of-the-art techniques are not aware of the other digital systems’ power/performance requirements that exist in modern multi-/many-core systems. This chapter presents an approach for power-aware non-intrusive online testing in many-core systems. The approach aims at scheduling at runtime Software-Based Self-Test (SBST) routines on the various cores to exploit their idle periods in order to benefit the potentially available power budget and minimize the performance degradation. Furthermore, a criticality metric is used to identify and rank cores that need testing at a time and power and reliability issues related to the testing at different voltage and frequency levels are taken into account. Experimental results show that the proposed approach can (1) efficiently perform cores’ testing, within less than 1?% penalty on system throughput and by dedicating only 2?% of the actual consumed power, (2) adapt to the current stress level of the cores by using the utilization metric, and (3) cover all the voltage and frequency levels during the various tests.

  • 48. Haghbayan, Mohammad-Hashem
    et al.
    Rahmani, Amir M.
    Liljeberg, Pasi
    Jantsch, Axel
    Miele, Antonio
    Bolchini, Cristiana
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Can Dark Silicon Be Exploited to Prolong System Lifetime?2017In: IEEE design & test, ISSN 2168-2356, E-ISSN 2168-2364, Vol. 34, no 2, p. 51-59Article in journal (Refereed)
  • 49.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT). KTH University.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT).
    Shakir, Muhammad
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    High Temperature Bipolar Master-Slave Comparator and Frequency Divider in 4H-SiC Technology2017In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 897, p. 681-684Article in journal (Refereed)
    Abstract [en]

    This paper demonstrates a fully integrated master-slave emitter-coupled logic (ECL)comparator and a frequency divider implemented in 4H-SiC bipolar technology. The comparator consists of two latch stages, two level shifters and an output buffer stage. The circuits have been tested up to 500 °C. The single ended output swing of the comparator is -7.73 V at 25 °C and-7.63 V at 500 °C with a -15 V supply voltage. The comparator consumes 585 mW at 25 °C. The frequency divider consisting of two latches shows a relatively constant output voltage swing over the wide temperature range. The output voltage swing is 7.62 V at 25 °C and 7.32 V at 500 °C.

  • 50.
    Hemani, Ahmed
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Farahini, Nasim
    Jafri, Syed
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Sohofi, Hassan
    KTH, School of Information and Communication Technology (ICT).
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT).
    Paul, K.
    The silago solution: Architecture and design methods for a heterogeneous dark silicon aware coarse grain reconfigurable fabric2017In: The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era, Springer, 2017, p. 47-94Chapter in book (Refereed)
    Abstract [en]

    The dark silicon constraint will restrict the VLSI designers to utilize an increasingly smaller percentage of transistors as we progress deeper into nano-scale regime because of the power delivery and thermal dissipation limits. The best way to deal with the dark silicon constraint is to use the transistors that can be turned on as efficiently as possible. Inspired by this rationale, the VLSI design community has adopted customization as the principal means to address the dark silicon constraint. Two categories of customization, often in tandem have been adopted by the community. The first is the processors that are heterogeneous in functionality and/or have ability to more efficiently match varying functionalities and runtime load. The second category of customization is based on the fact that hardware implementations often offer 2–6 orders more efficiency compared to software. For this reason, designers isolate the power and performance critical functionality and map them to custom hardware implementations called accelerators. Both these categories of customizations are partial in being compute centric and still implement the bulk of functionality in the inefficient software style. In this chapter, we propose a contrarian approach: implement the bulk of functionality in hardware style and only retain control intensive and flexibility critical functionality in small simple processors that we call flexilators. We propose using a micro-architecture level coarse grain reconfigurable fabric as the alternative to the Boolean level standard cells and LUTs of the FPGAs as the basis for dynamically reconfigurable hardware implementation. This coarse grain reconfigurable fabric allows dynamic creation of arbitrarily wide and deep datapath with their hierarchical control that can be coupled with a cluster of storage resources to create private execution partitions that host individual applications. Multiple such partitions can be created that can operate at different voltage frequency operating points. Unused resources can be put into a range of low power modes. This CGRA fabric allows not just compute centric customization but also interconnect, control, storage and access to storage can be customized. The customization is not only possible at compile/build time but also at runtime to match the available resources and runtime load conditions. This complete, micro-architecture level hardware centric customization overcomes the limitations of partial compute centric customization offered by the state-of-the-art accelerator-rich heterogeneous multi-processor implementation style by extracting more functionality and performance from the limited number of transistors that can be turned on. Besides offering complete and more effective customization and a hardware centric implementation style, we also propose a methodology that dramatically reduces the cost of customization. This methodology is based on a concept called SiLago (Silicon Large Grain Objects) method. The core idea behind the SiLago method is to use large grain micro-architecture level hardened and characterized blocks, the SiLago blocks, as the atomic physical design building blocks and a grid based structured layout scheme that enables composition of the SiLago fabric simply by abutting the blocks to produce a timing and DRC clean GDSII design. Effectively, the SiLago method raises the abstraction of the physical design to micro-architectural level from the present Boolean level standard cell and LUT based physical design. This significantly improves the efficiency and predictability of synthesis from higher levels of abstraction. In addition, it also enables true system-level synthesis that by virtue of correct-by-construction guarantee eliminates the costly functional verification step. The proposed solution allows a fully customized design with dynamic fine grain power management to be automatically generated from Simulink down to GDSII with computational and silicon efficiencies that are modestly lower than ASIC. The micro-architecture level SiLago block based design process with correct by construction guarantee is 5–6 orders more efficient and 2 orders more accurate compared to the Boolean standard cell based design flows.

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