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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    GOI fabrication for Monolithic 3D integrationIn: Article in journal (Other academic)
  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 4. Ahmad, S. A.
    et al.
    Naqvi, S. I.
    Khalid, M.
    Amin, Y.
    Loo, J.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Penta-band antenna with defected ground structure for wireless communication applications2019In: 2019 2nd International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2019, Institute of Electrical and Electronics Engineers Inc. , 2019Conference paper (Refereed)
    Abstract [en]

    This work proposes a compact, penta-band, slotted antenna with Defected Ground Structure (DGS). The proposed multiband resonator is intended for integration into microwave circuits and portable RF portable devices. The prototype with spurlines and DGS is designed on thin Rogers RT Duroid 5880 substrate having thickness 0.508 mm. The presented radiator is capable to cover the frequency bands 2.46-2.59 GHz, 2.99-3.78 GHz, 5.17-5.89 GHz, 6.86-7.36 GHz, 9.38-11 GHz. The impedance bandwidths of 5.24%, 23.68%, 12.8%, 7.24% and 16.08% is obtained for the covered frequency bands respectively. The antenna proposed in this work thus supports WLAN, WiMAX, ISM, LTE, Bluetooth, C-band and X-band applications. The radiator attains 4.2 dB peak gain. It is apparent from the radiation performance of the prototype, that it is an effective candidate for current and forthcoming multiband wireless applications.

  • 5.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zahedinejad, Mohammad
    Department of Physics, University of Gothenburg.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. Department of Physics, University of Gothenburg.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators2019In: IEEE transactions on magnetics, ISSN 0018-9464, E-ISSN 1941-0069, Vol. 55, no 10, article id 4003808Article in journal (Refereed)
    Abstract [en]

    Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

  • 6.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    Compressive-Strained Ge and Tensile-Strained SiGe on Insulator Fabrication via Wafer Bonding for Monolithic 3D IntegrationManuscript (preprint) (Other academic)
  • 7.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration2018Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

      To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

      The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

  • 8.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    Low Temperature SiGe Epitaxy Using SiH4-GeH4and Si2H6-Ge2H6 Gas PrecursorsIn: Journal of Solid State Science and TechnologyArticle in journal (Other academic)
  • 9.
    Aslam, Bilal
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Azam, Muhammad A.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Loo, Jonathan
    Middlesex Univ, Sch Engn & Informat Sci, Dept Comp Sci, London, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A high capacity tunable retransmission type frequency coded chipless radio frequency identification system2019In: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 29, no 9, article id e21855Article in journal (Refereed)
    Abstract [en]

    This article presents a 12-bit frequency coded chipless RFID system in the frequency range of 3 to 6 GHz. The system consists of a fully printable chipless tag and a pair of high-gain reader antennas. The tag also incorporates its own antennas to improve the read range. Information is encoded into frequency spectrum using a multi-resonant circuit. The circuit consists of multiple microstrip U and L-shaped open stub resonators patterned in a unique configuration. The proposed configuration aids in capturing more data in a reduced space as well as tunable frequency operation. Tag and reader antennas utilize techniques such as stepped impedance feeding line, defective partial ground plane, and stair-step patch structure to achieve wide-band impedance bandwidth in miniature size. The results of the wireless measurements in the non-anechoic environment show that the proposed system has a reading range of more than 20 cm. The presented system possesses great potential for low-cost short-range inventory tracking.

  • 10.
    Aslam, Bilal
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan..
    Kashif, Muhammad
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.;Beijing Univ Aeronaut & Astronaut, Beijing, Peoples R China..
    Azam, Muhammad Awais
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan..
    Amin, Yasar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.
    Loo, Jonathan
    Univ West London, Sch Comp & Commun Engn, Dept Comp Sci, London, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Turku, Dept Informat Technol, TUCS, Turku, Finland..
    A low profile miniature RFID tag antenna dedicated to IoT applications2019In: Electromagnetics, ISSN 0272-6343, E-ISSN 1532-527X, Vol. 39, no 6, p. 393-406Article in journal (Refereed)
    Abstract [en]

    RFID tag antennas with stable performance on the diverse electromagnetic mounting platforms are an integral part of the ubiquitous RFID systems. This research article presents a novel tag antenna design that facilitates the said objective. The proposed antenna consists of a modified H-shaped slot structure that ensures considerable robustness from the application environment through confining the surface current density within the antenna structure. The antenna offers a tunable bandwidth of 40 MHz within the microwave band of (2.4-2.5) GHz. The proposed tag antenna exhibits excellent response on metallic platforms of different sizes and thicknesses with an effective gain of almost four times of that in free space. Furthermore, the designed tag antenna performs adequately well on low-medium permittivity dielectrics (glass, paper, and plastic) and RF absorbers (water). The free space and on-metal performance of the proposed tag antenna are verified by testing a prototype realized on the FR4 substrate.

  • 11. Ayedh, H. M.
    et al.
    Bathen, M. E.
    Galeckas, A.
    Hassan, J. U.
    Bergman, J. P.
    Nipoti, R.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Svensson, B. G.
    Controlling the carbon vacancy in 4H-SiC by thermal processing2018In: ECS Transactions, Electrochemical Society Inc. , 2018, no 12, p. 91-97Conference paper (Refereed)
    Abstract [en]

    The carbon vacancy (Vc) is perhaps the most prominent point defect in silicon carbide (SiC) and it is an efficient charge carrier lifetime killer in high-purity epitaxial layers of 4H-SÌC. The Vc concentration needs to be controlled and minimized for optimum materials and device performance, and an approach based on post-growth thermal processing under C-rich ambient conditions is presented. It utilizes thermodynamic equilibration and after heat treatment at 1500 °C for 1 h, the Vc concentration is shown to be reduced by a factor-25 relative to that in as-grown state-of-the-art epi-layers. Concurrently, a considerable enhancement of the carrier lifetime occurs throughout the whole of >40 urn thick epi-layers. 

  • 12.
    Ayedh, H. M.
    et al.
    Norway.
    Nipoti, R.
    Italy.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Svensson, B. G.
    Norway.
    Kinetics modeling of the carbon vacancy thermal equilibration in 4H-SiC2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 233-236Conference paper (Refereed)
    Abstract [en]

    The carbon vacancy (VC) is a major limiting-defect of minority carrier lifetime in n-type 4H-SiC epitaxial layers and it is readily formed during high temperature processing. In this study, a kinetics model is put forward to address the thermodynamic equilibration of VC, elucidating the possible atomistic mechanisms that control the VC equilibration under C-rich conditions. Frenkel pair generation, injection of carbon interstitials (Ci’s) from the C-rich surface, followed by recombination with VC’s, and diffusion of VC’s towards the surface appear to be the major mechanisms involved. The modelling results show a close agreement with experimental deep-level transient spectroscopy (DLTS) depth profiles of VC after annealing at different temperatures.

  • 13.
    Azarov, Alexander
    et al.
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway.;Natl Ctr Nucl Res, A Soltana 7, PL-05400 Otwock, Poland..
    Aarseth, Bjorn L.
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Vines, Lasse
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Monakhov, Edouard
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Kuznetsov, Andrej
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Defect annealing kinetics in ZnO implanted with Zn substituting elements: Zn interstitials and Li redistribution2019In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 125, no 7, article id 075703Article in journal (Refereed)
    Abstract [en]

    It is known that the behavior of residual Li in ion implanted ZnO depends on the preferential localization of the implants, in particular, forming characteristic Li depleted or Li pile-up regions for Zn or O sublattice occupation of the implants due to the corresponding excess generation of Zn and O interstitials in accordance with the so-called "+1 model." However, the present study reveals that conditions for the radiation damage annealing introduce additional complexity into the interpretation of the Li redistribution trends. Specifically, four implants residing predominantly in the Zn-sublattice, but exhibiting different lattice recovery routes, were considered. Analyzing Li redistribution trends in these samples, it is clearly shown that Li behavior depends on the defect annealing kinetics which is a strong function of the implanted fluence and ion species. Thus, Li depleted and Li pile-up regions (or even combinations of the two) were observed and correlated with the defect evolution in the samples. It is discussed how the observed Li redistribution trends can be used for better understanding a thermal evolution of point defects in ZnO and, in particular, energetics and migration properties of Zn interstitials.

  • 14.
    Becker, Matthias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Chen, DeJiu
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Machine Design (Div.). KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Towards QoS-Aware Service-Oriented Communication in E/E Automotive Architectures2018In: Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society (IECON), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 4096-4101, article id 8591521Conference paper (Refereed)
    Abstract [en]

    With the raise of increasingly advanced driving assistance systems in modern cars, execution platforms that build on the principle of service-oriented architectures are being proposed. Alongside, service oriented communication is used to provide the required adaptive communication infrastructure on top of automotive Ethernet networks. A middleware is proposed that enables QoS aware service-oriented communication between software components, where the prescribed behavior of each software component is defined by Assume/Guarantee (A-G) contracts. To enable the use of COTS components, that are often not sufficiently verified for the use in automotive systems, the middleware monitors the communication behavior of components and verifies it against the components A/G contract. A violation of the allowed communication behavior then triggers adaption processes in the system while the impact on other communication is minimized. The applicability of the approach is demonstrated by a case study that utilizes a prototype implementation of the proposed approach.

  • 15.
    Becker, Matthias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Mubeen, Saad
    Mälardalen University.
    Timing Analysis Driven Design-Space Exploration of Cause-Effect Chains in Automotive Systems2018In: IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society, 2018Conference paper (Refereed)
    Abstract [en]

    Model-based development and component-based software engineering have emerged as a promising approach to deal with enormous software complexity in automotive systems. This approach supports the development of software architectures by interconnecting (and reusing) software components (SWCs) at various abstraction levels. Automotive software architectures are often modeled with chains of SWCs, also called cause-effect chains that are constrained by timing requirements. Based on the variations in activation patterns of SWCs, a single model of a cause-effect chain at a higher abstraction level can conform to several valid refined models of the chain at a lower abstraction level, which is closer to the system implementation. As a consequence, the total number of valid implementation-level models generated by the existing techniques increases exponentially, thereby significantly increasing the runtime of the timing analysis engines and liming the scalability of the existing techniques. This paper computes an upper bound on the activation pattern combinations that may result from a system of cause-effect chains in a given high-level model of the software architecture. An efficient algorithm is presented that traverses only a reduced number of possible combinations of the cause-effect chains, resulting in the timing analysis of a significantly lower number of implementation-level models of the software architecture. A proof of concept is provided by conducting a case study that shows significant reduction in the runtime of timing analysis engines, i.e., the timing behavior of the considered system is verified by performing the timing analysis of only 27% of all possible combinations of the cause-effect chains.

  • 16. Ben Dhaou, I.
    et al.
    Kondoro, Aron
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. University of Dar es Salaam, Tanzania.
    Kelati, Amleset
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. University of Turku, Finland.
    Rwegasira, Diana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. University of Turku, Finland.
    Naiman, S.
    Mvungi, N. H.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Communication and security technologies for smart grid2018In: Fog Computing: Breakthroughs in Research and Practice, IGI Global , 2018, p. 305-331Chapter in book (Other academic)
    Abstract [en]

    The smart grid is a new paradigm that aims to modernize the legacy power grid. It is based on the integration of ICT technologies, embedded system, sensors, renewable energy and advanced algorithms for management and optimization. The smart grid is a system of systems in which communication technology plays a vital role. Safe operations of the smart grid need a careful design of the communication protocols, cryptographic schemes, and computing technology. In this article, the authors describe current communication technologies, recently proposed algorithms, protocols, and architectures for securing smart grid communication network. They analyzed in a unifying approach the three principles pillars of smart-gird: Sensors, communication technologies, and security. Finally, the authors elaborate open issues in the smart-grid communication network.

  • 17.
    Chaourani, Panagiotis
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Sequential 3D Integration - Design Methodologies and Circuit Techniques2019Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.

    As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.

    The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.

    To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.

    Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.

  • 18.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines2019In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed)
    Abstract [en]

    Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

  • 19.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Stathis, Dimitrios
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper (Refereed)
    Abstract [en]

    The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

  • 20. Charif, Amir
    et al.
    Coelho, Alexandre
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. KTH.
    Bagherzadeh, Nader
    Zergainoh, Nacer-Eddine
    First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip2018In: IEEE transactions on computer, ISSN 0018-9340, Vol. 67, no 10, p. 1430-1444Article in journal (Refereed)
    Abstract [en]

    3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3DNetwork-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connectedNoCs, in which only a few vertical TSV links are available, have been gaining relevance. To reliably route packets under suchconditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected3D-NoCs named First-Last. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the Eastand North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layersis available anywhere in the network. An improved version of our algorithm, named Enhanced-First-Last is also introduced and shownto dramatically improve performance under low TSV availability while still using less virtual channels than state-of-the-art algorithms. Acomprehensive evaluation of the cost and performance of our algorithms is performed to demonstrate their merits with respects toexisting solutions.

  • 21.
    Chen, DeJiu
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Embedded Control Systems. KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Machine Design (Div.). KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Östberg, Kenneth
    RISE - Research Institutes of Sweden.
    Becker, Matthias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Sivencrona, Håkan
    Zenuity AB.
    Warg, Fredrik
    RISE - Research Institutes of Sweden.
    Design of a Knowledge-Base Strategy for Capability-Aware Treatment of Uncertainties of Automated Driving Systems2018In: Computer Safety, Reliability, and Security. / [ed] Gallina B., Skavhaug A., Schoitsch E., Bitsch F., Cham, 2018, Vol. 11094Conference paper (Refereed)
    Abstract [en]

    Automated Driving Systems (ADS) represent a key technological advancement in the area of Cyber-physical systems (CPS) and Embedded Control Systems (ECS) with the aim of promoting traffic safety and environmental sustainability. The operation of ADS however exhibits several uncertainties that if improperly treated in development and operation would lead to safety and performance related problems. This paper presents the design of a knowledge-base (KB) strategy for a systematic treatment of such uncertainties and their system-wide implications on design-space and state-space. In the context of this approach, we use the term Knowledge-Base (KB) to refer to the model that stipulates the fundamental facts of a CPS in regard to the overall system operational states, action sequences, as well as the related costs or constraint factors. The model constitutes a formal basis for describing, communicating and inferring particular operational truths as well as the belief and knowledge representing the awareness or comprehension of such truths. For the reasoning of ADS behaviors and safety risks, each system operational state is explicitly formulated as a conjunction of environmental state and some collective states showing the ADS capabilities for perception, control and actuations. Uncertainty Models (UM) are associated as attributes to such state definitions for describing and quantifying the corresponding belief or knowledge status due to the presences of evidences about system performance and deficiencies, etc. On a broader perspective, the approach is part of our research on bridging the gaps among intelligent functions, system capability and dependability for mission-&safety-critical CPS, through a combination of development- and run-time measures.

  • 22. Chen, Kun-Chih (Jimmy)
    et al.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Wang, Ting-Yi
    Yang, Yuch-Chi
    NoC-based DNN Accelerator: A Future Design Paradigm2019Conference paper (Refereed)
    Abstract [en]

    Deep Neural Networks (DNN) have shown significant advantagesin many domains such as pattern recognition, prediction, and controloptimization. The edge computing demand in the Internet-of-Things era has motivated many kinds of computing platforms toaccelerate the DNN operations. The most common platforms areCPU, GPU, ASIC, and FPGA. However, these platforms suffer fromlow performance (i.e., CPU and GPU), large power consumption(i.e., CPU, GPU, ASIC, and FPGA), or low computational flexibilityat runtime (i.e., FPGA and ASIC). In this paper, we suggest theNoC-based DNN platform as a new accelerator design paradigm.The NoC-based designs can reduce the off-chip memory accessesthrough a flexible interconnect that facilitates data exchange betweenprocessing elements on the chip. We first comprehensivelyinvestigate conventional platforms and methodologies used in DNNcomputing. Then we study and analyze different design parametersto implement the NoC-based DNN accelerator. The presentedaccelerator is based on mesh topology, neuron clustering, randommapping, and XY-routing. The experimental results on LeNet, MobileNet,and VGG-16 models show the benefits of the NoC-basedDNN accelerator in reducing off-chip memory accesses and improvingruntime computational flexibility.

  • 23.
    Chen, Qinyu
    et al.
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Fu, Yuxiang
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Cheng, Kaifeng
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Song, Wenqing
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Li, Li
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing, Jiangsu, Peoples R China..
    Zhang, Chuan
    Southeast Univ, Lab Efficient Architectures Digital Commun & Sign, Nanjing, Jiangsu, Peoples R China.;Southeast Univ, Natl Mobile Commun Res Lab, Nanjing, Jiangsu, Peoples R China..
    Smilodon: An Efficient Accelerator for Low Bit-Width CNNs with Task Partitioning2019In: 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2019Conference paper (Refereed)
    Abstract [en]

    Convolutional Neural Networks (CNNs) have been widely applied in various fields such as image and video recognition, recommender systems, and natural language processing. However, the massive size and intensive computation loads prevent its feasible deployment in practice, especially on the embedded systems. As a highly competitive candidate, low bit-width CNNs are proposed to enable efficient implementation. In this paper, we propose Smilodon, a scalable, efficient accelerator for low bit-width CNNs based on a parallel streaming architecture, optimized with a task partitioning strategy. We also present the 3D systolic-like computing arrays fitting for convolutional layers. Our design is implemented on Zynq XC7ZO20 FPGA, which can satisfy the needs of real-time with a frame rate of 1, 622 FPS throughput, while consuming 2.1 Watt. To the best of our knowledge, our accelerator is superior to the state-of-the-art works in the tradeoff among throughput, power efficiency, and area efficiency.

  • 24.
    Chen, Qinyu
    et al.
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    Fu, Yuxiang
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    Song, Wenqing
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    Cheng, Kaifeng
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zhang, Chuan
    Southeast Univ, Natl Mobile Commun Res Lab, Nanjing 210096, Jiangsu, Peoples R China..
    Li, Li
    Nanjing Univ, Sch Elect Sci & Engn, Nanjing 210093, Jiangsu, Peoples R China..
    An Efficient Streaming Accelerator for Low Bit-Width Convolutional Neural Networks2019In: ELECTRONICS, ISSN 2079-9292, Vol. 8, no 4, article id 371Article in journal (Refereed)
    Abstract [en]

    Convolutional Neural Networks (CNNs) have been widely applied in various fields, such as image recognition, speech processing, as well as in many big-data analysis tasks. However, their large size and intensive computation hinder their deployment in hardware, especially on the embedded systems with stringent latency, power, and area requirements. To address this issue, low bit-width CNNs are proposed as a highly competitive candidate. In this paper, we propose an efficient, scalable accelerator for low bit-width CNNs based on a parallel streaming architecture. With a novel coarse grain task partitioning (CGTP) strategy, the proposed accelerator with heterogeneous computing units, supporting multi-pattern dataflows, can nearly double the throughput for various CNN models on average. Besides, a hardware-friendly algorithm is proposed to simplify the activation and quantification process, which can reduce the power dissipation and area overhead. Based on the optimized algorithm, an efficient reconfigurable three-stage activation-quantification-pooling (AQP) unit with the low power staged blocking strategy is developed, which can process activation, quantification, and max-pooling operations simultaneously. Moreover, an interleaving memory scheduling scheme is proposed to well support the streaming architecture. The accelerator is implemented with TSMC 40 nm technology with a core size of . It can achieve TOPS/W energy efficiency and area efficiency at 100.1mW, which makes it a promising design for the embedded devices.

  • 25.
    Chen, Xiaowen
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Efficient Memory Access and Synchronization in NoC-based Many-core Processors2019Doctoral thesis, monograph (Other academic)
    Abstract [en]

    In NoC-based many-core processors, memory subsystem and synchronization mechanism are always the two important design aspects, since mining parallelism and pursuing higher performance require not only optimized memory management but also efficient synchronization mechanism. Therefore, we are motivated to research on efficient memory access and synchronization in three topics, namely, efficient on-chip memory organization, fair shared memory access, and efficient many-core synchronization.

    One major way of optimizing the memory performance is constructing a suitable and efficient memory organization. A distributed memory organization is more suitable to NoC-based many-core processors, since it features good scalability. We envision that it is essential to support Distributed Shared Memory (DSM) because of the huge amount of legacy code and easy programming. Therefore, we first adopt the microcoded approach to address DSM issues, aiming for hardware performance but maintaining the flexibility of programs. Second, we further optimize the DSM performance by reducing the virtual-to-physical address translation overhead. In addition to the general-purpose memory organization such as DSM, there exists special-purpose memory organization to optimize the performance of application-specific memory access. We choose Fast Fourier Transform (FFT) as the target application, and propose a multi-bank data memory specialized for FFT computation.

    In 3D NoC-based many-core processors, because processor cores and memories reside in different locations (center, corner, edge, etc.) of different layers, memory accesses behave differently due to their different communication distances. As the network size increases, the communication distance difference of memory accesses becomes larger, resulting in unfair memory access performance among different processor cores. This unfair memory access phenomenon may lead to high latencies of some memory accesses, thus negatively affecting the overall system performance. Therefore, we are motivated to study on-chip memory and DRAM access fairness in 3D NoC-based many-core processors through narrowing the round-trip latency difference of memory accesses as well as reducing the maximum memory access latency.

    Barrier synchronization is used to synchronize the execution of parallel processor cores. Conventional barrier synchronization approaches such as master-slave, all-to-all, tree-based, and butterfly are algorithm oriented. As many processor cores are networked on a single chip, contended synchronization requests may cause large performance penalty. Motivated by this, different from the algorithm-based approaches, we choose another direction (i.e., exploiting efficient communication) to address the barrier synchronization problem. We propose cooperative communication as a means and combine it with the master-slave algorithm and the all-to-all algorithm to achieve efficient many-core barrier synchronization. Besides, a multi-FPGA implementation case study of fast many-core barrier synchronization is conducted.

  • 26.
    Chen, Xiaowen
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS). Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China.
    Lei, Yuanwu
    Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Chen, Shuming
    Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China..
    A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition2018In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 26, no 10, p. 1953-1966Article in journal (Refereed)
    Abstract [en]

    Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different. Therefore, this paper proposes a variable-size FFT hardware accelerator, which fully supports the IEEE-754 single-precision floating-point standard and the FFT calculation with a wide size range from 2 to 220 points. First, a parallel Cooley-Tukey FFT algorithm based on matrix transposition (MT) is proposed, which can efficiently divide a large size FFT into several small size FFTs that can be executed in parallel. Second, guided by this algorithm, the FFT hardware accelerator is designed, and several FFT performance optimization techniques such as hybrid twiddle factor generation, multibank data memory, block MT, and token-based task scheduling are proposed. Third, its VLSI implementation is detailed, showing that it can work at 1 GHz with the area of 2.4 mm(2) and the power consumption of 91.3 mW at 25 degrees C, 0.9 V. Finally, several experiments are carried out to evaluate the proposal's performance in terms of FFT execution time, resource utilization, and power consumption. Comparative experiments show that our FFT hardware accelerator achieves at most 18.89x speedups in comparison to two software-only solutions and two hardware-dedicated solutions.

  • 27.
    Chen, Yancang
    et al.
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Xie, Lunguo
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Li, Jinwen
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Shi, Zhu
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Zhang, Minxuan
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Chen, Xiaowen
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    A Trace-driven Hardware-level Simulator for Design and Verification of Network-on-Chips2010In: 2011 INTERNATIONAL CONFERENCE ON COMPUTERS, COMMUNICATIONS, CONTROL AND AUTOMATION (CCCA 2011), VOL II / [ed] Thaung, K S, IEEE , 2010, p. 32-35Conference paper (Refereed)
    Abstract [en]

    Traditional communications of general-purpose multi-core processor and application-specific System-on-Chip face challenges in terms of scalability and complexity. Network-on-Chip (NoC) has been the most promising solution for the communications of multi-core and many-core chips. In this paper, we present a trace-driven hardware-level simulator (noted HS) based on SystemVerilog for the design and verification of NoCs. Different from the state-of-the-art NoC simulators, the HS owns three important characteristics in addition to the capability of creating simulation and synthesizable NoC descriptions: 1) hardware-level simulation can be done, which means more implementation details of hardware than flit-level simulation; 2) router debugging and verification can be done at RTL by inserting assertions and coverage; 3) trace-based application simulations can be done besides synthetic workloads. A 4 X 4 2D mesh NoC with output virtual-channel routers verifies the capability of our HS.

  • 28.
    Chen, Zhe
    et al.
    Univ Elect Sci & Technol China, Sch Informat & Commun Engn, Chengdu 611731, Sichuan, Peoples R China..
    Guo, Shize
    Univ Elect Sci & Technol China, Sch Informat & Commun Engn, Chengdu 611731, Sichuan, Peoples R China..
    Wang, Jian
    Univ Elect Sci & Technol China, Sch Informat & Commun Engn, Chengdu 611731, Sichuan, Peoples R China..
    Li, Yubai
    Univ Elect Sci & Technol China, Sch Informat & Commun Engn, Chengdu 611731, Sichuan, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Toward FPGA Security in IoT: A New Detection Technique for Hardware Trojans2019In: IEEE Internet of Things Journal, ISSN 2327-4662, Vol. 6, no 4, p. 7061-7068Article in journal (Refereed)
    Abstract [en]

    Nowadays, field programmable gate array (FPGA) has been widely used in Internet of Things (IoT) since it can provide flexible and scalable solutions to various IoT requirements. Meanwhile, hardware Trojan (HT), which may lead to undesired chip function or leak sensitive information, has become a great challenge for FPGA security. Therefore, distinguishing the Trojan-infected FPGAs is quite crucial for reinforcing the security of IoT. To achieve this goal, we propose a clock-tree-concerned technique to detect the HTs on FPGA. First, we present an experimental framework which helps us to collect the electromagnetic (EM) radiation emitted by FPGA clock tree. Then, we propose a Trojan identifying approach which extracts the mathematical feature of obtained EM traces, i.e., 2-D principal component analysis (2DPCA) in this paper, and automatically isolates the Trojan-infected FPGAs from the Trojan-free ones by using a BP neural network. Finally, we perform extensive experiments to evaluate the effectiveness of our method. The results reveal that our approach is valid in detecting HTs on FPGA. Specifically, for the trust-hub benchmarks, we can find out the FPGA with always on Trojans (100% detection rate) while identifying the triggered Trojans with high probability (by up to 92%). In addition, we give a thorough discussion on how the experimental setup, such as probe step size, scanning area, and chip ambient temperature, affects the Trojan detection rate.

  • 29. Choopani, S.
    et al.
    Samavat, F.
    Kolobova, E. N.
    Grishin, Alexander M.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Ferromagnetic resonance and magnetic anisotropy in biocompatible Y3Fe5O12@Na0.5K0.5NbO3 core-shell nanofibers2019In: Ceramics International, ISSN 0272-8842, E-ISSN 1873-3956Article in journal (Refereed)
    Abstract [en]

    Y3Fe5O12@Na0.5K0.5NbO3 (YIG@NKN) core-shell nanofibers were synthesized by the coaxial electrospinning technique. For comparison, samples of YIG and NKN nanofibers were prepared. Scanning Electron Microscopy (SEM) and 3D laser-scanning confocal microscopy (TDLM) of YIG@NKN nanofibers revealed long uniform size distributed fibers with the average diameter of 100–150 nm. X-Ray diffraction (XRD) examination shows the existence of the distinct peaks of orthorhombic NKN and cubic YIG. Magnetic force microscopy (MFM) of individual YIG@NKN nanofiber demonstrates a magnetic core that is extended in one half of the diameter of the fiber. These nanofibers show obvious Ferromagnetic resonance (FMR) with resonance near 2 KOe similar to YIG fibers but in such a way that it starts to increase linearly with applying magnetic field from zero up to near resonance field. Also they show a soft magnetic behavior with saturation magnetization of 10 emu/gr. Furthermore, we propose a model to explain line shape of randomly oriented fibers and extract all the magnetic anisotropy parameters from FMR data. The results rely the shape anisotropy as dominant effect, however the dipolar field among fibers should be considered. The highest degree of asymmetry observed in the case of core-shell fibers in hard direction that it can be originated from magneto electric effects. By taking into account the observed FMR, the ability of adequate control of microwave absorption by applying magnetic field and biocompatibility, the synthesized core-shell nanofibers are the most promising candidate for clinical application such as microwave cancer thermotherapy and adjustable microwave absorbers.

  • 30.
    Chung, Sunjae
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics. Department of Physics, University of Gothenburg.
    Jiang, Sheng
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Eklund, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Iacocca, Ezio
    Department of Applied Mathematics, University of Colorado.
    Le, Quang Tuan
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Mazraati, Hamid
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Mohseni, Seyed Majid
    Department of Physics, Shahid Beheshti University, Tehran 19839, Iran.
    Sani, Sohrab Redjai
    Department of Physics and Astronomy, Uppsala University,.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Effect of canted magnetic field on magnetic droplet nucleation boundariesManuscript (preprint) (Other academic)
    Abstract [en]

    The influence on magnetic droplet nucleation boundaries by canted magnetic elds are investigated and reported. The nucleation boundary condition, In = αAH + BH + C, is determined at different canted angles (0°< θH<20°) using magnetoresistance (MR) and microwave measurements in nanocontact spintorque oscillators (NC-STOs). As θH increased, the nucleation boundary shifts gradually towards higher In and H. The coefficient B of the nucleation boundary equation also nearly doubled as θH increases. On theother hand, the coefficient αA remained constant for all values of θH. These observations can be explained by considering the drift instability of magnetic droplets and the different tilt behaviour of the Co fixed layer induced by different θH.

  • 31.
    de Medeiros, Jose. E. G.
    et al.
    Univ Brasilia, Dept Elect Engn, Brasilia, DF, Brazil..
    Ungureanu, George
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Sander, Ingo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    An Algebra for Modeling Continuous Time Systems2018In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE, 2018, p. 861-864Conference paper (Refereed)
    Abstract [en]

    Advancements on analog integrated design have led to new possibilities for complex systems combining both continuous and discrete time modules on a signal processing chain. However, this also increases the complexity any design flow needs to address in order to describe a synergy between the two domains, as the interactions between them should be better understood. We believe that a common language for describing continuous and discrete time computations is beneficial for such a goal and a step towards it is to gain insight and describe more fundamental building blocks. In this work we present an algebra based on the General Purpose Analog Computer, a theoretical model of computation recently updated as a continuous time equivalent of the Turing Machine.

  • 32.
    Delekta, Szymon Sollami
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Adolfsson, Karin H.
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Fibre- and Polymer Technology.
    Benyahia Erdal, Nejla
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Fibre- and Polymer Technology.
    Hakkarainen, Minna
    KTH, School of Engineering Sciences in Chemistry, Biotechnology and Health (CBH), Fibre- and Polymer Technology, Polymer Technology.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Li, Jiantong
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Fully inkjet printed ultrathin microsupercapacitors based on graphene electrodes and a nano-graphene oxide electrolyte2019In: Nanoscale, ISSN 2040-3364, E-ISSN 2040-3372, Vol. 11, no 21, p. 10172-10177Article in journal (Refereed)
    Abstract [en]

    The advance of miniaturized and low-power electronics has a striking impact on the development of energy storage devices with constantly tougher constraints in terms of form factor and performance. Microsupercapacitors (MSCs) are considered a potential solution to this problem, thanks to their compact device structure. Great efforts have been made to maximize their performance with new materials like graphene and to minimize their production cost with scalable fabrication processes. In this regard, we developed a full inkjet printing process for the production of all-graphene microsupercapacitors with electrodes based on electrochemically exfoliated graphene and an ultrathin solid-state electrolyte based on nano-graphene oxide. The devices exploit the high ionic conductivity of nano-graphene oxide coupled with the high electrical conductivity of graphene films, yielding areal capacitances of up to 313 mu F cm-2 at 5 mV s-1 and high power densities of up to 4 mW cm-3 with an overall device thickness of only 1 mu m.

  • 33.
    Delekta, Szymon Sollami
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Li, Jiantong
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wet Transfer of Inkjet Printed Graphene for Microsupercapacitors on Arbitrary Substrates2019In: ACS Applied Energy Materials, ISSN 2574-0962, Vol. 2, no 1, p. 158-163Article in journal (Refereed)
    Abstract [en]

    Significant research interest is being devoted to exploiting the properties of graphene but the difficult integration on various substrates limits its use. In this regard, we developed a transfer technique that allows the direct deposition of inkjet printed graphene devices on arbitrary substrates, even 3D objects and living plants. With this technique, we fabricated micro-supercapacitors, which exhibited good adhesion on almost all substrates and no performance degradation induced by the process. Specifically, the microsupercapacitor on an orchid leaf showed an areal capacitance as high as 441 mu F cm(-2) and a volumetric capacitance of 1.16 F cm(-3). This technique can boost the use of graphene in key technological applications, such as self powered epidermal electronics and environmental monitoring systems.

  • 34. Dhaou, I. B.
    et al.
    Skhiri, H.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Study and implementation of a secure random number generator for DSRC devices2018In: 2017 9th IEEE-GCC Conference and Exhibition, GCCCE 2017, Institute of Electrical and Electronics Engineers Inc. , 2018Conference paper (Refereed)
    Abstract [en]

    This work presents an algorithm to select a low-cost modulus for the implementation of Blum Blum Shub pseudorandom number generator in an FPGA device. Additionally, it elaborates a low-latency architecture for the BBS algorithm suitable for the security service of the IEEE 1609.2 standard. The architecture uses diminished-1 arithmetic and is log2($N$) faster than previously reported implementation using Montgomery multiplier. The architecture is able to implement 224-bit and 256-bit BBS sequences. Synthesis results show that the latencies for the 224-bit and 256-bit BBS are, respectively, 1.12μs and 1.28μs.

  • 35.
    Du, Gaoming
    et al.
    Hefei Univ Technol, 193 Tunxi Rd, Hefei, Anhui, Peoples R China..
    Liu, Guanyu
    Hefei Univ Technol, 193 Tunxi Rd, Hefei, Anhui, Peoples R China..
    Li, Zhenmin
    Hefei Univ Technol, 193 Tunxi Rd, Hefei, Anhui, Peoples R China..
    Cao, Yifan
    Hefei Univ Technol, 193 Tunxi Rd, Hefei, Anhui, Peoples R China..
    Zhang, Duoli
    Hefei Univ Technol, 193 Tunxi Rd, Hefei, Anhui, Peoples R China..
    Ouyang, Yiming
    Hefei Univ Technol, 193 Tunxi Rd, Hefei, Anhui, Peoples R China..
    Gao, Minglun
    Hefei Univ Technol, 193 Tunxi Rd, Hefei, Anhui, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    SSS: Self-aware System-on-chip Using a Static-dynamic Hybrid Method2019In: ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS, ISSN 1550-4832, Vol. 15, no 3, article id 28Article in journal (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) has become the de facto communication standard for multi-core or many-core System-on-Chip (SoC) due to its scalability and flexibility. However, an important factor in NoC design is temperature, which affects the overall performance of SoC-decreasing circuit frequency, increasing energy consumption, and even shortening chip lifetime. In this article, we propose SSS, a self-aware SoC using a static-dynamic hybrid method that combines dynamic mapping and static mapping to reduce the hotspot temperature for NoC-based SoCs. First, we propose monitoring and thermal modeling for self-state sensoring. Then, in static mapping stage, we calculate the optimal mapping solutions under different temperature modes using the discrete firefly algorithm to help self-decisionmaking. Finally, in dynamic mapping stage, we achieve dynamic mapping through configuring NoC and SoC sentient units for self-optimizing. Experimental results show that SSS has substantially reduced the peak temperature by up to 37.52%. The FPGA prototype proves the effectiveness and smartness of SSS in reducing hotspot temperature.

  • 36.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    A reconfigurable arbiter PUF with 4 x 4 switch blocks2018In: Proceedings of The International Symposium on Multiple-Valued Logic, IEEE Computer Society , 2018, p. 31-37Conference paper (Refereed)
    Abstract [en]

    Physical Unclonable Functions (PUFs) exploit manufacturing process variation to create responses that are unique to individual integrated circuits (ICs). Typically responses of a PUF cannot be modified once the PUF is fabricated. In applications which use PUFs as a long-Term secret key, it would be useful to have a simple mechanism for reconfiguring the PUF in order to update the key periodically. In this paper, we present a new type of arbiter PUFs which use 4 x 4 switch blocks instead of the conventional 2 x 2 ones. Each 4 x 4 switch block can be reconfigured in many different ways during the PUF's lifetime, making possible regular key updates. © 2018 IEEE.

  • 37.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Naslund, Mats
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Selander, Göran
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Lindqvist, Fredrik
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Message authentication based on cryptographically secure CRC without polynomial irreducibility test2018In: Cryptography and Communications, ISSN 1936-2447, E-ISSN 1936-2455, Vol. 10, no 2, p. 383-399Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a message authentication scheme based on cryptographically secure cyclic redundancy check (CRC). Similarly to previously proposed cryptographically secure CRCs, the presented one detects both random and malicious errors without increasing bandwidth. The main difference from previous approaches is that we use random instead of irreducible generator polynomials. This eliminates the need for irreducibility tests. We provide a detailed quantitative analysis of the achieved security as a function of message and CRC sizes. The results show that the presented scheme is particularly suitable for the authentication of short messages.

  • 38.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Näslund, Oskar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Degen, Bernhard
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Gawell, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Yu, Yang
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    CRC-PUF: A Machine Learning Attack Resistant Lightweight PUF Construction2019In: 2019 IEEE European Symposium on Security and Privacy Workshops (EuroS&PW), IEEE conference proceedings, 2019, p. 264-271-Conference paper (Refereed)
    Abstract [en]

    Adversarial machine learning is an emerging threat to security of Machine Learning (ML)-based systems. However, we can potentially use it as a weapon against ML-based attacks. In this paper, we focus on protecting Physical Unclonable Functions (PUFs) against ML-based modeling attacks. PUFs are an important cryptographic primitive for secret key generation and challenge-response authentication. However, none of the existing PUF constructions are both ML attack resistant and sufficiently lightweight to fit low-end embedded devices. We present a lightweight PUF construction, CRC-PUF, in which input challenges are de-synchronized from output responses to make a PUF model difficult to learn. The de-synchronization is done by an input transformation based on a Cyclic Redundancy Check (CRC). By changing the CRC generator polynomial for each new response, we assure that success probability of recovering the transformed

  • 39.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Selander, G.
    Näslund, Mats
    KTH.
    Lindqvist, Fredrik
    KTH.
    Lightweight message authentication for constrained devices2018In: WiSec 2018 - Proceedings of the 11th ACM Conference on Security and Privacy in Wireless and Mobile Networks, Association for Computing Machinery (ACM), 2018, p. 196-201Conference paper (Refereed)
    Abstract [en]

    Message Authentication Codes (MACs) used in today's wireless communication standards may not be able to satisfy resource limitations of simpler 5G radio types and use cases such as machine type communications. As a possible solution, we present a lightweight message authentication scheme based on the cyclic redundancy check (CRC). It has been previously shown that a CRC with an irreducible generator polynomial as the key is an -almost XOR-universal (AXU) hash function with = (m + n)/2n-1, where m is the message size and n is the CRC size. While the computation of n-bit CRCs can be efficiently implemented in hardware using linear feedback shift registers, generating random degree-n irreducible polynomials is computationally expensive for large n. We propose using a product of k irreducible polynomials whose degrees sum up to n as a generator polynomial for an n-bit CRC and show that the resulting hash functions are -AXU with = (m + n)k/2n -k. The presented message authentication scheme can be seen as providing a trade-off between security and implementation efficiency.

  • 40.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Teslenko, Maxim
    An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms2018In: Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 65-72Conference paper (Refereed)
    Abstract [en]

    The absence of short cycles is a desirable property for cryptographic algorithms that are iterated. Furthermore, as demonstrated by the cryptanalysis of A5, short cycles can be exploited to reduce the complexity of an attack. We present an algorithm which uses a SAT-based bounded model checking for finding all short cycles of a given length. The existing Boolean Decision Diagram (BDD) based algorithms for finding cycles have limited capacity due to the excessive memory requirements of BDDs. The simulation-based algorithms can be applied to larger problem instances, however, they cannot guarantee the detection of all cycles of a given length. The same holds for general-purpose SAT-based model checkers. The presented algorithm can handle cryptographic algorithms with very large state spaces, including important ciphers such as Trivium and Grain-128. We found that these ciphers contain short cycles whose existence, to our best knowledge, was previously unknown. This potentially opens new possibilities for cryptanalysis.

  • 41.
    Ebrahimi, Masoumeh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Chen, K. -CJ.
    Reshadi, M.
    NoCArc 2018 Message from the Chairs2018In: 11th International Workshop on Network on Chip Architectures, NoCArc 2018, article id 8541230Article in journal (Refereed)
  • 42.
    Ebrahimi, Masoumeh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Kelati, Amleset
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Nkonoki, Emma
    Kondoro, Aron
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rwegasira, Diana
    KTH.
    Ben Dhaou, Imed
    Taajamaa, Ville
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Creation of CERID: Challenge, Education, Research, Innovation, and Deployment in the context of smart MicroGrid2019In: IST-Africa 2019 Conference Proceedings / [ed] Paul Cunningham ; Miriam Cunningham, 2019Conference paper (Refereed)
    Abstract [en]

    The iGrid project deals with the design and implementation of a solar-powered smart microgrid to supply electric power to small rural communities. In this paper, we discuss the roadmap of the iGrid project, which forms by merging the roadmaps of KIC (knowledge and Innovation Community) and CDE (Challenge-Driven Education). We introduce and explain a five-gear chain as Challenge, Education, Research, Innovation, and Deployment, called CERID, to reach the main goals of this project. We investigate the full chain in the iGrid project, which is established between KTH Royal Institute of Technology (Sweden) and University of Dar es Salam (Tanzania). We introduce the key stakeholders and explain how CERID goals can be accomplished in higher educations and through scientific research. Challenges are discussed, some innovative ideas are introduced and deployment solutions are recommended.

  • 43.
    Ekström, Mattias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    SiC CMOS and memory devices for high-temperature integrated circuits2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    High-temperature electronics find use in extreme environments, like data logging in downhole drilling for geothermal energy production, inside of high-temperature turbines, industrial gas sensors and space electronics. The simplest systems use a sensor and a transmitter, but more advance electronic systems would additionally require a microcontroller with memory. Silicon carbide (4H-SiC) integrated circuits target high-temperature electronics, although the current integration level is low due to immature process technology and non-volatile memory has not been demonstrated. SiC CMOS would allow highly dense integrated circuits for microcontrollers and random access memory (RAM). Ferroelectric capacitors could serve as high-temperature non-volatile memory devices.

    In this work, significant efforts have been taken to develop a SiC CMOS process and ferroelectric capacitors. SiC CMOS is challenging and mostly unexplored technology. A recessed channel transistor design was investigated. Several key challenges in the SiC CMOS process was identified, leading to a polyoxide-based field oxide, a deposited gate-dielectric process, reproducible Ni-Al semi-salicide contacts to p-type SiC, and a high-temperature CMP enabled two-level TiW-based metallisation. Self-aligned cobalt silicide contacts were investigated, and was found to produce low-resistance ohmic contactsto n-type SiC. Inverters and ring oscillators that operate at 200 °C were achieved in this recessed channel SiC CMOS process. It was found that steam-treating the gate oxide interface produced both NMOS and PMOS transistors that could be used for circuits. However, the reliability suffered due to poor PMOS performance. Wafer-level statistical measurements of interface trap density was performed on NMOS transistors treated by steam, dry oxygen and nitrided by nitrous oxide. A deposition and etch process for ferroelectric capacitors, using vanadium-doped bismuth titanate as ferroelectric material, was developed. High-temperature operation was demonstrated, and several scalability challenges for the etched process was identified.

    The implication of this thesis is that while operational recessed channel SiC CMOS was demonstrated at high temperature, more promising technologies like ion implanted bulk transistors should be investigated instead, due to the numerous difficulties in optimising both NMOS and PMOS with this recessed channel design. The presented recessed channel process technology can be used to fabricate short channel length NMOS-logic. Ferroelectric capacitors is a good candidate for high-temperature non-volatile memory applications, although more work is needed in the CMOS integration.

  • 44.
    Ekström, Mattias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Ferrario, Andrea
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Investigation of a Self-Aligned Cobalt Silicide Process for Ohmic Contacts to Silicon Carbide2019In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 48, no 4, p. 2509-2516Article in journal (Refereed)
    Abstract [en]

    Previous studies showed that cobalt silicide can form ohmic contacts to p-type 6H-SiC by directly reacting cobalt with 6H-SiC. Similar results can be achieved on 4H-SiC, given the similarities between the different silicon carbide polytypes. However, previous studies using multilayer deposition of silicon/cobalt on 4H-SiC gave ohmic contacts to n-type. In this study, we investigated the cobalt silicide/4H-SiC system to answer two research questions. Can cobalt contacts be self-aligned to contact holes to 4H-SiC? Are the self-aligned contacts ohmic to n-type, p-type, both or neither? Using x-ray diffraction, it was found that a mixture of silicides (Co2Si and CoSi) was reliably formed at 800°C using rapid thermal processing. The cobalt silicide mixture becomes ohmic to epitaxially grown n-type (1×1019cm-3) if annealed at 1000°C, while it shows rectifying properties to epitaxially grown p-type (1×1019cm-3) for all tested anneal temperatures in the range 800–1000°C. The specific contact resistivity (ρC) to n-type was 4.3×10-4 Ω cm2. This work opens the possibility to investigate other self-aligned contacts to silicon carbide.

  • 45.
    Ekström, Mattias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    High-Temperature Recessed Channel SiC CMOS Inverters and Ring Oscillators2019In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 5, p. 670-673Article in journal (Refereed)
    Abstract [en]

    Digital electronics in SiC find use in high-temperature applications. The objective of this study was to fabricate SiC CMOS without using ion implantation. In this letter, we present a recessed channel CMOS process. Selective doping is achieved by etching epitaxial layers into mesas. A deposited SiO2-film, post-annealed at lowtemperature and re-oxidized in pyrogenic steam, is used as the gate oxide to produce a conformal gate oxide over the non-planar topography. PMOS, NMOS, inverters, and ring oscillators are characterized at 200 °C. The PMOS requires reduced threshold voltage in order to enable long term reliability. This result demonstrates that it is possible to fabricate SiC CMOS without ion implantation and by low-temperature processing.

  • 46.
    El-Sayed, R.
    et al.
    Karolinska Inst, Dept Lab Med, Expt Canc Med, S-14186 Stockholm, Sweden..
    Waraky, A.
    Gothenburg Univ, Dept Lab Med, Gothenburg, Sweden..
    Ezzat, K.
    Stockholm Univ, Wenner Gren Inst, Dept Mol Biosci, Stockholm, Sweden..
    Albabtain, R.
    King Saud Univ, Coll Appl Med Sci, Riyadh, Saudi Arabia..
    Elgammal, Karim
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Shityakov, S.
    Univ Hosp Wilrzburg, Dept Anesthesia & Crit Care, Wurzburg, Germany..
    Muhammed, Mamoun
    KTH.
    Hassan, M.
    Karolinska Inst, Dept Lab Med, Expt Canc Med, S-14186 Stockholm, Sweden.;Karolinska Univ Hosp Huddinge, Clin Res Ctr, Stockholm, Sweden..
    Degradation of pristine and oxidized single wall carbon nanotubes by CYP3A42019In: Biochemical and Biophysical Research Communications - BBRC, ISSN 0006-291X, E-ISSN 1090-2104, Vol. 515, no 3, p. 487-492Article in journal (Refereed)
    Abstract [en]

    Carbon nanotubes (CNTs) are a class of carbon based nanomaterials which have attracted substantial attention in recent years as they exhibit outstanding physical, mechanical and optical properties. In the last decade many studies have emerged of the underlying mechanisms behind CNT toxicity including malignant transformation, the formation of granulomas, inflammatory responses, oxidative stress, DNA damage and mutation. In the present investigation, we studied the biodegradation of single-walled carbon nanotubes (SWCNTs) by Cytochrome P450 enzymes (CYP3A4) through using Raman spectroscopy. CYP3A4 is known isozyme accountable for metabolizing various endogenous and exogenous xenobiotics. CYP3A4 is expressed dominantly in the liver and other organs including the lungs. Our results suggest that CYP3A4 has a higher affinity for p-SWNTs compared to c-SWNTs. HEK293 cellular viability was not compromised when incubated with SWNT. However, CYP3A4 transfected HEK293 cell line showed no digestion of cSWNTs after incubation for 96 h. Cellular uptake of c-SWNTs was observed by electron microscopy and localization of c-SWNTs was confirmed in endosomal vesicles and in the cytoplasm. This is the first study CYP3A4 degrading both p-SWNTs and c-SWNTs in an in vitro setup. Interestingly, our results show that CYP3A4 is more proficient in degrading p-SWNTs than c-SWNTs. We also employed computational modeling and docking assessments to develop a further understanding of the molecular interaction mechanism. 

  • 47. Fakih, M.
    et al.
    Grüttner, K.
    Schreiner, S.
    Seyyedi, R.
    Azkarate-Askasua, M.
    Onaindia, P.
    Poggi, T.
    Romero, N. G.
    Gonzalez, E. Q.
    Sundström, T.
    Frasquet, S. P.
    Balbastre, P.
    Mohammadat, T.
    Öberg, Johnny
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Bebawy, Y.
    Obermaisser, R.
    Maleki, A.
    Lenz, A.
    Graham, D.
    Experimental evaluation of SAFEPOWER architecture for safe and power-efficient mixed-criticality systems2019In: Journal of Low Power Electronics and Applications, Vol. 9, no 1, article id 12Article in journal (Refereed)
    Abstract [en]

    With the ever-increasing industrial demand for bigger, faster and more efficient systems, a growing number of cores is integrated on a single chip. Additionally, their performance is further maximized by simultaneously executing as many processes as possible. Even in safety-critical domains like railway and avionics, multicore processors are introduced, but under strict certification regulations. As the number of cores is continuously expanding, the importance of cost-effectiveness grows. One way to increase the cost-efficiency of such a System on Chip (SoC) is to enhance the way the SoC handles its power consumption. By increasing the power efficiency, the reliability of the SoC is raised because the lifetime of the battery lengthens. Secondly, by having less energy consumed, the emitted heat is reduced in the SoC, which translates into fewer cooling devices. Though energy efficiency has been thoroughly researched, there is no application of those power-saving methods in safety-critical domains yet. The EU project SAFEPOWER (Safe and secure mixed-criticality systems with low power requirements) targets this research gap and aims to introduce certifiable methods to improve the power efficiency of mixed-criticality systems. This article provides an overview of the SAFEPOWER reference architecture for low-power mixed-criticality systems, which is the most important outcome of the project. Furthermore, the application of this reference architecture in novel railway interlocking and flight controller avionic systems was demonstrated, showing the capability to achieve power savings up to 37%, while still guaranteeing time-triggered task execution and time-triggered NoC-based communication. 

  • 48.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems.
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems.
    Wagner, Stefan
    AMO GmbH.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Lemme, Max C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. RWTH Aachen University; AMO GmbH.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems.
    Suspended Graphene Membranes with Attached Silicon Proof Masses as Piezoresistive Nanoelectromechanical Systems Accelerometers2019In: Nano letters (Print), ISSN 1530-6984, E-ISSN 1530-6992, Vol. 19, no 10, p. 6788-6799Article in journal (Refereed)
    Abstract [en]

    Graphene is an atomically thin material that features unique electrical and mechanical properties, which makes it an extremely promising material for future nanoelectromechanical systems (NEMS). Recently, basic NEMS accelerometer functionality has been demonstrated by utilizing piezoresistive graphene ribbons with suspended silicon proof masses. However, the proposed graphene ribbons have limitations regarding mechanical robustness, manufacturing yield, and the maximum measurement current that can be applied across the ribbons. Here, we report on suspended graphene membranes that are fully clamped at their circumference and have attached silicon proof masses. We demonstrate their utility as piezoresistive NEMS accelerometers, and they are found to be more robust, have longer life span and higher manufacturing yield, can withstand higher measurement currents, and are able to suspend larger silicon proof masses, as compared to the previous graphene ribbon devices. These findings are an important step toward bringing ultraminiaturized piezoresistive graphene NEMS closer toward deployment in emerging applications such as in wearable electronics, biomedical implants, and internet of things (IoT) devices.

  • 49.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Suspended graphenemembranes with attached proof masses as piezoresistive NEMS accelerometersIn: Article in journal (Refereed)
  • 50.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Rödjegård, Henrik
    Senseair AB .
    Fisher, Andreas
    Silex Microsystems AB.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Graphene beams with suspended masses as electromechanical transducers in ultra-small accelerometersIn: Article in journal (Refereed)
1234 1 - 50 of 177
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