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  • 1.
    Abdollahi, Meisam
    et al.
    Iran Univ Sci & Technol, Tehran, Iran..
    Baharloo, Mohammad
    Inst Res Fundamental Sci IPM, Tehran, Iran..
    Shokouhinia, Fateme
    Amirkabir Univ Technol, Tehran, Iran..
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    RAP-NoC: Reliability Assessment of Photonic Network-on-Chips, A simulator2021In: Proceedings of the 8th ACM international conference on nanoscale computing and communication (ACM NANOCOM 2021), Association for Computing Machinery (ACM) , 2021Conference paper (Refereed)
    Abstract [en]

    Nowadays, optical network-on-chip is accepted as a promising alternative solution for traditional electrical interconnects due to lower transmission delay and power consumption as well as considerable high data bandwidth. However, silicon photonics struggles with some particular challenges that threaten the reliability of the data transmission process.The most important challenges can be considered as temperature fluctuation, process variation, aging, crosstalk noise, and insertion loss. Although several attempts have been made to investigate the effect of these issues on the reliability of optical network-on-chip, none of them modeled the reliability of photonic network-on-chip in a system-level approach based on basic element failure rate. In this paper, an analytical model-based simulator, called Reliability Assessment of Photonic Network-on-Chips (RAP-NoC), is proposed to evaluate the reliability of different 2D optical network-on-chip architectures and data traffic. The experimental results show that, in general, Mesh topology is more reliable than Torus considering the same size. Increasing the reliability of Microring Resonator (MR) has a more significant impact on the reliability of an optical router rather than a network.

  • 2.
    Abedin, Ahmad
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Germanium layer transfer and device fabrication for monolithic 3D integration2021Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Monolithic three-dimensional (M3D) integration, it has been proposed,can overcome the limitations of further circuits’ performance improvementand functionality expansion. The emergence of the internet of things (IoT) isdriving the semiconductor industry toward the fabrication of higher-performancecircuits with diverse functionality. On the one hand, the scaling of devices isreaching critical dimensions, which makes their further downscaling techno-logically difficult and economically challenging, whereas, on the other hand,the field of electronics is no longer limited only to developing circuits thatare meant for data processing. Sensors, processors, actuators, memories, andeven power storage units need to be efficiently integrated into a single chip tomake IoT work. M3D integration through stacking different layers of deviceson each other can potentially improve circuits’ performance by shorteningthe wiring length and reducing the interconnect delay. Using multiple tiersfor device fabrication makes it possible to integrate different materials withsuperior physical properties. It offers the advantage of fabricating higher-performance devices with multiple functionalities on a single chip. However,high-quality layer transfer and processing temperature budget are the majorchallenges in M3D integration. This thesis involves an in-depth explorationof the application of germanium (Ge) in monolithic 3D integration.Ge has been recognized as one of the most promising materials that canreplace silicon (Si) as the channel material for p-type field-effect transistors(pFETs) because of its high hole mobility. Ge pFETs can be fabricated atsubstantially lower temperatures compared to Si devices which makes theformer a good candidate for M3D integration. However, the fabrication ofhigh-quality Ge-on-insulator (GOI) layers with superior thickness homogene-ity, low residual doping, and a sufficiently good interface with buried oxide(BOX) has been challenging.This thesis used low-temperature wafer bonding and etch-back techniquesto fabricate the GOI substrate for M3D applications. For this purpose, aunique stack of epitaxial layers was designed and fabricated. The layer stackcontains a Ge strain relaxed buffer (SRB) layer, a SiGe layer to be used asan etch stop, and a top Ge layer to be transferred to the handling wafer.The wafers were bonded at room temperature, and the sacrificial wafer wasremoved through multiple etching steps leaving 20 nm Ge on the insulatorwith excellent thickness homogeneity over the wafer. Ge pFET devices werefabricated on the GOI substrates and electrically characterized to evaluatethe layer quality. Finally, the epitaxial growth of the highly doped SiGeand sub-nm Si cap layers have been investigated as alternatives for improvedperformance Ge pFETs.The Ge buffer layer was developed through the two-step deposition tech-nique resulting in defect density of107cm−3and surface roughness of 0.5 nm.The fully strainedSi0.5Ge0.5film with high crystal quality was epitaxiallygrown at temperatures below 450°C. The layer was sandwiched between theGe buffer and the top 20 nm Ge layer to be used as an etch-stop in the etch- back process. A highly selective etching method was developed to remove the3μm Ge buffer and 10nm SiGe film without damaging the 20 nm transferringGe layer.The Ge pFETs were fabricated at temperatures below 600°C so that theycould be compatible with the M3D integration. The back interface of thedevices depleted atVBG= 0V, which confirmed the small density of fixedcharges at the Ge/BOX interface along with a low level of residual doping inthe Ge channel. The Ge pFETs with 70 % yield over the whole wafer showed60 % higher carrier mobility than Si reference devices.Low-temperature epitaxial growth of Si passivation layer on Ge was de-veloped in this thesis. For electrical evaluation of the passivation layer,metal-oxide-semiconductor (MOS) capacitors were fabricated and character-ized. The capacitors showed an interface trap density of3×1011eV−1cm−2,and hysteresis as low as 3 mV at Eox of 4MV/cm corresponding to oxide trapdensity of1.5×1010cm−2. The results indicate that this Si passivation layersubstantially improves the gate dielectric by reducing the subthreshold slopeof Ge devices while increasing their reliability. The in-situ doped SiGe layerwith a dopant concentration of2.5×1019cm−3and resistivity of 3.5 mΩcmwas selectively grown on Ge to improve the junction formation.The methods developed in this thesis are suitable for large-scale M3Dintegration of Ge pFET devices on the Si platform. The unique Ge layertransfer and etch-back techniques resulted in the fabrication of GOI substrateswith high thickness homogeneity, low residual doping, and sufficiently goodGe/BOX interface. The process temperatures for Ge transfer and pFETsfabrication are kept within the range of the M3D budget. Integration of theSi cap for gate dielectric formation and SiGe layers in the source/drain regionmay increase device performance and reliability

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  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Growth of epitaxial SiGe alloys as etch-stop layers in germanium-on-insulator fabricationManuscript (preprint) (Other academic)
    Abstract [en]

    In this study, the application of epitaxially grown SixGe1-x films as etch stop layers in a germanium-on-insulator substrate fabrication flow is investigated. Layers with Ge contents from 15% to 70% were epitaxially grown on Si (1 0 0) using silane and germane. It was found that the Ge content in the films is independent of the growth temperature for fixed partial pressure ratios. At low growth temperatures the activation energy is found to be 1.8 eV which points to a hydrogen desorption limited growth rate mechanism. At growth temperatures of less than 500℃, the surface roughness is <1 nm. This surface roughness does not change when the films are grown on Ge substrates. Finally, a fully strained Si0.5Ge0.5 film was grown on Ge strain relaxed buffer at 450℃. This layer demonstrates etch selectivity of >400:1 towards Ge in diluted SC-1. This result enables the integration of the Si0.5Ge0.5 film as an etch stop layer for single crystalline germanium-on-insulator substrate fabrication.

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  • 4.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH.
    GOI fabrication for Monolithic 3D integrationIn: Article in journal (Other academic)
  • 5.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, E-ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

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  • 6.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 7. Agirre, J. A.
    et al.
    Etxeberria, L.
    Barbosa, R.
    Basagiannis, S.
    Giantamidis, G.
    Bauer, T.
    Ferrari, E.
    Labayen Esnaola, M.
    Orani, V.
    Öberg, Johnny
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Pereira, D.
    Proença, J.
    Schlick, R.
    Smrčka, A.
    Tiberti, W.
    Tonetta, S.
    Bozzano, M.
    Yazici, A.
    Sangchoolie, B.
    The VALU3S ECSEL project: Verification and validation of automated systems safety and security2021In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 87, p. 104349-, article id 104349Article in journal (Refereed)
    Abstract [en]

    Manufacturers of automated systems and their components have been allocating an enormous amount of time and effort in R&D activities, which led to the availability of prototypes demonstrating new capabilities as well as the introduction of such systems to the market within different domains. Manufacturers need to make sure that the systems function in the intended way and according to specifications. This is not a trivial task as system complexity rises dramatically the more integrated and interconnected these systems become with the addition of automated functionality and features to them. This effort translates into an overhead on the V&V (verification and validation) process making it time-consuming and costly. In this paper, we present VALU3S, an ECSEL JU (joint undertaking) project that aims to evaluate the state-of-the-art V&V methods and tools, and design a multi-domain framework to create a clear structure around the components and elements needed to conduct the V&V process. The main expected benefit of the framework is to reduce time and cost needed to verify and validate automated systems with respect to safety, cyber-security, and privacy requirements. This is done through identification and classification of evaluation methods, tools, environments and concepts for V&V of automated systems with respect to the mentioned requirements. VALU3S will provide guidelines to the V&V community including engineers and researchers on how the V&V of automated systems could be improved considering the cost, time and effort of conducting V&V processes. To this end, VALU3S brings together a consortium with partners from 10 different countries, amounting to a mix of 25 industrial partners, 6 leading research institutes, and 10 universities to reach the project goal.

  • 8. Ahmad, S. A.
    et al.
    Naqvi, S. I.
    Khalid, M.
    Amin, Y.
    Loo, J.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Penta-band antenna with defected ground structure for wireless communication applications2019In: 2019 2nd International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2019, Institute of Electrical and Electronics Engineers Inc. , 2019Conference paper (Refereed)
    Abstract [en]

    This work proposes a compact, penta-band, slotted antenna with Defected Ground Structure (DGS). The proposed multiband resonator is intended for integration into microwave circuits and portable RF portable devices. The prototype with spurlines and DGS is designed on thin Rogers RT Duroid 5880 substrate having thickness 0.508 mm. The presented radiator is capable to cover the frequency bands 2.46-2.59 GHz, 2.99-3.78 GHz, 5.17-5.89 GHz, 6.86-7.36 GHz, 9.38-11 GHz. The impedance bandwidths of 5.24%, 23.68%, 12.8%, 7.24% and 16.08% is obtained for the covered frequency bands respectively. The antenna proposed in this work thus supports WLAN, WiMAX, ISM, LTE, Bluetooth, C-band and X-band applications. The radiator attains 4.2 dB peak gain. It is apparent from the radiation performance of the prototype, that it is an effective candidate for current and forthcoming multiband wireless applications.

  • 9.
    Aknesil, Can
    et al.
    KTH.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    An FPGA Implementation of 4x4 Arbiter PUF2021In: 2021 IEEE 51st international symposium on multiple-valued logic (ISMVL 2021), Institute of Electrical and Electronics Engineers (IEEE) , 2021, p. 160-165Conference paper (Refereed)
    Abstract [en]

    The need of protecting data and bitstreams increases in computation environments such as FPGA as a Service (FaaS). Physically Unclonable Functions (PUFs) have been proposed as a solution to this problem. In this paper, we present an implementation of Arbiter PUF with 4 x 4 switch blocks in Xilinx Series 7 FPGA, perform its statistical analysis, and compare it to other Arbiter PUF variants. We show that the presented implementation utilizes five times less area than 2 x 2 Arbiter PUF-based implementations. It is suitable for many real-world applications, including identification, authentication, key provisioning, and random number generation.

  • 10.
    Aknesil, Can
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers2022In: Proceedings of the 2022 IFIP/IEEE 30th international conference on very large scale integration (VLSI-SOC), Institute of Electrical and Electronics Engineers (IEEE) , 2022Conference paper (Refereed)
    Abstract [en]

    Today's power/EM side-channel analysis is limited by the complexity of the target hardware. We investigate the feasibility of power/EM side-channel analysis of general-purpose computers. This paper makes a step towards this goal by analyzing memory operations of Raspberry Pi 3 Model B, a widely used general-purpose IoT device that is capable of running an operating system, and shows that it is possible to extract information about the data field of memory operations from near-field EM measurements.

  • 11.
    Aknesil, Can
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Lindskog, Niklas
    Ericsson AB, Lund, Sweden.
    Englund, Hakan
    Ericsson AB, Lund, Sweden.
    Is your FPGA transmitting secrets: covert antennas from interconnect2023In: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023, Institute of Electrical and Electronics Engineers (IEEE) , 2023, p. 79-84Conference paper (Refereed)
    Abstract [en]

    A hidden transmitter embedded into a chip to extract secret information is a well-known type of hardware Trojan. Various ways of implementing covert channels have been proposed in the past. The focus of this paper is covert antennas created from the FPGA interconnect. We present several on-chip antenna implementations that leverage the routing resources of FPGAs. The proposed antennas can transmit data processed by the FPGA with bit-level precision. A near-field probe is used to capture the radiated signal and the transmitted data is restored with 100% accuracy. Our results suggest that introducing a routine screening process for covert antennas in FPGA designs, similar to the one performed for ring oscillators, would be of benefit for FPGA security.

  • 12.
    Albertsson, Dagur Ingi
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Spintronic and Electronic Oscillators for Magnetic Field Sensing and Ising Machines2023Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Oscillators can exhibit a range of complex dynamics which are often encountered in nature. These characteristics include synchronization, injection locking, chaos, bifurcations, etc. To date, the applications of electronic oscillators has mostly been limited to communication systems. However, in recent years, the possibility of using the rich dynamics of oscillators in unconventional applications, including time-based information processing and computational applications, has been also explored. In this thesis, this potential is investigated using emerging spintronic oscillators and established electronic oscillators. 

    The first part of this thesis targets emerging spintronic oscillators, which exhibit a range of attractive features, including GHz operating frequency, wide tunability and nanoscale size. To explore the potential of these devices, an electrical behavioural model was developed for the promising three-terminal spin-Hall nano-oscillator. The behavioural model is based on the macrospin approximation, which is commonly used to describe the operation principles of spintronic oscillators, and it was implemented in Verilog-A. Moreover, the behavioural model was verified against experimental measurements from literature, demonstrating that the most important characteristics of three-terminal spin-Hall nano-oscillators are accurately captured. Subsequently, two potential applications that could benefit from the unique characteristics of spintronic oscillators were identified and explored. First, a magnetic field sensing system, which takes advantage of the wide frequency tunability of spintronic oscillators as a function of externally applied magnetic field, was proposed and demonstrated. This sensing system, inspired by voltage-controlled oscillator analog-to-digital converters, shows performance similar to the state-of-the-art magnetic field sensors, making it a promising application for spintronic oscillators. Next, the possibility of utilizing spintronic oscillators to realize Ising machines (IMs) was explored and demonstrated with numerical simulations. This was the first-time demonstration of spintronic oscillator-based Ising machines. The numerical simulation results show that spintronic oscillators are a promising device to realize ultra-fast Ising Machines able to solve complex combinatorial optimization problems on nano-second time scale.

    The second part of the thesis extends on the idea of oscillator-based IMs, but using electronic oscillators. The potential of realizing highly reconfigurable oscillator-based IMs based on quasiperiodically modulated coupling was explored. The advantages and potential challenges associated with this approach were highlighted, and a proof-of-concept IM using CMOS ring oscillators was proposed and simulated. Finally, a completely new type of IMs based on bifurcations in a network of coupled Duffing oscillators was proposed and developed. This work highlights a new research direction based on using dynamical systems implemented with analog circuits to realize IMs.

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  • 13.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Experimental Demonstration of Duffing Oscillator-Based Analog Ising Machines2024In: LASCAS 2024 - 15th IEEE Latin American Symposium on Circuits and Systems, Proceedings, Institute of Electrical and Electronics Engineers (IEEE) , 2024Conference paper (Refereed)
    Abstract [en]

    This paper presents a proof-of-concept analog Ising Machine, which can solve combinatorial optimization problems using bifurcations in networks of coupled Duffing oscillators. The proof-of-concept system consists of a network of four coupled Duffing oscillators implemented with low-cost components on a prototyping board. Experimental results demonstrate that the proposed prototype operates as an Ising Machine and it can solve various Max-Cut problems. This work provides the foundation towards realizing analog Ising Machines based on circuits that exhibit bifurcation properties, such as the Duffing oscillators, and that can be scaled to large networks.

  • 14.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Highly reconfigurable oscillator-based Ising Machine through quasiperiodic modulation of coupling strength2023In: Scientific Reports, E-ISSN 2045-2322, Vol. 13, no 1, article id 4005Article in journal (Refereed)
    Abstract [en]

    Ising Machines (IMs) have the potential to outperform conventional Von-Neuman architectures in notoriously difficult optimization problems. Various IM implementations have been proposed based on quantum, optical, digital and analog CMOS, as well as emerging technologies. Networks of coupled electronic oscillators have recently been shown to exhibit characteristics required for implementing IMs. However, for this approach to successfully solve complex optimization problems, a highly reconfigurable implementation is needed. In this work, the possibility of implementing highly reconfigurable oscillator-based IMs is explored. An implementation based on quasiperiodically modulated coupling strength through a common medium is proposed and its potential is demonstrated through numerical simulations. Moreover, a proof-of-concept implementation based on CMOS coupled ring oscillators is proposed and its functionality is demonstrated. Simulation results show that our proposed architecture can consistently find the Max-Cut solution and demonstrate the potential to greatly simplify the physical implementation of highly reconfigurable oscillator-based IMs.

  • 15.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Ising Machine Based on Bifurcations in a Network of Duffing Oscillators2023In: Proceedings: IEEE International Symposium on Circuits and Systems, Institute of Electrical and Electronics Engineers (IEEE) , 2023Conference paper (Refereed)
    Abstract [en]

    Ising Machines have been extensively explored latelyfor developing new nonconventional computing architectures. Arecently proposed approach, based on simulating a dynamicalsystem exhibiting bifurcations, has shown promising performance. Inspired by this concept, we propose using bifurcationsin a network of coupled electrical Duffing oscillators to realize anIsing Machine. Numerical simulations of large Duffing oscillatornetworks, solving various Max-Cut problems, demonstrate thepotential of our proposed approach for realizing Ising Machinesbased on bifurcations. It also establishes a new direction towardsanalog Ising Machine architectures. 

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    Ising Machine Based on Bifurcations in a Network of Duffing Oscillators
  • 16.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Zahedinejad, Mohammad
    Univ Gothenburg, Phys Dept, S-41296 Gothenburg, Sweden.;NanOsc AB, Elect 229, S-16440 Kista, Sweden..
    Houshang, Afshin
    Univ Gothenburg, Phys Dept, S-41296 Gothenburg, Sweden.;NanOsc AB, Elect 229, S-16440 Kista, Sweden..
    Khymyn, Roman
    Univ Gothenburg, Phys Dept, S-41296 Gothenburg, Sweden..
    Akerman, Johan
    Univ Gothenburg, Phys Dept, S-41296 Gothenburg, Sweden.;NanOsc AB, Elect 229, S-16440 Kista, Sweden..
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Ultrafast Ising Machines using spin torque nano-oscillators2021In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 118, no 11, article id 112404Article in journal (Refereed)
    Abstract [en]

    Combinatorial optimization problems are known for being particularly hard to solve on traditional von Neumann architectures. This has led to the development of Ising Machines (IMs) based on quantum annealers and optical and electronic oscillators, demonstrating speed-ups compared to central processing unit (CPU) and graphics processing unit (GPU) algorithms. Spin torque nano-oscillators (STNOs) have shown GHz operating frequency, nanoscale size, and nanosecond turn-on time, which would allow their use in ultrafast oscillator-based IMs. Here, we show using numerical simulations based on STNO auto-oscillator theory that STNOs exhibit fundamental characteristics needed to realize IMs, including in-phase/out-of-phase synchronization and second harmonic injection locking phase binarization. Furthermore, we demonstrate numerically that large STNO network IMs can solve Max-Cut problems on nanosecond timescales.

  • 17.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Zahedinejad, Mohammad
    Department of Physics, University of Gothenburg.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. Department of Physics, University of Gothenburg.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators2019In: IEEE transactions on magnetics, ISSN 0018-9464, E-ISSN 1941-0069, Vol. 55, no 10, article id 4003808Article in journal (Refereed)
    Abstract [en]

    Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

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  • 18.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Åkerman, Johan
    Department of Physics, University of Gothenburg.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    A Magnetic Field-to-Digital Converter Employing a Spin-Torque Nano-Oscillator2020In: IEEE transactions on nanotechnology, ISSN 1536-125X, E-ISSN 1941-0085, Vol. 19, p. 565-570Article in journal (Refereed)
    Abstract [en]

    In this work, a novel magnetic field-to-digital converter based on emerging spin-torque nano-oscillators (STNOs) is proposed. The architecture is inspired by voltage controlled oscillator (VCO)-based analog-to-digital converters (ADCs) which have shown inherent first-order noise shaping of both quantization- and phase-noise without the need for feedback. In the proposed architecture, the STNO acts both as a magnetic field sensor and VCO. The architecture's performance is evaluated in terms of signal-to-noise and distortion ratio (SNDR) utilizing Verilog-AMS modeling, where a macrospin model fitted to experimental data is employed for accurate description of the STNO operation. The presented simulation results demonstrate the potential of the STNO-based magnetic field-to-digital converter architecture.

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  • 19.
    Altayo Gonzalez, u1dr0yqp
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Stathis, Dimitrios
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Hemani, Ahmed
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design2021In: Proceedings - 2021 15th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2021, Association for Computing Machinery (ACM), 2021, p. 61-66Conference paper (Refereed)
    Abstract [en]

    Synchoros VLSI design style has been proposed as an alternative to the standard cell-based design style; the word synchoros is derived from the Greek word choros for space. Synchoricity discretises space with a virtual grid, the way synchronicity discretises time with clock ticks. SiLago (Silicon Lego) blocks are atomic synchoros building blocks like Lego bricks. SiLago blocks absorb all metal layer details, i.e., all wires, to enable composition by abutment of valid; valid in the sense of being technology design rules compliant, timing clean and OCV ruggedized. Effectively, composition by abutment eliminates logic and physical synthesis for the end user. Like Lego system, synchoricity does need a finite number of SiLago block types to cater to different types of designs. Global NoCs are important system level design components. In this paper, we show, how with a small library of SiLago blocks for global NoCs, it is possible to automatically synthesize arbitrary global NoCs of different types, dimensions, and topology. The synthesized global NoCs are not only valid VLSI designs, but their cost metrics (area, latency, and energy) are known with post-layout accuracy in linear time. We argue that this is essential to be able to do chip-level design space exploration. We show how the abstract timing model of such global NoC SiLago blocks can be built and used to analyse the timing of global NoC links with post layout accuracy and in linear time. We validate this claim by subjecting the same VLSI designs of global NoC to commercial EDA's static timing analysis and show that the abstract timing analysis enabled by synchoros VLSI design gives the same results as the commercial EDA tools.

  • 20.
    Amagat, Jordi
    et al.
    Department of Biological and Chemical Engineering, Aarhus University, Denmark; Sino-Danish College (SDC), University of Chinese Academy of Sciences, Beijing 101400, China.
    Müller, Christoph Alexander
    Department of Biological and Chemical Engineering, Aarhus University, Denmark.
    Jensen, Bjarke Nørrehvedde
    Department of Biological and Chemical Engineering, Aarhus University, Denmark.
    Xiong, Xuya
    Interdisciplinary Nanoscience Center, iNANO, Aarhus University, Denmark.
    Su, Yingchun
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems. Department of Biological and Chemical Engineering, Aarhus University, Denmark.
    Christensen, Natasja Porskjær
    Department of Biological and Chemical Engineering, Aarhus University, Denmark.
    Le Friec, Alice
    Department of Biological and Chemical Engineering, Aarhus University, Denmark.
    Dong, Mingdong
    Interdisciplinary Nanoscience Center, iNANO, Aarhus University, Denmark.
    Fang, Ying
    CAS Center for Excellence in Nanoscience, National Center for Nanoscience and Technology, Beijing 100190, People's Republic of China; CAS Center for Excellence in Brain Science and Intelligence Technology, Institute of Neuroscience, Chinese Academy of Sciences, Shanghai 200031, People's Republic of China.
    Chen, Menglin
    Department of Biological and Chemical Engineering, Aarhus University, Denmark; Interdisciplinary Nanoscience Center, iNANO, Aarhus University, Denmark.
    Injectable 2D flexible hydrogel sheets for optoelectrical/biochemical dual stimulation of neurons2023In: Biomaterials Advances, E-ISSN 2772-9508, Vol. 146, article id 213284Article in journal (Refereed)
    Abstract [en]

    Major challenges in developing implanted neural stimulation devices are the invasiveness, complexity, and cost of the implantation procedure. Here, we report an injectable, nanofibrous 2D flexible hydrogel sheet-based neural stimulation device that can be non-invasively implanted via syringe injection for optoelectrical and biochemical dual stimulation of neuron. Specifically, methacrylated gelatin (GelMA)/alginate hydrogel nanofibers were mechanically reinforced with a poly(lactide-co-ε-caprolactone) (PLCL) core by coaxial electrospinning. The lubricant hydrogel shell enabled not only injectability, but also facile incorporation of functional nanomaterials and bioactives. The nanofibers loaded with photocatatlytic g-C3N4/GO nanoparticles were capable of stimulating neural cells via blue light, with a significant 36.3 % enhancement in neurite extension. Meanwhile, the nerve growth factor (NGF) loaded nanofibers supported a sustained release of NGF with well-maintained function to biochemically stimulate neural differentiation. We have demonstrated the capability of an injectable, hydrogel nanofibrous, neural stimulation system to support neural stimulation both optoelectrically and biochemically, which represents crucial early steps in a larger effort to create a minimally invasive system for neural stimulation.

  • 21.
    Amagat, Jordi
    et al.
    Aarhus Univ, Dept Biol & Chem Engn, Aarhus, Denmark.;Univ Chinese Acad Sci, Sinodanish Coll SDC, Beijing 101400, Peoples R China..
    Su, Yingchun
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems. Aarhus Univ, Dept Biol & Chem Engn, Aarhus, Denmark..
    Svejso, Frederik Hobjerg
    Aarhus Univ, Dept Biol & Chem Engn, Aarhus, Denmark..
    Le Friec, Alice
    Aarhus Univ, Dept Biol & Chem Engn, Aarhus, Denmark..
    Sonderskov, Steffan Moller
    Aarhus Univ, INANO, Interdisciplinary Nanosci Ctr, Aarhus, Denmark..
    Dong, Mingdong
    Aarhus Univ, INANO, Interdisciplinary Nanosci Ctr, Aarhus, Denmark..
    Fang, Ying
    Chinese Acad Sci, Ctr Excellence Nanosci, Natl Ctr Nanosci & Technol, Beijing 100190, Peoples R China.;Chinese Acad Sci, Inst Neurosci, CAS Ctr Excellence Brain Sci & Intelligence Techno, Shanghai 200031, Peoples R China..
    Chen, Menglin
    Aarhus Univ, Dept Biol & Chem Engn, Aarhus, Denmark.;Aarhus Univ, INANO, Interdisciplinary Nanosci Ctr, Aarhus, Denmark.;Aarhus Univ, Univ Byen 36, DK-8000 Aarhus, Denmark..
    Self-snapping hydrogel-based electroactive microchannels as nerve guidance conduits2022In: MATERIALS TODAY BIO, ISSN 2590-0064, Vol. 16, article id 100437Article in journal (Refereed)
    Abstract [en]

    Peripheral nerve regeneration with large defects needs innovative design of nerve guidance conduits (NGCs) which possess anisotropic guidance, electrical induction and right mechanical properties in one. Herein, we present, for the first time, facile fabrication and efficient neural differentiation guidance of anisotropic, conductive, self-snapping, hydrogel-based NGCs. The hydrogels were fabricated via crosslinking of graphitic carbon nitride (g-C3N4) upon exposure with blue light, incorporated with graphene oxide (GO). Incorporation of GO and in situ reduction greatly enhanced surface charges, while decayed light penetration endowed the hydrogel with an intriguing self-snapping feature by the virtue of a crosslinking gradient. The hydrogels were in the optimal mechanical stiffness range for peripheral nerve regeneration and supported normal viability and proliferation of neural cells. The PC12 cells differentiated on the electroactive g-C3N4 H/rGO3 (3 mg/mL GO loading) hydrogel presented 47% longer neurite length than that of the pristine g-C3N4 H hydrogel. Furthermore, the NGC with aligned microchannels was successfully fabricated using sacrificial melt electrowriting (MEW) moulding, the anisotropic microchannels of the 10 mu m width showed optimal neurite guidance. Such anisotropic, electroactive, self-snapping NGCs may possess great potential for repairing peripheral nerve injuries.

  • 22. Anzanpour, A.
    et al.
    Rahmani, Amir Mohammad
    KTH.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Internet of things enabled in-home health monitoring system using early warning score2015In: MOBIHEALTH 2015 - 5th EAI International Conference on Wireless Mobile Communication and Healthcare - Transforming Healthcare through Innovations in Mobile and Wireless Technologies, ICST , 2015Conference paper (Refereed)
    Abstract [en]

    Early warning score (EWS) is an approach to detect the deterioration of a patient. It is based on a fact that there are several changes in the physiological parameters prior a clinical deterioration of a patient. Currently, EWS procedure is mostly used for in-hospital clinical cases and is performed in a manual paper-based fashion. In this paper, we propose an automated EWS health monitoring system to intelligently monitor vital signs and prevent health deterioration for in-home patients using Internet-of-Things (IoT) technologies. IoT enables our solution to provide a real-Time 24/7 service for health professionals to remotely monitor inhome patients via Internet and receive notifications in case of emergency. We also demonstrate a proof-of-concept EWS system where continuous reading, transferring, recording, and processing of vital signs have been implemented. 

  • 23. Arshad, F.
    et al.
    Ali, A.
    Loo, J.
    Amin, Y.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Beam-width agile antenna for 5g mmw applications2020In: Proceedings 2020 International Conference on UK-China Emerging Technologies, UCET 2020, Institute of Electrical and Electronics Engineers (IEEE) , 2020Conference paper (Refereed)
    Abstract [en]

    In this communication, a beam width reconfigurable antenna with the parasitic elements is presented for 5G applications. The proposed antenna consists of an inset fed circular patch (driven element). To enhance the impedance matching a-35° rotated slot is inserted in the circular patch. Four parasitic arcs are placed in the close proximity of the driven element. In first case three pin-diodes are loaded among the arcs to tune the mutual coupling between arcs and driven element. In the second case pin-diodes are replaced with GeTe material based strips for reconfiguration purposes. This design can operate between 27.2-32 GHz with a peak realized gain of 9.1 dBi. In the first case, beamwidth can be enlarged from 58° to 121.3o. In the second case, beamwidth can be vary from 75° to 128.7°. In both cases beam is also steered.

  • 24. Arshad, F.
    et al.
    Amin, Y.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Ali, A.
    Loo, J.
    Polorization Reconfigurable MIMO System for 5G MMW Applications2020In: Proceedings - 2020 23rd IEEE International Multi-Topic Conference, INMIC 2020, Institute of Electrical and Electronics Engineers Inc. , 2020Conference paper (Refereed)
    Abstract [en]

    This paper presents a novel electronically polarization reconfigurable 2 port multi input multi output (MIMO) for millimeter wave (MMW) fifth-generation (5G) wireless communications. The design consists of slotted circular patch. A semicircle and open-ended T-shaped arcs are inserted in circular patch to achieve the circular polarization. Furthermore in order to enhance the gain 2 element array is designed. Two pin-diodes are inserted in antenna array for polarization diversity. The design is extended to two ports MIMO. Port isolation is enhanced between the ports using defected ground structure (DGS). The vertical and horizontal slots are inserted in the ground to enhance the port isolation. The presented design covers dual frequency band that 24.0-25.3 and 27.3-28.7 GHz band. The 27.3-28.7 GHz band is considered for investigation of all parameters. The simulated peak gain is 9.99 dBi. The axial ratio (AR) below-3dB is achieved for whole operating band of proposed design. The MIMO performance parameters like transmission coefficient, Envelop correlation coefficient (ECC), and diversity gain (DG) are also investigated.

  • 25.
    Arshad, Farzana
    et al.
    Univ Engn & Technol Taxila, Telecommun Engn Dept, Taxila 47050, Pakistan..
    Khan, Zia Ullah
    Queen Mary Univ London, Sch Elect Engn & Comp Sci, London, England..
    Ali, Ahsan
    Univ Engn & Technol Taxila, Dept Elect Engn, Taxila, Pakistan..
    Amin, Yasar
    Univ Engn & Technol Taxila, Telecommun Engn Dept, Taxila 47050, Pakistan..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. Royal Inst Technol KTH, Dept Elect Syst, Stockholm, Sweden.;Univ Turku, Dept Informat Technol, Tugs, Turku, Finland..
    Compact beam-switchable antenna for mm-wave 5G handheld devices2021In: IET Microwaves, Antennas & Propagation, ISSN 1751-8725, E-ISSN 1751-8733, Vol. 15, no 7, p. 778-787Article in journal (Refereed)
    Abstract [en]

    An electronically beam-steerable antenna (BSA) is envisioned. The presented BSA is a possible solution to overthrow the limitations inherent to phased antenna arrays. The design consists of a gap coupling inset feed rectangular patch (driven element) and 3 x 1 passive parasitic patches deployed on both sides of the driven patch. Prototype having 20 x 20 mm dimensions is printed on Rogers(R) RT/duroid(R)5870. Four switches are used to load the reactive impedance on parasitic patches, which in turn, change the phases of surface current on parasitic elements and the driven element. Based on the different ON and OFF configuration of switches in parasitic array elements, the main beam is steered along with different directions. The simulated results show that the design can operate between 26.8 and 30.3 GHz a wide impedance bandwidth |S-11|< -10 dB (12.5%) with a peak gain of 8.9 dBi and wide 3-dB scanning angle that is, -37 degrees to 156 degrees in the azimuth plane. The exhibited performance of BSA with favourable characteristics, such as wideband, adequate gain, wide-angle beam switching, and low profile renders the BSA a good candidate for 5G millimetre wave handheld devices. Moreover, to corroborate the performance, the design is fabricated, and experimental measurements were performed. Congruence is observed between the experimentally measured and computationally simulated results. The simulated results of spherical coverage analysis of BSA with the integration of smartphone form factor are also presented.

  • 26.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH.
    Compressive-Strained Ge and Tensile-Strained SiGe on Insulator Fabrication via Wafer Bonding for Monolithic 3D IntegrationManuscript (preprint) (Other academic)
  • 27.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration2018Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

      To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

      The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

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  • 28.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH.
    Low Temperature SiGe Epitaxy Using SiH4-GeH4and Si2H6-Ge2H6 Gas PrecursorsIn: Journal of Solid State Science and TechnologyArticle in journal (Other academic)
  • 29.
    Aslam, Bilal
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Azam, Muhammad A.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
    Loo, Jonathan
    Middlesex Univ, Sch Engn & Informat Sci, Dept Comp Sci, London, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    A high capacity tunable retransmission type frequency coded chipless radio frequency identification system2019In: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 29, no 9, article id e21855Article in journal (Refereed)
    Abstract [en]

    This article presents a 12-bit frequency coded chipless RFID system in the frequency range of 3 to 6 GHz. The system consists of a fully printable chipless tag and a pair of high-gain reader antennas. The tag also incorporates its own antennas to improve the read range. Information is encoded into frequency spectrum using a multi-resonant circuit. The circuit consists of multiple microstrip U and L-shaped open stub resonators patterned in a unique configuration. The proposed configuration aids in capturing more data in a reduced space as well as tunable frequency operation. Tag and reader antennas utilize techniques such as stepped impedance feeding line, defective partial ground plane, and stair-step patch structure to achieve wide-band impedance bandwidth in miniature size. The results of the wireless measurements in the non-anechoic environment show that the proposed system has a reading range of more than 20 cm. The presented system possesses great potential for low-cost short-range inventory tracking.

  • 30.
    Aslam, Bilal
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Pakistan..
    Kashif, Muhammad
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Pakistan.;Beijing Univ Aeronaut & Astronaut, Beijing, Peoples R China..
    Amin, Yasar
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Pakistan.;Royal Inst Technol KTH, iPack Vinn Excellence Ctr, Dept Elect Syst, Stockholm, Sweden..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. Royal Inst Technol KTH, iPack Vinn Excellence Ctr, Dept Elect Syst, Stockholm, Sweden..
    Low-profile magnetically coupled dual resonance patch antenna for UHF RFID applications2021In: AEU - International Journal of Electronics and Communications, ISSN 1434-8411, E-ISSN 1618-0399, Vol. 133, article id 153672Article in journal (Refereed)
    Abstract [en]

    A novel low-profile metal mountable UHF RFID tag antenna is presented. The tag antenna design consists of two resonating patches with different resonant frequencies fed through a joint inductive loop. This design topology offers benefits such as bandwidth enhancement in the single band and the possibility of attaining a tunable dualband coverage in the UHF RFID band. The proposed antenna structure doesn't require any electrical connection (shorting pins/shorting plates/via holes) and therefore facilitates fabrication through a conventional RFID inlay manufacturing process. Fabrication and testing of a prototype of the proposed antenna design are carried out. The prototype antenna achieves free space and an on-metal reading range of better than 8 m and 11 m respectively in the US RFID band of 902-928 MHz.

  • 31.
    Aslam, Bilal
    et al.
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan..
    Kashif, Muhammad
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.;Beijing Univ Aeronaut & Astronaut, Beijing, Peoples R China..
    Azam, Muhammad Awais
    Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan..
    Amin, Yasar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.
    Loo, Jonathan
    Univ West London, Sch Comp & Commun Engn, Dept Comp Sci, London, England..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. Univ Turku, Dept Informat Technol, TUCS, Turku, Finland..
    A low profile miniature RFID tag antenna dedicated to IoT applications2019In: Electromagnetics, ISSN 0272-6343, E-ISSN 1532-527X, Vol. 39, no 6, p. 393-406Article in journal (Refereed)
    Abstract [en]

    RFID tag antennas with stable performance on the diverse electromagnetic mounting platforms are an integral part of the ubiquitous RFID systems. This research article presents a novel tag antenna design that facilitates the said objective. The proposed antenna consists of a modified H-shaped slot structure that ensures considerable robustness from the application environment through confining the surface current density within the antenna structure. The antenna offers a tunable bandwidth of 40 MHz within the microwave band of (2.4-2.5) GHz. The proposed tag antenna exhibits excellent response on metallic platforms of different sizes and thicknesses with an effective gain of almost four times of that in free space. Furthermore, the designed tag antenna performs adequately well on low-medium permittivity dielectrics (glass, paper, and plastic) and RF absorbers (water). The free space and on-metal performance of the proposed tag antenna are verified by testing a prototype realized on the FR4 substrate.

  • 32. Attarzadeh-Niaki, S. -H
    et al.
    Sander, Ingo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Heterogeneous co-simulation for embedded and cyber-physical systems design2020In: Simulation (San Diego, Calif.), ISSN 0037-5497, E-ISSN 1741-3133, Vol. 96, no 9, p. 753-765Article in journal (Refereed)
    Abstract [en]

    The growing complexity of embedded and cyber-physical systems makes the design of all system components from scratch increasingly impractical. Consequently, already from early stages of a design flow, designers rely on prior experience, which comes in the form of legacy code or third-party intellectual property (IP) blocks. Current approaches partly address the co-simulation problem for specific scenarios in an ad hoc style. This work suggests a general method for co-simulation of heterogeneous IPs with a system modeling and simulation framework. The external IPs can be integrated as high-level models running in an external simulator or as software- and hardware-in-the-loop simulation with minimal effort. Examples of co-simulation scenarios for wrapping models with different semantics are presented together with their practical usage in two case studies. The presented method is also used to formulate a refinement-by-replacement workflow for IP-based system design.

  • 33. Attarzadeh-Niaki, S. -H
    et al.
    Sander, Ingo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Ahmadi, M.
    An automated parallel simulation flow for cyber-physical system design2021In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 77, p. 48-58Article in journal (Refereed)
    Abstract [en]

    Parallel and distributed simulation (PDS) is often employed to tackle the computational intensity of system-level simulation of real-world complex embedded and cyber-physical systems (CPSs). However, CPS models comprise heterogeneous components with diverge semantics for which incompatible PDS approaches are developed. We propose an automated PDS flow based on a formal modeling framework—with necessary extensions—targeting heterogeneous embedded and CPS design. The proposed flow characterizes the sequential executable specification of a heterogeneous model and generates a PDS cluster. State-of-the-art graph partitioning methods are adopted and a new extensible constraint-base formulation of the model partitioning problem is developed. The applicability, effectiveness, and scalability of the proposed flow is demonstrated using case studies.

  • 34.
    Aybek, Mehmet Onur
    et al.
    Arcticus Syst AB, Järfälla, Sweden..
    Jordao, Rodolfo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Lundbäck, John
    Arcticus Syst AB, Järfälla, Sweden..
    Lundbäck, Kurt-Lennart
    Arcticus Syst AB, Järfälla, Sweden..
    Becker, Matthias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    From the Synchronous Data Flow Model of Computation to an Automotive Component Model2021In: Proceedings 26th IEEE International Conference on Emerging Technologies and Factory Automation, ETFA 2021, Institute of Electrical and Electronics Engineers (IEEE) , 2021Conference paper (Refereed)
    Abstract [en]

    The size and complexity of automotive software systems are steadily increasing. Software functions are subject to different requirements and belong to different functional domains of the car. Meanwhile, streaming applications have become increasingly relevant in emerging application areas such as Advanced Driving Assistance Systems. Among models for streaming applications, the Synchronous Data Flow model is well-known for its analysable properties. This work presents transformation rules that allow transforming applications described by the Synchronous Data Flow model to an automotive component model. The proposed transformation rules are implemented in form of a software plugin for an automotive tool suite that allows for timing analysis, code synthesis and deployment to a Real-Time Operating System. To demonstrate the applicability of the proposed approach, a case study of a Kalman filter that is part of a simplified cruise control application is presented. An abstract Synchronous Data Flow model of the filter is transformed into a component that is deployed on an Electronic Control Unit with hard timing guarantees.

  • 35. Ayedh, H. M.
    et al.
    Bathen, M. E.
    Galeckas, A.
    Hassan, J. U.
    Bergman, J. P.
    Nipoti, R.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Svensson, B. G.
    Controlling the carbon vacancy in 4H-SiC by thermal processing2018In: ECS Transactions, Electrochemical Society Inc. , 2018, no 12, p. 91-97Conference paper (Refereed)
    Abstract [en]

    The carbon vacancy (Vc) is perhaps the most prominent point defect in silicon carbide (SiC) and it is an efficient charge carrier lifetime killer in high-purity epitaxial layers of 4H-SÌC. The Vc concentration needs to be controlled and minimized for optimum materials and device performance, and an approach based on post-growth thermal processing under C-rich ambient conditions is presented. It utilizes thermodynamic equilibration and after heat treatment at 1500 °C for 1 h, the Vc concentration is shown to be reduced by a factor-25 relative to that in as-grown state-of-the-art epi-layers. Concurrently, a considerable enhancement of the carrier lifetime occurs throughout the whole of >40 urn thick epi-layers. 

  • 36.
    Ayedh, H. M.
    et al.
    Univ Oslo, Dept Phys, POB 1048 Blindern, N-0316 Oslo, Norway.;Aalto Univ, Dept Elect & Nanoengn, Tietotie 3, FI-02150 Espoo, Finland..
    Kvamsdal, K-E
    Univ Oslo, Dept Phys, POB 1048 Blindern, N-0316 Oslo, Norway..
    Bobal, V
    Univ Oslo, Dept Phys, POB 1048 Blindern, N-0316 Oslo, Norway..
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Ling, F. C. C.
    Univ Hong Kong, Dept Phys, Pokfulam, Hong Kong, Peoples R China..
    Kuznetsov, A. Yu
    Univ Oslo, Dept Phys, POB 1048 Blindern, N-0316 Oslo, Norway..
    Carbon vacancy control in p(+)-n silicon carbide diodes for high voltage bipolar applications2021In: Journal of Physics D: Applied Physics, ISSN 0022-3727, E-ISSN 1361-6463, Vol. 54, no 45, article id 455106Article in journal (Refereed)
    Abstract [en]

    Controlling the carbon vacancy (V-C) in silicon carbide (SiC) is one of the major remaining bottleneck in manufacturing of high voltage SiC bipolar devices, because V-C provokes recombination levels in the bandgap, offensively reducing the charge carrier lifetime. In literature, prominent V-C evolutions have been measured by capacitance spectroscopy employing Schottky diodes, however the trade-offs occurring in the p(+)-n diodes received much less attention. In the present work, applying similar methodology, we showed that V-C is re-generated to its unacceptably high equilibrium level at similar to 2 x10(13) V-C cm(-3) by 1800 degrees C anneals required for the implanted acceptor activation in the p(+)-n components. Nevertheless, we have also demonstrated that the V-C eliminating by thermodynamic equilibrium anneals at 1500 degrees C employing carbon-cap can be readily integrated into the p(+)-n components fabrication resulting in <= 10(11) V-C cm(-3), potentially paving the way towards the realization of the high voltage SiC bipolar devices.

  • 37. Ayedh, H. M.
    et al.
    Nipoti, R.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Svensson, B. G.
    Isothermal treatment effects on the carbon vacancy in 4H silicon carbide2015In: Mater. Sci. Forum, Trans Tech Publications, Ltd. , 2015, p. 351-354Conference paper (Refereed)
    Abstract [en]

    The carbon vacancy (VC) is a minority carrier lifetime controlling defect in 4H-SiC and it is formed during high temperature treatment. In this study, we have performed heat treatment on two sets of n-type 4H-SiC epitaxial samples. The first set was isothermally treated at 1850 °C to follow the evolution of VC as a function of time. The VC concentration is not affected by changing the duration. Samples of the other set were treated at 1950 °C for 10 min, but with different cooling rates and a reduction of the VC concentration was indeed demonstrated by lowering the cooling rate. The VC concentration in the slow-cooled sample is about 2 times less than in the fast-cooled one, reflecting a competition between equilibrium conditions and the cooling rate.

  • 38.
    Ayedh, H. M.
    et al.
    Norway.
    Nipoti, R.
    Italy.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Svensson, B. G.
    Norway.
    Kinetics modeling of the carbon vacancy thermal equilibration in 4H-SiC2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 233-236Conference paper (Refereed)
    Abstract [en]

    The carbon vacancy (VC) is a major limiting-defect of minority carrier lifetime in n-type 4H-SiC epitaxial layers and it is readily formed during high temperature processing. In this study, a kinetics model is put forward to address the thermodynamic equilibration of VC, elucidating the possible atomistic mechanisms that control the VC equilibration under C-rich conditions. Frenkel pair generation, injection of carbon interstitials (Ci’s) from the C-rich surface, followed by recombination with VC’s, and diffusion of VC’s towards the surface appear to be the major mechanisms involved. The modelling results show a close agreement with experimental deep-level transient spectroscopy (DLTS) depth profiles of VC after annealing at different temperatures.

  • 39.
    Azarov, Alexander
    et al.
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway.;Natl Ctr Nucl Res, A Soltana 7, PL-05400 Otwock, Poland..
    Aarseth, Bjorn L.
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Vines, Lasse
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Monakhov, Edouard
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Kuznetsov, Andrej
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Defect annealing kinetics in ZnO implanted with Zn substituting elements: Zn interstitials and Li redistribution2019In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 125, no 7, article id 075703Article in journal (Refereed)
    Abstract [en]

    It is known that the behavior of residual Li in ion implanted ZnO depends on the preferential localization of the implants, in particular, forming characteristic Li depleted or Li pile-up regions for Zn or O sublattice occupation of the implants due to the corresponding excess generation of Zn and O interstitials in accordance with the so-called "+1 model." However, the present study reveals that conditions for the radiation damage annealing introduce additional complexity into the interpretation of the Li redistribution trends. Specifically, four implants residing predominantly in the Zn-sublattice, but exhibiting different lattice recovery routes, were considered. Analyzing Li redistribution trends in these samples, it is clearly shown that Li behavior depends on the defect annealing kinetics which is a strong function of the implanted fluence and ion species. Thus, Li depleted and Li pile-up regions (or even combinations of the two) were observed and correlated with the defect evolution in the samples. It is discussed how the observed Li redistribution trends can be used for better understanding a thermal evolution of point defects in ZnO and, in particular, energetics and migration properties of Zn interstitials.

  • 40.
    Baccelli, Guido
    et al.
    Politecn Torino, DET, Turin, Italy..
    Stathis, Dimitrios
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Hemani, Ahmed
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Martina, Maurizio
    Politecn Torino, DET, Turin, Italy..
    NACU: A Non-Linear Arithmetic Unit for Neural Networks2020In: PROCEEDINGS OF THE 2020 57TH ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), IEEE , 2020Conference paper (Refereed)
    Abstract [en]

    Reconfigurable architectures targeting neural networks are an attractive option. They allow multiple neural networks of different types to be hosted on the same hardware, in parallel or sequence. Reconfig-urability also grants the ability to morph into different micro-architectures to meet varying power-performance constraints. In this context, the need for a reconfigurable non-linear computational unit has not been widely researched. In this work, we present a formal and comprehensive method to select the optimal fixed-point representation to achieve the highest accuracy against the floating-point implementation benchmark. We also present a novel design of an optimised reconfigurable arithmetic unit for calculating non-linear functions. The unit can be dynamically configured to calculate the sigmoid, hyperbolic tangent, and exponential function using the same underlying hardware. We compare our work with the state-of-the-art and show that our unit can calculate all three functions without loss of accuracy.

  • 41.
    Backlund, Linus
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Ngo, Kalle
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Gärtner, Joel
    KTH, School of Engineering Sciences (SCI), Mathematics (Dept.), Mathematics (Div.).
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Secret Key Recovery Attack on Masked and Shuffled Implementations of CRYSTALS-Kyber and Saber2023In: Applied Cryptography and Network Security Workshops - ACNS 2023 Satellite Workshops, ADSC, AIBlock, AIHWS, AIoTS, CIMSS, Cloud S and P, SCI, SecMT, SiMLA, Proceedings, Springer Nature , 2023, p. 159-177Conference paper (Refereed)
    Abstract [en]

    Shuffling is a well-known countermeasure against side-channel attacks. It typically uses the Fisher-Yates (FY) algorithm to generate a random permutation which is then utilized as the loop iterator to index the processing of the variables inside the loop. The processing order is scrambled as a result, making side-channel attacks more difficult. Recently, a side-channel attack on a masked and shuffled implementation of Saber requiring 61,680 power traces to extract the long-term secret key was reported. In this paper, we present an attack that can recover the long-term secret key of Saber from 4,608 traces. The key idea behind the 13-fold improvement is to recover FY indexes directly, rather than by extracting the message Hamming weight and bit flipping, as in the previous attack. We capture a power trace during the execution of the decryption algorithm for a given ciphertext, recover FY indexes 0 and 255, and extract the corresponding two message bits. Then, we modify the ciphertext to cyclically rotate the message, capture a power trace, and extract the next two message bits with FY indexes 0 and 255. In this way, all message bits can be extracted. By recovering messages contained in k∗ l chosen ciphertexts constructed using a new method based on error-correcting codes of length l, where k is the module rank, we recover the long-term secret key. To demonstrate the generality of the presented approach, we also recover the secret key from a masked and shuffled implementation of CRYSTALS-Kyber, which NIST recently selected as a new public-key encryption and key-establishment algorithm to be standardized.

  • 42.
    Backlund, Linus
    et al.
    KTH.
    Ngo, Kalle
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Gärtner, Joel
    KTH.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Secret Key Recovery Attacks on Masked and Shuffled Implementations of CRYSTALS-Kyber and SaberManuscript (preprint) (Other academic)
    Abstract [en]

    Shuffling is a well-known countermeasure against side-channel analysis. It typically uses the Fisher-Yates (FY) algorithm to generate a random permutation which is then utilized as the loop iterator to index the processing of the variables inside the loop. The processing order is scrambled as a result, making side-channel analysis more difficult. Recently, a side-channel attack on a masked and shuffled implementation of Saber requiring 61,680 power traces to extract the secret key was reported. In this paper, we present an attack that can recover the secret key of Saber from 4,608 traces. The key idea behind the 13-fold improvement is to recover FY indexes directly, rather than by extracting the message Hamming weight and bit flipping, as in the previous attack.We capture a power trace during the execution of the decapsulation algorithm for a given ciphertext, recover FY indexes 0 and 255, and extract the corresponding two message bits. Then, we modify the ciphertext to cyclically rotate the message, capture a power trace, and extract the next two message bits with FY indexes 0 and 255. In this way, all message bits can be extracted.By recovering messages contained in $k*l$ chosen ciphertexts constructed using a new method based on error-correcting codes with length $l$, where $k$ is the security level, we recover the long term secret key. To demonstrate the generality of the presented approach, we also recover the secret key from a masked and shuffled implementation of CRYSTALS-Kyber, which NIST recently selected as a new public-key encryption and key-establishment algorithm to be standardized.

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  • 43.
    Baharloo, Mohammad
    et al.
    University of Tehran, Tehran, Iran.
    Khonsari, Ahmen
    University of Tehran, Tehran, Iran.
    Dolati, Mahdi
    University of Tehran, Tehran, Iran.
    Shiri, Pouya
    University of Victoria, BC, Canada.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Rahmati, Dara
    University of Tehran, Tehran, Iran.
    Traffic-aware performance optimization in Real-time wireless network on chip2020In: Nano Communication Networks, ISSN 1878-7789, E-ISSN 1878-7797, Vol. 26, article id 100321Article in journal (Refereed)
    Abstract [en]

    Network on Chip (NoC) is a prevailing communication platform for multi-core embedded systems. Wireless network on chip (WNoC) employs wired and wireless technologies simultaneously to improve the performance and power-efficiency of traditional NoCs. In this paper, we propose a deterministic and scalable arbitration mechanism for the medium access control in the wireless plane and present its analytical worst-case delay model in a certain use-case scenario that considers both Real-time (RT) and Non Real-time (NRT) flows with different packet sizes. Furthermore, we design an optimization model to jointly consider the worst-case and the average-case performance parameters of the system. The Optimization technique determines how NRT flows are allowed to use the wireless plane in a way that all RT flows meet their deadlines, and the average case delay of the WNoC is minimized. Results show that our proposed approach decreases the average latency of network flows up to 17.9%, and 11.5% in 5 × 5, and 6 × 6 mesh sizes, respectively.

    Download full text (pdf)
    fulltext
  • 44.
    Batista, Gracieth Cavalcanti
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. Electronic Engineering Division, Aeronautics Institute of Technology, Sao Jose dos Campos SP 12228-900, Brazil, SP.
    Öberg, Johnny
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Saotome, Osamu
    Electronic Engineering Division, Aeronautics Institute of Technology, Sao Jose dos Campos SP 12228-900, Brazil, SP.
    de Campos Velho, Haroldo F.
    Laboratory of Applied Computing and Mathematics, Institute for Space Research (INPE), Sao Jose dos Campos SP 12227-900, Brazil, SP.
    Shiguemori, Elcio Hideiti
    Electronic Engineering Division, Aeronautics Institute of Technology, Sao Jose dos Campos SP 12228-900, Brazil, SP; Dept. of C4ISR, Institute for Advanced Studies, Sao Jose dos Campos SP 12228-001, Brazil, SP.
    Söderquist, Ingemar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. Saab AB, Linköping 581 88, Sweden.
    Machine learning algorithm partially reconfigured on FPGA for an image edge detection system2024In: Journal of Electronic Science and Technology, ISSN 1674-862X, Vol. 22, no 2, article id 100248Article in journal (Refereed)
    Abstract [en]

    Unmanned aerial vehicles (UAVs) have been widely used in military, medical, wireless communications, aerial surveillance, etc. One key topic involving UAVs is pose estimation in autonomous navigation. A standard procedure for this process is to combine inertial navigation system sensor information with the global navigation satellite system (GNSS) signal. However, some factors can interfere with the GNSS signal, such as ionospheric scintillation, jamming, or spoofing. One alternative method to avoid using the GNSS signal is to apply an image processing approach by matching UAV images with georeferenced images. But a high effort is required for image edge extraction. In this paper, a support vector regression (SVR) model is proposed to reduce this computational load and processing time. The dynamic partial reconfiguration (DPR) of part of the SVR datapath is implementated to accelerate the process, reduce the area, and analyze its granularity by increasing the grain size of the reconfigurable region. Results show that the implementation in hardware is 68 times faster than that in software. This architecure with DPR also facilitates the low power consumption of 4 ​mW, leading to a reduction of 57% than that without DPR. This is also the lowest power consumption in current machine learning hardware implementations. Besides, the circuitry area is 41 times smaller. SVR with Gaussian kernel shows a success rate of 99.18% and minimum square error of 0.0146 for testing with the planning trajectory. This system is useful for adaptive applications where the user/designer can modify/reconfigure the hardware layout during its application, thus contributing to lower power consumption, smaller hardware area, and shorter execution time.

  • 45.
    Becker, Matthias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Meeting Job-Level Dependencies by Task Merging2024In: 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024, Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 792-798Conference paper (Refereed)
    Abstract [en]

    Industrial applications are often time critical and subject to end-to-end latency constraints. Job-level dependencies can be leveraged to specify a partial ordering on tasks' jobs already at early design phases, agnostic of the hardware platform or scheduling algorithm, and guarantee that end-to-end latency constraints of task chains are met as long as the job-level dependencies are respected. However, their realization at runtime can introduce overheads and complicates the scheduling and timing analysis. This work presents an approach that merges multi-periodic tasks that are connected by job-level dependencies to a single task. A Constraint Programming formulation is presented that optimally merges such task clusters while all job-level dependencies are respected. Such an approach removes the need to consider job-level dependencies at runtime without being bound to a specific scheduling algorithm. Evaluations highlight the applicability of the approach by systemlevel experiments and showcase the scalability of the approach using synthetic task clusters.

  • 46.
    Becker, Matthias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Dasari, Dakshina
    Robert Bosch GmbH, Gerlingen, Germany..
    Casini, Daniel
    Scuola Super StAnna, TeCIP Inst, Pisa, Italy.;Scuola Super StAnna, Dept Excellence Robot & AI, Pisa, Italy..
    On the QNX IPC: Assessing Predictability for Local and Distributed Real-Time Systems2023In: 2023 IEEE 29TH REAL-TIME AND EMBEDDED TECHNOLOGY AND APPLICATIONS SYMPOSIUM, RTAS, Institute of Electrical and Electronics Engineers (IEEE) , 2023, p. 289-302Conference paper (Refereed)
    Abstract [en]

    With the advent of massively distributed applications such as those required by the IoT-to-Edge-to-Cloud compute continuum (i.e., automotive, smart agriculture, smart manufacturing, and more), real-time communication mechanisms allowing physically distributed nodes to seamlessly communicate as if they were running on the same host acquired noteworthy importance. To this end, the synchronous inter-process communication (IPC) mechanism provided by the QNX operating system (OS) is a promising candidate, as it allows using the application programming interface for communicating both on a single- and multi-node setting. Furthermore, it provides priority and partition inheritance mechanisms to improve predictability when working with the Adaptive Partitioning Scheduler (APS), a reservation-based scheduler provided by the QNX OS. This paper explores the behavior of the QNX synchronous message-passing (SyncMP) IPC with an extensive set of experiments, using them to formalize its behavior and model it from a real-time perspective. Then, it provides a response-time analysis for client-server applications based on the QNX SyncMP building upon self-suspending task theory. Finally, we evaluate the analysis on an application based on the WATERS 2019 Challenge by Bosch.

  • 47.
    Becker, Matthias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Chen, DeJiu
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics. KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Machine Design (Div.).
    An adaptive resource provisioning scheme for industrial SDN networks2019In: IEEE International Conference on Industrial Informatics (INDIN), Institute of Electrical and Electronics Engineers Inc. , 2019, p. 877-880Conference paper (Refereed)
    Abstract [en]

    Many industrial domains face the challenge of ever growing networks, driven for example by Internet-of-Things and Industry 4.0. This typically comes together with increased network configuration and management efforts. In addition to the increasing network size, these domains typically are subject to adaptive load situations that pose an additional challenge on the network infrastructure.Software defined networking (SDN) is a promising networking paradigm that reduces configuration complexity and management effort in Ethernet networks. In this work, we investigate SDN in context of adaptive scenarios with QoS constraints. Our approach applies monitoring of several thresholds which automatically trigger redistribution of resources via the central SDN controller. This setup leads to an agile system that can dynamically react to load changes while the infrastructure is not overprovisioned. The approach is implemented in a low-level simulation environment where we demonstrate the benefits of the approach using a case study.

  • 48.
    Becker, Matthias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Chen, DeJiu
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Machine Design (Div.). KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Towards QoS-Aware Service-Oriented Communication in E/E Automotive Architectures2018In: Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society (IECON), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 4096-4101, article id 8591521Conference paper (Refereed)
    Abstract [en]

    With the raise of increasingly advanced driving assistance systems in modern cars, execution platforms that build on the principle of service-oriented architectures are being proposed. Alongside, service oriented communication is used to provide the required adaptive communication infrastructure on top of automotive Ethernet networks. A middleware is proposed that enables QoS aware service-oriented communication between software components, where the prescribed behavior of each software component is defined by Assume/Guarantee (A-G) contracts. To enable the use of COTS components, that are often not sufficiently verified for the use in automotive systems, the middleware monitors the communication behavior of components and verifies it against the components A/G contract. A violation of the allowed communication behavior then triggers adaption processes in the system while the impact on other communication is minimized. The applicability of the approach is demonstrated by a case study that utilizes a prototype implementation of the proposed approach.

  • 49.
    Becker, Matthias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Mubeen, Saad
    Mälardalen University.
    Timing Analysis Driven Design-Space Exploration of Cause-Effect Chains in Automotive Systems2018In: IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society, 2018Conference paper (Refereed)
    Abstract [en]

    Model-based development and component-based software engineering have emerged as a promising approach to deal with enormous software complexity in automotive systems. This approach supports the development of software architectures by interconnecting (and reusing) software components (SWCs) at various abstraction levels. Automotive software architectures are often modeled with chains of SWCs, also called cause-effect chains that are constrained by timing requirements. Based on the variations in activation patterns of SWCs, a single model of a cause-effect chain at a higher abstraction level can conform to several valid refined models of the chain at a lower abstraction level, which is closer to the system implementation. As a consequence, the total number of valid implementation-level models generated by the existing techniques increases exponentially, thereby significantly increasing the runtime of the timing analysis engines and liming the scalability of the existing techniques. This paper computes an upper bound on the activation pattern combinations that may result from a system of cause-effect chains in a given high-level model of the software architecture. An efficient algorithm is presented that traverses only a reduced number of possible combinations of the cause-effect chains, resulting in the timing analysis of a significantly lower number of implementation-level models of the software architecture. A proof of concept is provided by conducting a case study that shows significant reduction in the runtime of timing analysis engines, i.e., the timing behavior of the considered system is verified by performing the timing analysis of only 27% of all possible combinations of the cause-effect chains.

  • 50. Ben Dhaou, I.
    et al.
    Kondoro, Aron
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. University of Dar es Salaam, Tanzania.
    Kelati, Amleset
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems. University of Turku, Finland.
    Rwegasira, Diana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. University of Turku, Finland.
    Naiman, S.
    Mvungi, N. H.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Communication and security technologies for smart grid2018In: Fog Computing: Breakthroughs in Research and Practice, IGI Global , 2018, p. 305-331Chapter in book (Other academic)
    Abstract [en]

    The smart grid is a new paradigm that aims to modernize the legacy power grid. It is based on the integration of ICT technologies, embedded system, sensors, renewable energy and advanced algorithms for management and optimization. The smart grid is a system of systems in which communication technology plays a vital role. Safe operations of the smart grid need a careful design of the communication protocols, cryptographic schemes, and computing technology. In this article, the authors describe current communication technologies, recently proposed algorithms, protocols, and architectures for securing smart grid communication network. They analyzed in a unifying approach the three principles pillars of smart-gird: Sensors, communication technologies, and security. Finally, the authors elaborate open issues in the smart-grid communication network.

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