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• 1.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
GOI fabrication for Monolithic 3D integrationIn: Article in journal (Other academic)
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Penta-band antenna with defected ground structure for wireless communication applications2019In: 2019 2nd International Conference on Computing, Mathematics and Engineering Technologies, iCoMET 2019, Institute of Electrical and Electronics Engineers Inc. , 2019Conference paper (Refereed)

This work proposes a compact, penta-band, slotted antenna with Defected Ground Structure (DGS). The proposed multiband resonator is intended for integration into microwave circuits and portable RF portable devices. The prototype with spurlines and DGS is designed on thin Rogers RT Duroid 5880 substrate having thickness 0.508 mm. The presented radiator is capable to cover the frequency bands 2.46-2.59 GHz, 2.99-3.78 GHz, 5.17-5.89 GHz, 6.86-7.36 GHz, 9.38-11 GHz. The impedance bandwidths of 5.24%, 23.68%, 12.8%, 7.24% and 16.08% is obtained for the covered frequency bands respectively. The antenna proposed in this work thus supports WLAN, WiMAX, ISM, LTE, Bluetooth, C-band and X-band applications. The radiator attains 4.2 dB peak gain. It is apparent from the radiation performance of the prototype, that it is an effective candidate for current and forthcoming multiband wireless applications.

• 3.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Department of Physics, University of Gothenburg. KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. Department of Physics, University of Gothenburg. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators2019In: IEEE transactions on magnetics, ISSN 0018-9464, E-ISSN 1941-0069, Vol. 55, no 10, article id 4003808Article in journal (Refereed)

Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

• 4.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
Compressive-Strained Ge and Tensile-Strained SiGe on Insulator Fabrication via Wafer Bonding for Monolithic 3D IntegrationManuscript (preprint) (Other academic)
• 5.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration2018Doctoral thesis, comprehensive summary (Other academic)

The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

• 6.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
Low Temperature SiGe Epitaxy Using SiH4-GeH4and Si2H6-Ge2H6 Gas PrecursorsIn: Journal of Solid State Science and TechnologyArticle in journal (Other academic)
• 7.
Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan..
Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan.. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila, Punjab, Pakistan.. Middlesex Univ, Sch Engn & Informat Sci, Dept Comp Sci, London, England.. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
A high capacity tunable retransmission type frequency coded chipless radio frequency identification system2019In: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 29, no 9, article id e21855Article in journal (Refereed)

This article presents a 12-bit frequency coded chipless RFID system in the frequency range of 3 to 6 GHz. The system consists of a fully printable chipless tag and a pair of high-gain reader antennas. The tag also incorporates its own antennas to improve the read range. Information is encoded into frequency spectrum using a multi-resonant circuit. The circuit consists of multiple microstrip U and L-shaped open stub resonators patterned in a unique configuration. The proposed configuration aids in capturing more data in a reduced space as well as tunable frequency operation. Tag and reader antennas utilize techniques such as stepped impedance feeding line, defective partial ground plane, and stair-step patch structure to achieve wide-band impedance bandwidth in miniature size. The results of the wireless measurements in the non-anechoic environment show that the proposed system has a reading range of more than 20 cm. The presented system possesses great potential for low-cost short-range inventory tracking.

• 8. Ayedh, H. M.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Controlling the carbon vacancy in 4H-SiC by thermal processing2018In: ECS Transactions, Electrochemical Society Inc. , 2018, no 12, p. 91-97Conference paper (Refereed)

The carbon vacancy (Vc) is perhaps the most prominent point defect in silicon carbide (SiC) and it is an efficient charge carrier lifetime killer in high-purity epitaxial layers of 4H-SÌC. The Vc concentration needs to be controlled and minimized for optimum materials and device performance, and an approach based on post-growth thermal processing under C-rich ambient conditions is presented. It utilizes thermodynamic equilibration and after heat treatment at 1500 °C for 1 h, the Vc concentration is shown to be reduced by a factor-25 relative to that in as-grown state-of-the-art epi-layers. Concurrently, a considerable enhancement of the carrier lifetime occurs throughout the whole of >40 urn thick epi-layers.

• 9.
Norway.
Italy. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Norway.
Kinetics modeling of the carbon vacancy thermal equilibration in 4H-SiC2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 233-236Conference paper (Refereed)

The carbon vacancy (VC) is a major limiting-defect of minority carrier lifetime in n-type 4H-SiC epitaxial layers and it is readily formed during high temperature processing. In this study, a kinetics model is put forward to address the thermodynamic equilibration of VC, elucidating the possible atomistic mechanisms that control the VC equilibration under C-rich conditions. Frenkel pair generation, injection of carbon interstitials (Ci’s) from the C-rich surface, followed by recombination with VC’s, and diffusion of VC’s towards the surface appear to be the major mechanisms involved. The modelling results show a close agreement with experimental deep-level transient spectroscopy (DLTS) depth profiles of VC after annealing at different temperatures.

• 10.
Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway.;Natl Ctr Nucl Res, A Soltana 7, PL-05400 Otwock, Poland..
Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway.. Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway.. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway.. Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
Defect annealing kinetics in ZnO implanted with Zn substituting elements: Zn interstitials and Li redistribution2019In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 125, no 7, article id 075703Article in journal (Refereed)

It is known that the behavior of residual Li in ion implanted ZnO depends on the preferential localization of the implants, in particular, forming characteristic Li depleted or Li pile-up regions for Zn or O sublattice occupation of the implants due to the corresponding excess generation of Zn and O interstitials in accordance with the so-called "+1 model." However, the present study reveals that conditions for the radiation damage annealing introduce additional complexity into the interpretation of the Li redistribution trends. Specifically, four implants residing predominantly in the Zn-sublattice, but exhibiting different lattice recovery routes, were considered. Analyzing Li redistribution trends in these samples, it is clearly shown that Li behavior depends on the defect annealing kinetics which is a strong function of the implanted fluence and ion species. Thus, Li depleted and Li pile-up regions (or even combinations of the two) were observed and correlated with the defect evolution in the samples. It is discussed how the observed Li redistribution trends can be used for better understanding a thermal evolution of point defects in ZnO and, in particular, energetics and migration properties of Zn interstitials.

• 11.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Sequential 3D Integration - Design Methodologies and Circuit Techniques2019Doctoral thesis, monograph (Other academic)

Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.

As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.

The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.

To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.

Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.

• 12.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper (Refereed)

The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

• 13.
KTH, School of Engineering Sciences (SCI), Applied Physics. Department of Physics, University of Gothenburg.
KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Department of Applied Mathematics, University of Colorado. KTH, School of Engineering Sciences (SCI), Applied Physics. KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. Department of Physics, Shahid Beheshti University, Tehran 19839, Iran. Department of Physics and Astronomy, Uppsala University,. KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
Effect of canted magnetic field on magnetic droplet nucleation boundariesManuscript (preprint) (Other academic)

The influence on magnetic droplet nucleation boundaries by canted magnetic elds are investigated and reported. The nucleation boundary condition, In = αAH + BH + C, is determined at different canted angles (0°< θH<20°) using magnetoresistance (MR) and microwave measurements in nanocontact spintorque oscillators (NC-STOs). As θH increased, the nucleation boundary shifts gradually towards higher In and H. The coefficient B of the nucleation boundary equation also nearly doubled as θH increases. On theother hand, the coefficient αA remained constant for all values of θH. These observations can be explained by considering the drift instability of magnetic droplets and the different tilt behaviour of the Co fixed layer induced by different θH.

• 14.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS).
Wet Transfer of Inkjet Printed Graphene for Microsupercapacitors on Arbitrary Substrates2019In: ACS Applied Energy Materials, ISSN 2574-0962, Vol. 2, no 1, p. 158-163Article in journal (Refereed)

Significant research interest is being devoted to exploiting the properties of graphene but the difficult integration on various substrates limits its use. In this regard, we developed a transfer technique that allows the direct deposition of inkjet printed graphene devices on arbitrary substrates, even 3D objects and living plants. With this technique, we fabricated micro-supercapacitors, which exhibited good adhesion on almost all substrates and no performance degradation induced by the process. Specifically, the microsupercapacitor on an orchid leaf showed an areal capacitance as high as 441 mu F cm(-2) and a volumetric capacitance of 1.16 F cm(-3). This technique can boost the use of graphene in key technological applications, such as self powered epidermal electronics and environmental monitoring systems.

• 15. Dhaou, I. B.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Study and implementation of a secure random number generator for DSRC devices2018In: 2017 9th IEEE-GCC Conference and Exhibition, GCCCE 2017, Institute of Electrical and Electronics Engineers Inc. , 2018Conference paper (Refereed)

This work presents an algorithm to select a low-cost modulus for the implementation of Blum Blum Shub pseudorandom number generator in an FPGA device. Additionally, it elaborates a low-latency architecture for the BBS algorithm suitable for the security service of the IEEE 1609.2 standard. The architecture uses diminished-1 arithmetic and is log2($N$) faster than previously reported implementation using Montgomery multiplier. The architecture is able to implement 224-bit and 256-bit BBS sequences. Synthesis results show that the latencies for the 224-bit and 256-bit BBS are, respectively, 1.12μs and 1.28μs.

• 16.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
Creation of CERID: Challenge, Education, Research, Innovation, and Deployment in the context of smart MicroGrid2019In: IST-Africa 2019 Conference Proceedings / [ed] Paul Cunningham ; Miriam Cunningham, 2019Conference paper (Refereed)

The iGrid project deals with the design and implementation of a solar-powered smart microgrid to supply electric power to small rural communities. In this paper, we discuss the roadmap of the iGrid project, which forms by merging the roadmaps of KIC (knowledge and Innovation Community) and CDE (Challenge-Driven Education). We introduce and explain a five-gear chain as Challenge, Education, Research, Innovation, and Deployment, called CERID, to reach the main goals of this project. We investigate the full chain in the iGrid project, which is established between KTH Royal Institute of Technology (Sweden) and University of Dar es Salam (Tanzania). We introduce the key stakeholders and explain how CERID goals can be accomplished in higher educations and through scientific research. Challenges are discussed, some innovative ideas are introduced and deployment solutions are recommended.

• 17.
KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems.
Scania Technical Centre. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems. AMO GmbH. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. RWTH Aachen University; AMO GmbH. KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems.
Suspended Graphene Membranes with Attached Silicon Proof Masses as Piezoresistive Nanoelectromechanical Systems Accelerometers2019In: Nano letters (Print), ISSN 1530-6984, E-ISSN 1530-6992, Vol. 19, no 10, p. 6788-6799Article in journal (Refereed)

Graphene is an atomically thin material that features unique electrical and mechanical properties, which makes it an extremely promising material for future nanoelectromechanical systems (NEMS). Recently, basic NEMS accelerometer functionality has been demonstrated by utilizing piezoresistive graphene ribbons with suspended silicon proof masses. However, the proposed graphene ribbons have limitations regarding mechanical robustness, manufacturing yield, and the maximum measurement current that can be applied across the ribbons. Here, we report on suspended graphene membranes that are fully clamped at their circumference and have attached silicon proof masses. We demonstrate their utility as piezoresistive NEMS accelerometers, and they are found to be more robust, have longer life span and higher manufacturing yield, can withstand higher measurement currents, and are able to suspend larger silicon proof masses, as compared to the previous graphene ribbon devices. These findings are an important step toward bringing ultraminiaturized piezoresistive graphene NEMS closer toward deployment in emerging applications such as in wearable electronics, biomedical implants, and internet of things (IoT) devices.

• 18.
KTH, School of Electrical Engineering and Computer Science (EECS).
Scania Technical Centre. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS). Faculty of Electrical Engineering and Information Technology, RWTH Aachen University. KTH, School of Electrical Engineering and Computer Science (EECS). Faculty of Electrical Engineering and Information Technology, RWTH Aachen University. KTH, School of Electrical Engineering and Computer Science (EECS).
Suspended graphenemembranes with attached proof masses as piezoresistive NEMS accelerometersIn: Article in journal (Refereed)
• 19.
KTH, School of Electrical Engineering and Computer Science (EECS).
Scania Technical Centre. KTH, School of Electrical Engineering and Computer Science (EECS). KTH, School of Electrical Engineering and Computer Science (EECS). Faculty of Electrical Engineering and Information Technology, RWTH Aachen University. Senseair AB . Silex Microsystems AB. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. Faculty of Electrical Engineering and Information Technology, RWTH Aachen University. KTH, School of Electrical Engineering and Computer Science (EECS).
Graphene beams with suspended masses as electromechanical transducers in ultra-small accelerometersIn: Article in journal (Refereed)
• 20.
KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
Scania Technical Centre. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Senseair AB. AMO GmbH. Senseair AB. KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB, Järfälla, Sweden. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. RWTH Aachen University ; AMO GmbH. KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
Graphene ribbons with suspended masses as transducers in ultra-small nanoelectromechanical accelerometers2019In: Nature Electronics, ISSN 2520-1131, Vol. 2, no 9, p. 394-404Article in journal (Refereed)

Nanoelectromechanical system (NEMS) sensors and actuators could be of use in the development of next-generation mobile, wearable and implantable devices. However, these NEMS devices require transducers that are ultra-small, sensitive and can be fabricated at low cost. Here, we show that suspended double-layer graphene ribbons with attached silicon proof masses can be used as combined spring–mass and piezoresistive transducers. The transducers, which are created using processes that are compatible with large-scale semiconductor manufacturing technologies, can yield NEMS accelerometers that occupy at least two orders of magnitude smaller die area than conventional state-of-the-art silicon accelerometers. With our devices, we also extract the Young’s modulus values of double-layer graphene and show that the graphene ribbons have significant built-in stresses.

• 21.
KTH, School of Electrical Engineering and Computer Science (EECS).
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Faculty of Electrical Engineering and Information Technology, RWTH Aachen University. KTH, School of Electrical Engineering and Computer Science (EECS). Silex Microsystems AB. KTH, School of Electrical Engineering and Computer Science (EECS). Faculty of Electrical Engineering and Information Technology, RWTH Aachen University. KTH, School of Electrical Engineering and Computer Science (EECS).
Manufacturing of Graphene Membranes with Suspended Silicon Proof Masses forMEMS and NEMSIn: Article in journal (Refereed)
• 22.
Univ Engn & Technol Taxila, ACTSENA Res Grp, Telecommun Engn Dept, Punjab 47050, Pakistan.
Univ Engn & Technol Taxila, ACTSENA Res Grp, Telecommun Engn Dept, Punjab 47050, Pakistan.. Polytech Montreal, Dept Elect Engn, Montreal, PQ H3T 1J4, Canada.. Univ Engn & Technol Taxila, ACTSENA Res Grp, Telecommun Engn Dept, Punjab 47050, Pakistan.. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Univ Turku, Dept Informat Technol, TUCS, FIN-20520 Turku, Finland..
Low-Rank Multi-Channel Features for Robust Visual Object Tracking2019In: Symmetry, ISSN 2073-8994, E-ISSN 2073-8994, Vol. 11, no 9, article id 1155Article in journal (Refereed)

Kernel correlation filters (KCF) demonstrate significant potential in visual object tracking by employing robust descriptors. Proper selection of color and texture features can provide robustness against appearance variations. However, the use of multiple descriptors would lead to a considerable feature dimension. In this paper, we propose a novel low-rank descriptor, that provides better precision and success rate in comparison to state-of-the-art trackers. We accomplished this by concatenating the magnitude component of the Overlapped Multi-oriented Tri-scale Local Binary Pattern (OMTLBP), Robustness-Driven Hybrid Descriptor (RDHD), Histogram of Oriented Gradients (HoG), and Color Naming (CN) features. We reduced the rank of our proposed multi-channel feature to diminish the computational complexity. We formulated the Support Vector Machine (SVM) model by utilizing the circulant matrix of our proposed feature vector in the kernel correlation filter. The use of discrete Fourier transform in the iterative learning of SVM reduced the computational complexity of our proposed visual tracking algorithm. Extensive experimental results on Visual Tracker Benchmark dataset show better accuracy in comparison to other state-of-the-art trackers.

• 23.
KTH, School of Engineering Sciences (SCI), Physics, Particle and Astroparticle Physics.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Venus long-life surface package (VL2SP)2017In: Proceedings of the International Astronautical Congress, IAC, International Astronautical Federation, IAF , 2017, p. 3035-3043Conference paper (Refereed)

Measurements in the atmosphere and at the surface of Venus are required to understand fundamental processes of how terrestrial planets evolve and how they work today. While the European Venus community is unified in its support of the EnVision orbiter proposal as the next step in European Venus exploration, many scientific questions also require in situ Venus exploration. We suggest a long-duration lander at Venus, which would be capable of undertaking a seismometry mission, operating in the 460°C surface conditions of Venus. Radar maps have shown Venus to be covered with volcanic and tectonic features, and mounting evidence, including observations from Venus Express, suggests that some of these volcanoes are active today. Assessing Venus' current seismicity, and measuring its interior structure, is essential if we are to establish the geological history of our twin planet, for example to establish whether it ever had a habitable phase with liquid water oceans. Although some constraints on seismic activity can be obtained from orbit, using radar or ionospheric observation, the most productive way to study planetary interiors is through seismometry. Seismometry requires a mission duration of months or (preferably) years. Previous landers have used passive cooling, relying on thermal insulation and the lander's thermal inertia to provide a brief window of time in which to conduct science operations - but this allows mission durations of hours, not months. Proposals relying on silicon electronics require an electronics enclosure cooled to < 200 °C; the insulation, cooling and power system requirements escalate rapidly to require a > 1 ton, > €1bn class mission, such as those studied in the context of NASA flagship missions. However, there are alternatives to silicon electronics: in particular, there have been promising advances in silicon carbide (SiC) electronics capable of operating at temperatures of 500°C. Within the coming decade it will be possible to assemble at least simple circuits using SiC components, sufficient to run a seismometry lander. We are proposing a Venus Long-Lived Surface Package (VL2SP) consisting of power source (RTG), science payload (seismometer and meteorology sensors), and ambient temperature electronics including a telecommunications system weighing < 100 kg. We do not specify how this VL2SP gets to the surface of Venus, but we estimate that an orbiter providing data relay would be essential. This presentation is based on a response sumitted to ESA's Call for New Scientific Ideas in September 2016.

• 24.
KTH, School of Engineering Sciences (SCI), Physics, Particle and Astroparticle Physics.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS).
Working on venus and beyond - SiC electronics for extreme environments2017In: Proceedings of the International Astronautical Congress, IAC, International Astronautical Federation, IAF , 2017, p. 10393-10398Conference paper (Refereed)

Venus is our closest planet, but we know much less about it than about Mars. The main reason for this is the extreme conditions, with a dense atmosphere of mainly CO2 at 92 bar atmosphere and 460 °C temperature at the surface. Only six spacecraft have succeeded to land on Venus and transmit data back to Earth; however none survived for long due to the high temperature. Venera-13 has the record, with 127 minutes at the surface of Venus in 1982. There are many compelling reasons to learn more about the sister planet of Earth, which requires measurements over months rather than minutes on the surface of Venus. Perhaps the single-most challenging task for long-term data taking on the surface of Venus is to build electronics that can operate at temperatures up to 500 °C without cooling. It seems that such technology must be based on wide bandgap semiconductors, such as GaN, SiC or diamond. At KTH, research with SiC devices and integrated circuits has been done for more than 20 years, demonstrating high voltage devices and digital integrated circuit operation at 600 °C. In 2014 the project Working On Venus launched, with funding from Knut and Alice Wallenberg Foundation. The goal is to demonstrate all the electronics for a complete working lander, with all electronics from sensors through amplifiers and analog-to-digital converters to microcontroller with memory and radio, including power supply. The particular sensors the project has in mind are seismic, gas and image sensors. So far, a 200 device level integration has been demonstrated at 500 °C and a 5000+ device level 4 bit microcontroller is being fabricated in an in-house bipolar technology. As for all devices for space, radiation is another concern. SiC integrated circuits have survived exposure to 3 MeV protons with fluences of 1013 cm-2 and gamma rays with doses of 332 Mrad. The dedicated project SUPERHARD IC will study manufacture methods for radiation hardened instrument components that could go beyond Venus, for example for Jovian system exploration. Members of Working on Venus are discussing with scientists seeking opportunities for a Venus Long-Life Surface Package (lander). In 2016 a response was submitted to ESA's Call for New Scientific Ideas.

• 25.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Radiation hardness for silicon oxide and aluminum oxide on 4H-SiC2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, Vol. 924, p. 229-232Conference paper (Refereed)

The radiation hardness of two dielectrics, SiO2 and Al2O3, deposited on low doped, ntype 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011 cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3 can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

• 26.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
A Silicon Carbide 256 Pixel UV Image Sensor Array Operating at 400 degrees C2020In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 8, no 1, p. 116-121Article in journal (Refereed)

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.

• 27.
KTH, School of Electrical Engineering and Computer Science (EECS). Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China.. KTH. Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China.. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
A 3D Tiled Low Power Accelerator for Convolutional Neural Network2018In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Conference paper (Refereed)

It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 x 14 x 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.

• 28. Huang, Letian
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip2018In: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 147-152Conference paper (Refereed)

Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.

• 29.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Silicon Carbide BJT Oscillator Design Using S-Parameters2018In: European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018., 2018Conference paper (Refereed)

Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation isfurther aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, analternative small-signal, S-parameter based design method can be employed directly without goinginto complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 0C) was accessed by on-wafer probing and connectedby RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

• 30.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Silicon carbide BJT oscillator design using S-parameters2019In: Silicon Carbide and Related Materials 2018, Trans Tech Publications Ltd , 2019, p. 674-678Conference paper (Refereed)

Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation is further aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, an alternative small-signal, S-parameter based design method can be employed directly without going into complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 °C) was accessed by on-wafer probing and connected by RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

• 31.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
An Intermediate Frequency Amplifier for High-Temperature Applications (vol 65, pg 1411, 2018)2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 8, p. 3694-3694Article in journal (Refereed)

This correspondence highlights an error in the above-titled paper. The corrected material is presented here.

• 32.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB. University of Arkansas. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. University of Arkansas. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications2019In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed)

This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

• 33.
KTH, School of Electrical Engineering and Computer Science (EECS).
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. University of Arkansas. KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. University of Arkansas. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)

This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

• 34. Inoue, J.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
4H-SIC trench pMOSFETs for high-frequency CMOS inverters2019In: Silicon Carbide and Related Materials 2018, Trans Tech Publications Ltd , 2019, p. 837-840Conference paper (Refereed)

Low-parasitic-capacitance 4H-SiC pMOSFETs were demonstrated for high-frequency CMOS inverters. In these pMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain capacitance) were investigated and low parasitic capacitance was achieved by the trench gate structure.

• 35. Ishii, T.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Suppression of short-channel effects in 4H-SIC trench MOSFETS2019In: Silicon Carbide and Related Materials 2018, Trans Tech Publications Ltd , 2019, p. 613-616Conference paper (Refereed)

Submicron 4H-SiC MOSFETs are attractive for high frequency operation of 4H-SiC integrated circuits. However, the short channel effects, such as threshold voltage lowering, would be induced at the short-channel devices. In this work, short channel effects were investigated with planar and trench 4H-SiC MOSFETs, and the suppression of the short channel effect with the trench structure was achieved.

• 36.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces2019Doctoral thesis, comprehensive summary (Other academic)

Implantable neural interfaces are microelectronic systems, which have the potential to enable a wide range of applications, such as diagnosis and treatment of neurological disorders. These applications depend on neural interfaces to accurately record electrical activity from the surface of the brain, referred to as electrocorticography (ECoG), and provide controlled electrical stimulation as feedback. Since the electrical activity in the brain is caused by ionic currents in neurons, the bridge between living tissue and inorganic electronics is achieved via microelectrode arrays. The conversion of the ionic charge into freely moving electrons creates a built-in electrode potential that is several orders of magnitude larger than the ECoG signal, which increases the dynamic range, resolution, and power consumption requirements of neural interfaces. Also, the small surface area of microelectrodes implies a high-impedance contact, which can attenuate the ECoG signal. Moreover, the applied electrical stimulation can also interfere with the recording and ultimately cause irreversible damages to the electrodes or change their impedance. This thesis is devoted to resolving the challenges of high-resolution recording and monitoring the electrode impedance in implantable neural interfaces.

The first part of this thesis investigates the state-of-the-art neural interfaces for ECoG and identifies their limitations. As a result of the investigation, a high-resolution ADC is proposed and implemented based on a ΔΣ modulator. In order to enhance performance, dynamic biasing and area-efficient switched-capacitor circuits were proposed. The ΔΣ modulator is combined with the analog front-end to provide a complete readout solution for high-resolution ECoG recording. The corresponding chip prototype was fabricated in a 180 nm CMOS process, and the measurement results showed a 14-ENOB over a 300-Hz bandwidth while dissipating 54-μW.

The second part of this thesis expands upon the well-known methods for impedance measurements and proposes an alternative digital method for monitoring the electrode-tissue interface impedance. The proposed method is based on the system identification technique from adaptive digital filtering, and it is compatible with existing circuitry for neural stimulation. The method is simple to implement and performs wide-band measurements. The system identification was first verified through behavioral simulations and then tested with a board-level prototype in order to validate the functionality under real conditions. The measurement results showed successful identification of the electrode-electrolyte and electrode-skin impedance magnitudes.

• 37.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed)

This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

• 38.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation2018Conference paper (Refereed)

A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

• 39.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Impedance Spectroscopy Based on Linear System Identification2019In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, Vol. 13, no 2, p. 396-402Article in journal (Refereed)

Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

• 40.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach2017In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper (Refereed)

Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

• 41.
Univ Engn & Technol, ACTSENA Res Grp, Dept Telecommun Engn, Taxila 47050, Punjab, Pakistan..
Univ Engn & Technol, ACTSENA Res Grp, Dept Telecommun Engn, Taxila 47050, Punjab, Pakistan.. Univ Engn & Technol, ACTSENA Res Grp, Dept Telecommun Engn, Taxila 47050, Punjab, Pakistan.. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. Univ Engn & Technol, ACTSENA Res Grp, Dept Telecommun Engn, Taxila 47050, Punjab, Pakistan.;Royal Inst Technol KTH, Dept Elect Syst, iPack Vinn Excellence Ctr, Stockholm, Sweden.. Middlesex Univ, Sch Engn & Informat Sci, Dept Comp Sci, London, England.. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. Univ Turku, TUCS, Dept Informat Technol, Turku, Finland..
Elliptical slot based polarization insensitive compact and flexible chipless RFID tag2019In: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 29, no 11, article id e21734Article in journal (Refereed)

A miniaturized, polarization insensitive, and fully passive chipless radio frequency identification tag is proposed in this research article. The realized tag is based on slotted elliptical structures in a nested loop fashion with identical lengths and widths of slot resonators. Alteration of data sequence is accomplished by addition and elimination of nested resonators in the geometric structure. The tag is capable to encode 10 bits of data and covers spectral range from 3.6 to 15.6 GHz. The formulated structure demonstrates polarization insensitive characteristic. The data encoding structure is analyzed and optimized for different substrates that are, Rogers RT/duroid/5880, Rogers RT/duroid/5870, and Taconic TLX-0 over the miniaturized footprint of 22.8 x 16 mm(2). The presented tag is robust, novel, compact, and flexible exhibiting a stable response to impinging electromagnetic waves at various angles of incidence.

• 42.
Univ Engn & Technol, Dept Telecommun Engn, ACTSENA Res Grp, Taxila 47050, Punjab, Pakistan.
ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan. ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan. KTH. ACTSENA Research Group, Department of Telecommunication Engineering, University of Engineering and Technology, Taxila, Punjab 47050, Pakistan. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Department of Information Technology, TUCS, University of Turku, Turku, 20520, Finland.
Miniaturized cross-lines rectangular ring-shaped flexible multiband antenna2019In: Applied Computational Electromagnetics Society Journal, ISSN 1054-4887, Vol. 34, no 5, p. 625-630Article in journal (Refereed)

A compact, flexible antenna for wireless applications, i.e., WLAN/WiMAX/Wi-Fi, UMTS2100, C-Band, and DSRC is presented. The quad-band antenna is designed and analyzed in terms of efficiency, gain, radiation pattern, return loss, and VSWR. The optimized design consists of a CPW fed rectangular ring patch with the semi-circular ground. The cross-lines and the semicircular ground is investigated to ascertain the multiband effect. A concept of inset feed mechanism is also interpolated to enhance impedance matching. The framed antenna is examined under the bent condition as well. The reported work is an apt candidate for the proposed applications because of its high efficiency of 95% with a peak gain of 3.22 dBi along with VSWR less than 2. With stable radiation pattern and bandwidth, there is a justified concurrence between simulated and measured results.

• 43.
Fudan Univ, Shanghai, Peoples R China..
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Fudan Univ, Shanghai, Peoples R China.. Fudan Univ, Shanghai, Peoples R China.. Fudan Univ, Shanghai, Peoples R China.. KTH. Fudan Univ, Shanghai, Peoples R China..
TMR Group Coding Method for Optimized SEU and MBU Tolerant Memory Design2018In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Conference paper (Refereed)

This work proposes a fault tolerant memory design using the method of Triple Module Redundancy (TMR) group coding to tolerant the Single-Event Upset (SEU) and Multi-Bit Upset (MBU) influence on memory devices in space environment. The group coding method uses different models to partition and code each word line in memory with Hamming code to achieve best performance. TMR group coding method further increases the capability of self-correction for the errors occurred in parity bits. The evaluation results show that the suggested approach can obtain improved correctness for the memory output with optimized tradeoff between reliability and cost. At 5% error rate, the probability of correct output reaches 70.78% with small cost increment. To achieve 90% reliability, the accuracy improvement is 31.9% compared to TMR with 9% increased area. This solution proposed is evaluated on the memory rich micro-coded processor, but can be further extended to other memory-based processors that need high reliability for the SEU and MBU influence in aerospace applications.

• 44.
Japan.
Japan. Japan. Japan. japan. Japan. japan. KTH, School of Electrical Engineering and Computer Science (EECS). KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
4H-SiC pMOSFETs with al-doped S/D and NbNi silicide ohmic contacts2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 423-427Conference paper (Refereed)

4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200°C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni stack, Nb-Ni Alloy, Ni and Nb/Ti were investigated, and the Nb/Ni stack silicide with the contact resistance of 5.04×10-3 Ωcm2 were applied for the pMOSFETs.

• 45. Kalinga, E. A.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
Active learning through smart grid model site in challenge based learning course2018In: IMSCI 2018 - 12th International Multi-Conference on Society, Cybernetics and Informatics, Proceedings, International Institute of Informatics and Systemics, IIIS , 2018, p. 120-126Conference paper (Refereed)

Smart Grid is a new and growing technology to developing countries. Its implementation and sustainability rely on well trained experts. Sustainability of the smart grid need local experts, hence a project named iGRID: Smart Grid Capacity Development and Enhancement in Tanzania was started. The project is running at the College of Information and Communication Technologies, University of Dar es Salaam. It intends to generate the necessary technical and scientific skills to ensure sustainable implementation of smart grid. iGRID project introduced taught PhD and Masters programs focusing on society, innovation and entrepreneurship in iGRID aspects, as well as to facilitate implementation of automation of monitoring, evaluation, analysis, control and management of electrical power system (smart grid) in order to improve delivery efficiency and to optimize operational costs in the electrical power system in Tanzania. The project made use of Challenge-Based Learning (CBL) methodology to engage students to work together with stakeholders in identifying challenges facing electrical power system in Tanzania. This paper presents the experience of using CBL methodology to achieve active learning to engineering students. The dynamicity of the teaching model, allowed students to acquire skills necessary to solve medium to high tech complex problems. The results build a continuous learning platform for students researching in electrical field.

• 46.
Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA..
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. DIEGM Univ Udine, I-33100 Udine, Italy.. Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA.. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
500 degrees C SiC PWM Integrated Circuit2019In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 34, no 3, p. 1997-2001Article in journal (Refereed)

This letter reports on a high-temperature pulsewidth modulation (PWM) integrated circuit microfabricated in 4H-SiC bipolar process technology that features an on-chip integrated ramp generator. The circuit has been characterized and shown to be operational in a wide temperature range from 25 to 500 degrees C. The operating frequency of the PWM varies in the range of 160 to 210 kHz and the duty cycle varies less than 17% over the entire temperature range. The proposed PWM is suggested to efficiently and reliably control power converters in extreme environments.

• 47.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. university of Turku.
BioSignal Monitoring tool Using Wearable IoT2018In: Proceedings of the 22nd IEEE FRUCT conference,, Jyvaskyla, 2018, p. 4-8Conference paper (Refereed)
• 48.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. Univ Turku, Turku, Finland..
Qassim Univ, Unaizah Coll Engn, Buraydah, Saudi Arabia.;Univ Monastir, Monastir, Tunisia.. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. Univ Dar Es Salaam, Dar Es Salaam, Tanzania.. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. Univ Dar Es Salaam, Dar Es Salaam, Tanzania.. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems. Univ Turku, Turku, Finland..
IoT based Appliances Identification Techniques with Fog Computing for e-Health2019In: IST-Africa 2019 Conference Proceedings / [ed] Paul Cunningham, Miriam Cunningham, IEEE , 2019Conference paper (Refereed)

To improve the living standard of urban communities and to render the healthcare services sustainable and efficient, e-health system is experiencing a paradigm shift. Patients with cognitive discrepancies can be monitored and observed through the analyses of power consumption of home appliances. This paper surveys recent trends in home-based e-health services using metered energy consumption data. It also analyses and summarizes the constant impedance, constant current and constant power (ZIP) approaches for load modelling. The analysis briefly recaptures both non-intrusive and intrusive techniques. The work reports an architecture using IoT technologies for the design of a smart-meter, and fog-computing paradigm for raw processing of energy dataset. Finally, the paper describes the implementation platform based on GirdLAB-D simulation to construct accurate models of household appliances and test the machine-learning algorithm for the detection of abnormal behaviour.

• 49.
KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Univ Turku, Turku, Finland..
Qassim Univ, Buraydah, Saudi Arabia.;Univ Monastir, Monastir, Tunisia.. Univ Turku, Turku, Finland.. Royal Inst Technol, Stockholm, Sweden.;Univ Dar Es Salaam, Dar Es Salaam, Tanzania.. Royal Inst Technol, Stockholm, Sweden.;Univ Dar Es Salaam, Dar Es Salaam, Tanzania.. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Univ Turku, Turku, Finland.. Univ Dar Es Salaam, Dar Es Salaam, Tanzania..
CHALLENGES FOR TEACHING AND LEARNING ACTIVITIES (TLA) AT ENGINEERING EDUCATION2018In: 12TH INTERNATIONAL TECHNOLOGY, EDUCATION AND DEVELOPMENT CONFERENCE (INTED) / [ed] Chova, LG Martinez, AL Torres, IC, IATED-INT ASSOC TECHNOLOGY EDUCATION & DEVELOPMENT , 2018, p. 9093-9098Conference paper (Refereed)

In the knowledge-based society, the legacy education system does not provide the needed skills for creative engineers especially enhancing student innovation and entrepreneurship capacity. Triple-helix model is a concept that aims to bond universities, industry and government in a bid to create innovations. In Europe, integrating research, education, and innovation together in a comprehensive manner has been the major driving force for local and European university development, as example in the form of European Institute Innovation Technology (EIT). At KTH, there are activities that alien the Teaching and Learning Activities (TLA) with different task group with the aim of creating a mutual innovation capacity to contribute solutions for major social challenges. Some of these task groups are Cross-Cultural Faculty Development for Challenge Driven Education, Global learning and digital platform and open innovation platform for learning. The progress and the success are measured by the number of joint student teams and their skills, knowledge development with the follow-up workshop, and the ongoing research and results of the socio-oriented projects. To enhance TLA and the teaching and learning practices, we have developed new curriculums (MSc. and PhD) for our partners to spark innovation and entrepreneurship where the students interact with Open Lab activities. The assessments show that the enrolled students have gained creative skills in dealing with engineering problem and consolidate their knowledge to improve the future TLA and the Intended Learning Outcome (ILO).

• 50.
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. University of Turku, Finland.
University of Turku, Finland. University of Turku, Finland. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. University of Turku, Finland.
Biosignal Feature Extraction Techniques for IoT Healthcare Platform2016In: IEEE Conference on Design and Architectures for Signal and Image Processing (DASIP2016), Rennes, France, 2016Conference paper (Other (popular science, discussion, etc.))

In IoT healthcare platform, a variety of biosignals are acquired from its sensors and appropriate feature extraction techniques are crucial in order to make use of the acquired biosignal data and help the healthcare scientist or bio-engineer to reach at optimal decisions. This work reviews the existing biosignal feature extraction and classification methods for different healthcare applications. Due the enormous amount of different biosignals and since most healthcare applications uses electrocardiogram (ECG), electroencephalogram (EEG), electromyogram (EMG), Electrogastrogram (EGG), we focus the review on feature extractions and classification method for these biosignals. The review also includes a summary of Blood Oxygen Saturation determined by Pulse Oximetry (SpO2), Electrooculography and eye movement (EOG), and Respiration (RSP) signals. Its discussion and analysis focuses on advantages, performance and drawbacks of the techniques.

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