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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density2016In: ECS Transactions, Electrochemical Society, 2016, no 8, p. 615-621Conference paper (Refereed)
    Abstract [en]

    Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 4. Aberg, J
    et al.
    Persson, S
    Hellberg, Per-Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Smith, U
    Ericson, F
    Engstrom, M
    Kaplan, W
    Electrical properties of the TiSi2-Si transition region in contacts: The influence of an interposed layer of Nb2001In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 90, no 5, p. 2380-2388Article in journal (Refereed)
    Abstract [en]

    The influence of an interposed ultrathin Nb layer between Ti and Si on the silicide formation and the electrical contact between the silicide formed and the Si substrate is investigated. The presence of the Nb interlayer results in the formation of ternary alloy (Nb,Ti)Si-2 in the C40 crystallographic structure adjacent to the Si substrate. Depending on the nature of the Si substrates and/or the amount of the initial Nb, the interfacial C40 (Nb,Ti)Si-2 leads, in turn, to either epitaxial growth of a highly faulted metastable C40 TiSi2 or formation of the desired C54 TiSi2 at a lower temperature than needed for it to form in reference samples with Ti deposited directly on Si. On p-type substrates doped to various concentrations, the Nb also leads to a considerably lower specific contact resistivity than that obtained in the reference samples: a twofold to fourfold reduction in the contact resistivity is found using cross-bridge Kelvin structures in combination with two-dimensional numerical simulation. As C40 (Nb,Ti)Si-2 forms at the interface when an interfacial Nb is present, the interface characterized is likely to represent the one between (Nb,Ti)Si-2 and Si. For the reference samples, the interface studied is between TiSi2 and Si.

  • 5.
    Asadollahi, Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zabel, Thomas
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of strained Ge on insulator via room temperature wafer bonding2014In: 2014 15th International Conference on Ultimate Integration on Silicon, ULIS 2014, IEEE Computer Society, 2014, p. 81-84Conference paper (Refereed)
    Abstract [en]

    This work describes a strained germanium on insulator (GeOI) fabrication process using wafer bonding and etch-back techniques. The strained Ge layer is fabricated epitaxially using reduced pressure chemical vapor deposition (RPCVD). The strained Ge is grown pseudomorphic on top of a partially relaxed Si 0.66Ge0.34 layer. Wafer bonding is performed at room temperature without post-anneal processes and the etch-back steps are performed without mechanical grinding and chemical mechanical polishing (CMP).

  • 6.
    Asadollahi, Ali
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zabel, Thomas
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Roupillard, Gabriel
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of relaxed germanium on insulator via room temperature wafer bonding2014In: ECS Transactions: Volume 64, Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, Electrochemical Society, 2014, no 6, p. 533-541Conference paper (Refereed)
    Abstract [en]

    We report on the fabrication of, high quality, monocrystalline relaxed Germanium with ultra-low roughness on insulator (GeOI) using low-temperature direct wafer bonding. We observe that a two-step epitaxially grown germanium film fabricated on silicon by reduced pressure chemical vapor deposition can be directly bonded to a SiO2 layer using a thin Al2O3 as bonding mediator. After removing the donor substrate silicon the germanium layer exhibits a complete relaxation without degradation in crystalline quality and no stress in the film. . The results suggest that the fabricated high quality GeOI substrate is a suitable platform for high performance device applications.

  • 7. Bolten, J.
    et al.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ternon, C.
    Serre, P.
    Fabrication of Nanowires2014In: Beyond CMOS Nanodevices 1, Wiley Blackwell , 2014, p. 5-23Chapter in book (Other academic)
    Abstract [en]

    Several fabrication processes of silicon nanowires have been developed in the research community. They can be divided into bottom-up or top-down approaches. This chapter describes top-down fabrication of silicon nanowires using electron beam lithography (EBL), which combined with optical lithography can be a viable approach if not too many silicon nanowires need to be patterned on a wafer. It also describes the sidewall transfer lithography (STL) technique using I-line stepper lithography to pattern a vast amount of silicon nanowires on a silicon wafer. In addition the chapter examines how bottom-up Si nanowires synthesized by vapor-liquid-solid (VLS)-chemical vapor deposition (CVD) can be assembled at low cost in an efficient way for further use as a sensing material. Among the solution-based assembly methods for the nanostructured network (nanonet) fabrication, the vacuum filtration method is highly simple, versatile, low cost and scalable to large areas.

  • 8.
    Chaourani, Panagiotis
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Onet, Raul
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Enabling Area Efficient RF ICs through Monolithic 3D Integration2017In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 610-613, article id 7927059Conference paper (Refereed)
    Abstract [en]

    The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

  • 9.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines2019In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed)
    Abstract [en]

    Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

  • 10.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Stathis, Dimitrios
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper (Refereed)
    Abstract [en]

    The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

  • 11.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Valerio, Sven
    KTH, School of Information and Communication Technology (ICT).
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O2013In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 160, no 11, p. D538-D542Article in journal (Refereed)
    Abstract [en]

    A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic precursor eliminates the need for a strong oxidizing agent (such as O-3) and provides a high deposition rate of similar to 1.5 angstrom/cycle. A thorough characterization of the process has been performed, identifying true ALD-type film growth in the temperature range 200-300 degrees C. The ALD process has been further investigated by extensive physical and electrical characterization of the deposited films in terms of-composition, crystalline phase, surface roughness and extraction of the dielectric constant. The films were found to be oxygen-rich Tm2O3, with low carbon impurity content at low deposition temperature and after annealing at 600 degrees C. The developed process produced polycrystalline films, with a surface roughness <1 nm RMS. Integration in MOS capacitors demonstrated well-behaved CV curves after annealing at 600 degrees C, with a relative dielectric constant of similar to 16.

  • 12.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs2013In: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS), IEEE , 2013, p. 122-125Conference paper (Refereed)
    Abstract [en]

    The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.

  • 13.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 20-25Article in journal (Refereed)
    Abstract [en]

    This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.

  • 14.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks2012In: 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012, IEEE , 2012, p. 105-108Conference paper (Refereed)
    Abstract [en]

    This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 A) while preserving the electrical quality of the stack.

  • 15.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Thulium silicate interfacial layer for scalable high-k/metal gate stacks2013In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 10, p. 3271-3276Article in journal (Refereed)
    Abstract [en]

    Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.

  • 16.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effective Workfunction Control in TmSiO/HfO2 high-k/metal gate stacks2014In: ULIS 2014: 2014 15th International Conference on Ultimate Integration on Silicon, 2014, p. 69-72Conference paper (Refereed)
    Abstract [en]

    Integration of high-k interfacial layers in CMOS technology has been proposed to overcome the scaling limitations of the SiOx/HfO2 dielectric stack. Candidate high-k interfacial layers have to be compatible with strict requirements in terms of EOT, inversion layer mobility, threshold voltage control and device reliability. We have previously demonstrated a CMOS-compatible process for integration of thulium silicate (TmSiO) as interfacial layer, providing advantages in terms of EOT and channel mobility. This work demonstrates the compatibility of the TmSiO/HfO2 stack with the threshold voltage control techniques commonly employed in gate-last and gate-first integration schemes, namely the use of a dual-metal process and the integration of dielectric capping layers. We show that the flatband voltage can be set from -1V to +0.5V by proper choice of gate metal, while a shift of 150-400 mV is achievable by means of integration of Al2O3 or La2O3 capping layers.

  • 17.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Enhanced channel mobility at sub-nm EOT by integration of a TmSiO interfacial layer in HfO2/TiN high-k/metal gate MOSFETs2015In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 3, no 5, p. 397-404, article id 7120903Article in journal (Refereed)
    Abstract [en]

    Integration of a high-k interfacial layer (IL) is considered the leading technological solution to extend the scalability of Hf-based high-k/metal gate CMOS technology. We have previously shown that thulium silicate (TmSiO) IL can provide excellent electrical characteristics and enhanced channel mobility at sub-nm EOT. This paper presents a detailed analysis of channel mobility in TmSiO/HfO<inf>2</inf>/TiN MOSFETs, obtained through measurements at varying temperature and under constant voltage stress. We show experimentally for the first time that integration of a high-k IL can benefit mobility by attenuating remote phonon scattering. Specifically, integration of TmSiO results in attenuated remote phonon scattering compared to reference SiO<inf>x</inf>/HfO<inf>2</inf> dielectric stacks having the same EOT, whereas it has no significant influence on remote Coulomb scattering.

  • 18.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Enhanced channel mobility by integration of sub-nm-EOT TmSiO/HfO2/TiNhigh-k/metal gate MOSFETsManuscript (preprint) (Other academic)
  • 19.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    (Invited) TmSiO As a CMOS-Compatible High-k Dielectric2016In: SILICON COMPATIBLE MATERIALS, PROCESSES, AND TECHNOLOGIES FOR ADVANCED INTEGRATED CIRCUITS AND EMERGING APPLICATIONS 6 / [ed] Roozeboom, F Narayanan, V Kakushima, K Timans, PJ Gusev, EP Karim, Z DeGendt, S, Electrochemical Society, 2016, no 4, p. 79-89Conference paper (Refereed)
    Abstract [en]

    Novel materials are being aggressively researched for integration in high-k/metal gate CMOS technology, as innovations in the gate stacks are necessary to sustain scaling toward the end of the roadmap. In this paper, we discuss thulium silicate as a candidate dielectric for integration as interfacial layer, focusing on compatibility with the requirements in terms of both process integration and effects on electrical device characteristics. In particular, we demonstrate that thulium silicate provides advantages over conventional chemical oxide interfacial layers in terms of scalability and channel mobility.

  • 20.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Mobility enhancement by integration of TmSiO IL in 0.65nm EOT high-k/metal gate MOSFETs2013In: 2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC), IEEE Computer Society, 2013, p. 155-158Conference paper (Refereed)
    Abstract [en]

    Thulium silicate has been demonstrated as a possible replacement of chemical oxide interfacial layers for extended scalability of high-k/metal gate MOSFETs. In this work, thulium silicate was integrated in a scaled HfO 2/TiN gate-last CMOS process, achieving an EOT of 0.65 nm and well-behaved and reproducible IV and CV characteristics with almost symmetric threshold voltages, low subthreshold slope and low hysteresis. Comparison with reference devices employing chemical oxide interfacial layers shows improvement in terms of leakage current density and electron and hole mobility. Specifically, channel mobility is enhanced by 20% in N-MOSFETs and by 15% in P-MOSFETs at an inversion charge density of 1013cm-2, yielding values of 180 and 75 cm2/Vs at EOT = 0.65 and 0.8 nm respectively.

  • 21.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Threshold voltage control in TmSiO/HfO2 high-k/metal gate MOSFETs2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 108, p. 24-29Article in journal (Refereed)
    Abstract [en]

    High-k interfacial layers have been proposed as a way to extend the scalability of Hf-based high-k/metal gate CMOS technology, which is currently limited by strong degradations in threshold voltage control, channel mobility and device reliability when the chemical oxide (SiOx) interfacial layer is scaled below 0.4 nm. We have previously demonstrated that thulium silicate (TmSiO) is a promising candidate as a high-k interfacial layer, providing competitive advantages in terms of EOT scalability and channel mobility. In this work, the effect of the TmSiO interfacial layer on threshold voltage control is evaluated, showing that the TmSiO/HfO2 dielectric stack is compatible with threshold voltage control techniques commonly used with SiOx/HfO2 stacks. Specifically, we show that the flatband voltage can be set in the range -1 V to +0.5 V by the choice of gate metal and that the effective workfunction of the stack is properly controlled by the metal workfunction in a gate-last process flow. Compatibility with a gate-first approach is also demonstrated, showing that integration of La2O3 and Al2O3 capping layers can induce a flatband voltage shift of at least 150 mV. Finally, the effect of the annealing conditions on flatband voltage is investigated, finding that the duration of the final forming gas anneal can be used as a further process knob to tune the threshold voltage. The evaluation performed on MOS capacitors is confirmed by the fabrication of TmSiO/HfO2/TiN MOSFETs achieving near-symmetric threshold voltages at sub-nm EOT.

  • 22. Donetti, L.
    et al.
    Gamiz, F.
    Thomas, S.
    Whall, T. E.
    Leadley, D. R.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hole effective mass in silicon inversion layers with different substrate orientations and channel directions2011In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 110, no 6, p. 063711-Article in journal (Refereed)
    Abstract [en]

    We explore the possibility to define an effective mass parameter to describe hole transport in inversion layers in bulk MOSFETs and silicon-on-insulator devices. To do so, we employ an accurate and computationally efficient self-consistent simulator based on the six-band k . p model. The valence band structure is computed for different substrate orientations and silicon layer thicknesses and is then characterized through the calculation of different effective masses taking account of the channel direction. The effective masses for quantization and density of states are extracted from the computed energy levels and subband populations, respectively. For the transport mass, a weighted averaging procedure is introduced and justified by comparing the results with hole mobility from experiments and simulations.

  • 23. Donetti, L.
    et al.
    Gámiz, F.
    Thomas, S. M.
    Whall, T. E.
    Leadley, D. R.
    Hellström, Per -Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    On the effective mass of holes in inversion layers2011In: International Conference on Ultimate Integration on Silicon, 2011, p. 50-53Conference paper (Refereed)
    Abstract [en]

    We study hole inversion layers in bulk MOSFETs and silicon-on-insulator devices employing a self-consistent simulator based on the six-band kp model. Valence Band structure is computed for different device orientations and silicon layer thicknesses, and then it is characterized through the calculation of different effective masses.

  • 24. Driussi, F.
    et al.
    Esseni, D.
    Selmi, L.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Grasby, T. J.
    Leadley, D. R.
    Mescot, X.
    On the electron mobility enhancement in biaxially strained Si MOSFETs2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 4, p. 498-505Article in journal (Refereed)
    Abstract [en]

    This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.

  • 25.
    Edström, Kristina
    et al.
    KTH, School of Education and Communication in Engineering Science (ECE), Learning.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT).
    Improving student learning in STEM education: Promoting a deep approach to problem-solvingManuscript (preprint) (Other academic)
    Abstract [en]

    This paper addresses educational practice related to problem-solving within STEM education. A conceptual framework is shaped by conceptualising problem-solving first as an educational aim, then as a learning activity. Five principles for purposeful active learning are derived. Through this theoretical lens we investigate an active learning method called student-led recitations. In this activity students are randomly selected to present solutions to given problems, requiring them to solve the problems in advance and prepare for presenting their solutions. Drawing on the conceptual framework and informed by course results and qualitative data in the form of student interviews and teacher experiences, we analyse the teaching method. One conclusion is to challenge recitations based on teacher demonstrations of problem-solving. We suggest that student-led recitations are a cost-effective intervention, improving learning while affording more stimulating roles to both students and teachers. 

  • 26.
    Garidis, Konstantinos
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration2015In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 165-168Conference paper (Refereed)
    Abstract [en]

    We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

  • 27. Grahn, J.V
    et al.
    Hellberg, P.-E.
    Olsson, E
    Effect of growth temperature on the properties of evaporated tantalum pentoxide thin films on silicon deposited using oxygen radicals1998In: Journal of Applied Physics, Vol. 84, p. 1632-1642Article in journal (Refereed)
  • 28.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Luo, Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 5, p. 541-543Article in journal (Refereed)
    Abstract [en]

    Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (<= 700 degrees C) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (t(si) = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 (.) 10(15) and 5. 10(15) cm(-2). Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.

  • 29.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of dopant segregated Schottky barrier source/drain contacts2009In: ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON / [ed] Mantl S, Lemme M, Schubert J, Albrecht W, NEW YORK: IEEE , 2009, p. 73-76Conference paper (Refereed)
    Abstract [en]

    In this paper, the gate-voltage dependent source/drain (S/D) resistance (R-SD) in dopant segregated (DS) Schottky barrier (SB) junctions is examined by experiment and simulation. The focus is placed on fully depleted UTB-SOI MOSFETs featuring PtSi S/D with As-DS realized at low temperatures. When modeling SB-S/D with DS, it is challenging to determine if the performance enhancement observed is induced by a highly doped shallow layer in Si or by an interfacial dipole causing SB height lowering. The simulation reveals that the gate-voltage dependence of R-SD is stronger for the dipole effect. For the SB-MOSFETs with DS-S/D examined in this work, the simulation gives an excellent fit to the measured data when SBH lowering is combined with high concentration shallow doping.

  • 30.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM2008In: PROCEEDINGS OF THE 17TH INTERNATIONAL VACUUM CONGRESS/13TH INTERNATIONAL CONFERENCE ON SURFACE SCIENCE/INTERNATIONAL CONFERENCE ON NANOSCIENCE AND TECHNOLOGY / [ed] Johansson LSO, Andersen JN, Gothelid M, Helmersson U, Montelius L, Rubel M, Setina J, Wernersson LE, Bristol: IOP PUBLISHING LTD , 2008, Vol. 100Conference paper (Refereed)
    Abstract [en]

    In this paper the effect of the commonly used HBr/Cl-2 chemistry for dry etching on the line-edge roughness (LER) of photoresist patterned single crystalline Si (sc-Si), polycrystalline Si (poly-Si) and poly-Si0.2Ge0.8 sidewalls was characterized. Measurements were done by means of atomic force microscopy in combination with an elaborated sample preparation technique that allowed the LER at different depths of the sidewall to be measured. Samples were patterned by I-line lithography and etching was performed at an RF power of 200 W using HBr/Cl-2 (30/10 sccm) plasma. For sc-Si the photoresist and Si sidewalls had an LER of 0.8-1.4 nm and 1.5-2 nm, respectively. For poly-Si and poly-SiGe the photoresist sidewall roughness was, respectively, increased to 1.5-3 nm and 2-3.5 nm due to light scattering from the rough surface of the polycrystalline materials. The poly-Si film had a sidewall roughness of 3-4 nm. Poly-SiGe sidewall exhibited larger roughness with an LER of 5-12 nm which was not transferred from the photoresist. The results show that for sc-Si and poly-Si the sidewall roughness mainly originates from the photoresist process and little additional roughening is caused by the HBr/Cl-2 etching. However, for poly-Si0.2Ge0.8 the LER is considerably increased from that of the photoresist indicating that the HBr/Cl-2 etching is the main contributor to the LER.

  • 31.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Effect of Be segregation on NiSi/Si Schottky barrier heights2011In: Solid-State Device Research Conference (ESSDERC), 2011Conference paper (Refereed)
    Abstract [en]

    The effect of Be segregation on the Schottky barrier heights (SBH) of NiSi/Si is studied. Many elements have been shown to modulate the SBH of NiSi. However, group II elements have, to our knowledge, not been investigated before. Be is a double acceptor in Si, making it interesting for SBH modulation towards the valence band. The results show that Be implantation did not change the silicidation process. The SBH modulation was found to be strongly dependent on the silicidation temperature, with a minimum barrier to the valence band Φbp=0.28±0.02 eV, for diodes formed at 600 °C. SIMS analysis show the Be dose left at the interface is very low. With such a low dose, modulation cannot be caused by an interface dipole. However, the results can be explained assuming a thin (~4-5 nm) layer of activated Be close to the interface.

  • 32.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Error Propagation in Contact Resistivity Extraction Using Cross-Bridge Kelvin Resistors2012In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, no 6, p. 1585-1591Article in journal (Refereed)
    Abstract [en]

    The cross-bridge Kelvin resistor is a commonly used method for measuring contact resistivity (rho(c)). For low rho(c), the measurement has to be corrected for systematic error using measurements of contact resistance, semiconductor sheet resistance, and device dimensions. However, it is not straightforward to estimate the propagation of random measurement error in the measured quantities on the extracted rho(c). In this paper, a method is presented to quantify the effect of random measurement error on the accuracy of rho(c) extraction. This is accomplished by generalized error propagation curves that show the error in rho(c) caused by random measurement errors. Analysis shows that when the intrinsic resistance of the contact is smaller than the semiconductor sheet resistance, it becomes important to consider random error propagation. Comparison of literature data, where rho(c) < 5.10(-8) Omega.cm(2) has been reported, shows that care should be taken since, even assuming precise electrical data, a 1% error in the measurement of device dimensions can lead to up to similar to 50% error in the estimation of rho(c).

  • 33.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Palestri, P.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Selmi, L.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simulation of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo model2013In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 79, p. 172-178Article in journal (Refereed)
    Abstract [en]

    We present a simple and efficient approach to implement Schottky barrier contacts in a Multi-subband Monte Carlo simulator by using the subband smoothening technique to mimic tunneling at the Schottky junction. In the absence of scattering, simulation results for Schottky barrier MOSFETs are in agreement with ballistic Non-Equilibrium Green's Functions calculations. We then include the most relevant scattering mechanisms, and apply the model to the study of double gate Schottky barrier MOSFETs representative of the ITRS 2015 high performance device. Results show that a Schottky barrier height of less than approximately 0.15 eV is required to outperform the doped source/drain structure.

  • 34.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Palestri, Pierpaolo
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Selmi, Luca
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Investigation of the performance of low Schottky barrier MOSFETs using an improved Multi-subband Monte Carlo modelArticle in journal (Other academic)
  • 35.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Palestri, Pierpaolo
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Selmi, Luca
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Multi-subband Monte Carlo simulation of fully-depleted silicon-on-insulator Schottky barrier MOSFETs2010In: 11th International Conference on Ultimate Integration of Silicon (ULIS), 2010, 2010Conference paper (Refereed)
  • 36. Hellberg, P.-E
    et al.
    Gagnor, A
    Zhang, S.-L.
    Petersson, C.S.
    Boron-doped polycrystalline SixGe1-x films: Dopant activation and solid solubility1997In: Journal of the Electrochemical Society, Vol. 144, p. 3968-3973Article in journal (Refereed)
  • 37. Hellberg, P.-E.
    et al.
    Zhang, S.-L.
    d'Heurle, F.M.
    Petersson, C.S.
    Oxidation of silicon-germanium alloys. I. An experimental study1997In: Journal of Applied Physics, Vol. 82, p. 5773-5778Article in journal (Refereed)
  • 38. Hellberg, P.-E.
    et al.
    Zhang, S.-L.
    d'Heurle, F.M
    Petersson, C.S.
    Oxidation of silicon-germanium alloys. II. A mathematical model1997In: Journal of Applied Physics, Vol. 82, p. 5779-5787Article in journal (Refereed)
  • 39. Hellberg, P.-E.
    et al.
    Zhang, S.-L.
    Petersson, C.S.
    Work function of Boron-Doped polycrystalline SixGe1-x films1997In: IEEE Electron Device Letters, Vol. 18, p. 456-458Article in journal (Refereed)
  • 40. Hellberg, P.-E.
    et al.
    Zhang, S.-L
    Radamsson, H.H.
    Kaplan, W
    Threshold voltage control for PMOSFETs using an undoped epitaxial Si channel and a p+-SixGe1-x gate2000In: Solid-State Electronics, Vol. 44, p. 2085-2088Article in journal (Refereed)
  • 41.
    Hellberg, Per-Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zhang, Shi-Li
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, HH
    Kaplan, W
    Threshold voltage control for PMOSFETs using an undoped epitaxial Si channel and a p(+)-SixGe1-x gate2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 11, p. 2085-2088Article in journal (Refereed)
    Abstract [en]

    This paper examines experimentally the performance of PMOSFETs with an undoped epitaxial Si channel in combination with a p(+)-SixGe1-x gate electrode. The channel doping profiles were made using shallow As-implantation followed by selective epitaxy of undoped Si to different thicknesses of 40, 80 and 120 nm. The p(+)-SixGe1-x gate with different values of x was used to tailor the threshold voltage. The transconductance and saturation current were found to increase and the threshold voltage to decrease with increasing thickness of the undoped Si channel for the same gate material. Increasing Ge content in the p(+)-SixGe1-x gate resulted in an increased threshold voltage. Compared to the p(+)-Si gate, the threshold voltage was increased by 0.15 and 0.35 V with a p(+)-Si0.79Ge0.21 and p(+)-Si0.53Ge0.47 gate, respectively, independently of the Si channel thickness. Therefore, the use of a p(+)-SixGe1-x gate introduces an extra degree of freedom when designing the channel for high performance PMOSFETs.

  • 42.
    Hellström, Per-Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interfacial layer engineering using thulium silicate/germanate for high-k/metal gate MOSFETs2014In: ECS Transactions: Cancun, Mexico, October 5 – 9, 2014 2014 ECS and SMEQ Joint International Meeting, Electrochemical Society, 2014, no 6, p. 249-260Conference paper (Refereed)
    Abstract [en]

    Thulium silicate (TmSiO) is considered as high-k interfacial layer in high-k/metal gate stacks, providing advantages in terms of EOT scalability and enhanced inversion layer mobility. In this work, we show that optimized annealing conditions for the TmSiO/HfO2/TiN gate stack provide competitive gate leakage current density, symmetric nFET and pFET threshold voltages, while retaining compatibility with CMOS processing and ∼20% higher electron and hole mobility than literature data on optimized SiOx/HfO2 stacks at EOT as low as 0.65 nm. We also evaluate cleaning procedures to facilitate thulium germanate formation on Ge channel materials and found that HF cleaning optimization is needed to allow thulium germanate formation while keeping surface roughness at an acceptable level.

  • 43.
    Hellström, Per-Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Edholm, J.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Olsen, S.
    O'Neill, A.
    Lyutovich, K.
    Oehme, M.
    Kasper, E.
    Strained-Si NMOSFETs on thin 200 nm virtual substrates2005Conference paper (Refereed)
  • 44.
    Hellström, Per-Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of Silicon Nanowires with CMOS2014In: Beyond CMOS Nanodevices 1, Wiley Blackwell , 2014, p. 65-72Chapter in book (Other academic)
    Abstract [en]

    Silicon nanowires exhibit attractive characteristics that have motivated their use as the sensor element in a biochemical sensor system. An integrated silicon nanowire and complementary metal-oxide-semiconductor (CMOS) circuit chip would allow more design freedom with respect to interaction with the full biochemical sensor system, including interaction with the electrolyte solution. The CMOS fabrication process is divided into two parts, called the front-end-of-line (FEOL) and back-end-of-line (BEOL) processing. A CMOS process that allows the integration of silicon nanowires, as described in this chapter offers a vast amount of design opportunities to enhance the performance of the silicon nanowire-based sensor. The chapter describes a sensor design that allows measurement of the conductance variations of biosensitive silicon nanowires in a serial manner by using on-chip integrated CMOS circuitry. Integration of silicon nanowires can also be achieved by defining the silicon nanowires in the silicon layer of a SOI wafer.

  • 45.
    Henkel, Christoph
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bethge, O.
    Stöger-Pollach, M.
    Bertagnolli, E.
    Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks2011In: European Solid-State Device Res. Conf., 2011, p. 75-78Conference paper (Refereed)
    Abstract [en]

    The current work is discussing the surface passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition for use in Ge-based MOSFET devices. The improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing agencies in presence of thin Pt cap layers are investigated. The results suggest the formation of thin intermixed La xGeyOz interfacial layers with thicknesses controllable by oxidation time. An additional reduction treatment further improves the electrical properties of the gate dielectrics in contact to the Ge substrate. The scaling potential of the respective layered gate dielectrics used in MOS-based device structures is discussed. As a result low interface trap densities of the ALD deposited La2O3/ZrO2 layers on (100) Ge down to 3·1011 eV-1 cm -2 are demonstrated. A trade-off between improved interface trap density and equivalent oxide thickness is found.

  • 46.
    Henkel, Christoph
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Stoeger-Pollach, Michael
    Bethge, Ole
    Bertagnolli, Emmerich
    Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, p. 7-12Article in journal (Refereed)
    Abstract [en]

    The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3 x 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k LaxGeyOz, layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

  • 47.
    Hou, Shuoben
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    4H-SiC PIN diode as high temperature multifunction sensor2017In: 11th European Conference on Silicon Carbide and Related Materials, ECSCRM 2016, Trans Tech Publications Ltd , 2017, p. 630-633Conference paper (Refereed)
    Abstract [en]

    An in-house fabricated 4H-SiC PIN diode that has both optical sensing and temperature sensing functions from room temperature (RT) to 550 ºC is presented. The two sensing functions can be simply converted from one to the other by switching the bias voltage on the diode. The optical responsivity of the diode at 365 nm is 31.8 mA/W at 550 ºC. The temperature sensitivity of the diode is 2.7 mV/ºC at the forward current of 1 μA.

  • 48.
    Hou, Shuoben
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    550 degrees C 4H-SiC p-i-n Photodiode Array With Two-Layer Metallization2016In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 37, no 12, p. 1594-1596Article in journal (Refereed)
    Abstract [en]

    The p-i-n ultraviolet (UV) photodiodes based on 4H-SiC have been fabricated and characterized from room temperature (RT) to 550 degrees C. Due to bandgap narrowing at higher temperatures, the photocurrent of the photodiode increases by 9 times at 365 nm and reduces by 2.6 times at 275 nm from RT to 550 degrees C. Moreover, a 4H-SiC p-i-n photodiode array has been fabricated. Each column and row of the array is separately connected by two-layer metallization.

  • 49.
    Hou, Shuoben
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    A 4H-SiC BJT as a Switch for On-Chip Integrated UV Photodiode2019In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 40, no 1, p. 51-54Article in journal (Refereed)
    Abstract [en]

    This letter presents the design, fabrication, and characterization of a 4H-SiC n-p-n bipolar junction transistor as a switch controlling an on-chip integrated p-i-n photodiode. The transistor and photodiode share the same epitaxial layers and topside contacts for each terminal. By connecting the collector of the transistor and the anode of the photodiode, the photo current from the photodiode is switched off at low base voltage (cutoff region of the transistor) and switched on at high base voltage (saturation region of the transistor). The transfer voltage of the circuit decreases as the ambient temperature increases (2 mV/degrees C). Both the on-state and off-state current of the circuit have a positive temperature coefficient and the on/off ratio is >80 at temperature ranged from 25 degrees C to 400 degrees C. It is proposed that the on/off ratio can be increased by similar to 1000 times by adding a light blocking layer on the transistor to reduce light induced off-state current in the circuit.

  • 50.
    Hou, Shuoben
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Scaling and modeling of high temperature 4H-SiC p-i-n photodiodes2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 139-145, article id 8240922Article in journal (Refereed)
    Abstract [en]

    4H-SiC p-i-n photodiodes with various mesa areas (40,000μm2, 2500μm2, 1600μm2, and 400μm2) have been fabricated. Both C-V and I-V characteristics of the photodiodes have been measured at room temperature, 200 °C, 400 °C, and 500 °C. The capacitance and photo current (at 365 nm) of the photodiodes are directly proportional to the area. However, the dark current density increases as the device is scaled down due to the perimeter surface recombination effect. The photo to dark current ratio at the full depletion voltage of the intrinsic layer (-2.7 V) of the photodiode at 500 °C decreases 7 times as the size of the photodiode scales down 100 times. The static and dynamic behavior of the photodiodes are modeled with SPICE parameters at the four temperatures.

123 1 - 50 of 131
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