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  • 1.
    Andersson, Helene
    et al.
    KTH, Superseded Departments, Biotechnology.
    van der Wijngaart, Wouter
    KTH, Superseded Departments, Signals, Sensors and Systems.
    Griss, P.
    Niklaus, Frank
    KTH, Superseded Departments, Signals, Sensors and Systems.
    Stemme, Göran
    KTH, Superseded Departments, Signals, Sensors and Systems.
    Hydrophobic valves of plasma deposited octafluorocyclobutane in DRIE channels2001In: Sensors and actuators. B, Chemical, ISSN 0925-4005, E-ISSN 1873-3077, Vol. 75, no 1-2, p. 136-141Article in journal (Refereed)
    Abstract [en]

    The suitability of using octafluorocyclobutane (C4F8) patches as hydrophobic valves in microfluidic biochemical applications has been shown. A technique has been developed to generate lithographically defined C4F8 hydrophobic patches in deep reactive ion-etched silicon channels. Some of the advantages of this process are that no specific cleaning of the substrate is required, C4F8 is deposited on the sidewalls and the bottom of the channels, a standard photoresist mask can be used to define the patches, and that it is a fast and convenient dry chemical process performed by a standard inductively coupled plasma etcher using the Bosch process. Different patch lengths (200-1000 mum) of C4F8 were deposited in 50 mum wide channels to evaluate which size is most suitable for microfluidic biochemical applications. The valve function of the hydrophobic patches was tested for the following liquids: DD water, acetone, propanol, bead solution and a mixture used for pyrosequencing of DNA. Patch lengths of 200 mum of C4F8 successfully stopped each solution for at least 20 consecutive times. The C4F8 film resists water for at least 5 h. The hydrophobic valve also resists very high concentrations (25%) of surfactants (Tween 80). C4F8 shows a much higher resistance towards water and surface active solutions than previous hydrophobic patches. However, 50% Tween 80 was not stopped at all by the hydrophobic patch. An applied pressure of 760 Pa at the inlet was needed for water to over-run the hydrophobic patch.

  • 2.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Hermetic integration of liquids using high-speed stud bump bonding for cavity sealing at the wafer level2012In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 4, p. 045021-Article in journal (Refereed)
    Abstract [en]

    This paper reports a novel room-temperature hermetic liquid sealing process where the access ports of liquid-filled cavities are sealed with wire-bonded stud bumps. This process enables liquids to be integrated at the fabrication stage. Evaluation cavities were manufactured and used to investigate the mechanical and hermetic properties of the seals. Measurements on the successfully sealed structures show a helium leak rate of better than 10 (10) mbarL s (1), in addition to a zero liquid loss over two months during storage near boiling temperature. The bond strength of the plugs was similar to standard wire bonds on flat surfaces.

  • 3.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Wafer-Level Vacuum Sealing by Coining of Wire Bonded Gold Bumps2013In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 22, no 6, p. 1347-1353Article in journal (Refereed)
    Abstract [en]

    This paper reports on the investigation of a novel room-temperature vacuum sealing method based on compressing wire bonded gold bumps which are placed to partially overlap the access ports into the cavity. The bump compression, which is done under vacuum, causes a material flow into the access ports, thereby hermetically sealing a vacuum inside the cavities. The sealed cavity pressure was measured by residual gas analysis to 8x10(-4) mbar two weeks after sealing. The residual gas content was found to be mainly argon, which indicates the source as outgassing inside the cavity and no measurable external leak. The seals are found to be mechanically robust and easily implemented by the use of standard commercial tools and processes.

  • 4.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Fischer, Andreas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Hermetic integration of liquids in MEMS by room temperature, high-speed plugging of liquid-filled cavities at wafer level2011In: Proceedings IEEE International Conference on Micro Electro Mechanical Systems (MEMS), IEEE , 2011, p. 356-359Conference paper (Other academic)
    Abstract [en]

    This paper reports a novel room temperature hermetic liquid sealing process based on wire bonded "plugs" over the access ports of liquid-filled cavities. The method enables liquids to be integrated already at the fabrication stage. Test vehicles were manufactured and used to investigate the mechanical and hermetic properties of the seals. A helium leak rate of better than 1E-10 mbarL/s was measured on the successfully sealed structures. The bond strength of the "plugs" were similar to standard wire bonds on flat surfaces.

  • 5.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Fischer, Andreas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Room-temperature wafer-level vacuum sealing by compression of high-speed wire bonded gold bumps2011In: Proceedings IEEE International Conference on Solid-State Sensors, Actuators, and Microsystems (Transducers), IEEE , 2011, p. 1360-1363Conference paper (Other academic)
    Abstract [en]

    This paper reports experimental results of a novel room temperature vacuum sealing process based on compressing wire bonded gold “bumps”, causing a material flow into the access ports of vacuum-cavities. The leak rate out of manufactured cavities was measured over 5 days and evaluated to less than the detection limit, 6×10-12 mbarL/s, per sealed port. The cavities have been sealed at a vacuum level below 10 mbar. The method enables sealing of vacuum cavities at room temperature using standard commercial tools and processes.

  • 6.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Sohlström, Hans
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Holgado, Miguel
    Universidad Politécnica de Madrid.
    Casquel, Rafael
    Universidad Politécnica de Madrid.
    Sanza, Francisco J.
    Universidad Politécnica de Madrid.
    Griol, Amadeu
    Universidad Politécnica de Valencia.
    Bernier, Damien
    Multitel.
    Dortu, Fabian
    Multitel.
    Cáceres, Santiago
    ETRA I+D.
    Aparicio, Francisco J.
    Instituto de Ciencia de Materiales de Sevilla CSIC-Universidad de Sevilla.
    Alcaire, María
    Instituto de Ciencia de Materiales de Sevilla CSIC-Universidad de Sevilla.
    González-Elipe, Agustín R.
    Instituto de Ciencia de Materiales de Sevilla CSIC-Universidad de Sevilla.
    Barranco, Angel
    Instituto de Ciencia de Materiales de Sevilla CSIC-Universidad de Sevilla.
    A photonic dye-based sensing system on a chip produced at wafer scaleArticle in journal (Other academic)
  • 7.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Sohlström, Hans
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Holgado, Miguel
    Casquel, Rafael
    Sanza, Francisco J.
    Griol, Amadeu
    Bernier, Damien
    Dortu, Fabian
    Cáceres, Santiago
    Aparicio, Francisco J.
    Alcaire, Maria
    Gonzáles-Elipe, Agustin R.
    Barranco, Angel
    A wafer-scale, dye-based, photonic sensing systemManuscript (preprint) (Other academic)
  • 8.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Small footprint wafer-level vacuum packaging using compressible gold sealing rings2011In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 21, no 8, p. 085011-Article in journal (Refereed)
    Abstract [en]

    A novel low-temperature wafer-level vacuum packaging process is presented. The process uses plastically deformed gold rings as sealing structures in combination with flux-free soldering to provide the bond force for a sealing wafer. This process enables the separation of the sealing and the bonding functions both spatially on the wafer and temporally in different process steps, which results in reduced areas for the sealing rings and prevents outgassing from the solder process in the cavity. This enables space savings and yields improvements. We show the experimental result of the hermetic sealing. The leak rate into the packages is determined, by measuring the package lid deformation over 10 months, to be lower than 3.5 x 10(-13) mbar l s(-1), which is suitable for most MEMS packages. The pressure inside the produced packages is measured to be lower than 10 mbar.

  • 9. Aparicio, Francisco J.
    et al.
    Alcaire, Maria
    Gonzalez-Elipe, Agustin R.
    Barranco, Angel
    Holgado, Miguel
    Casquel, Rafael
    Sanza, Francisco J.
    Griol, Amadeu
    Bernier, Damien
    Dortu, Fabian
    Caceres, Santiago
    Antelius, Mikael
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. APR Technol AB, Sweden.
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Bosch Automot Elect, Germany.
    Sohlstrom, Hans
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Dye-based photonic sensing systems2016In: Sensors and actuators. B, Chemical, ISSN 0925-4005, E-ISSN 1873-3077, Vol. 228, p. 649-657Article in journal (Refereed)
    Abstract [en]

    We report on dye-based photonic sensing systems which are fabricated and packaged at wafer scale. For the first time luminescent organic nanocomposite thin-films deposited by plasma technology are integrated in photonic sensing systems as active sensing elements. The realized dye-based photonic sensors include an environmental NO2 sensor and a sunlight ultraviolet light (UV) A+B sensor. The luminescent signal from the nanocomposite thin-films responds to changes in the environment and is selectively filtered by a photonic structure consisting of a Fabry-Perot cavity. The sensors are fabricated and packaged at wafer-scale, which makes the technology viable for volume manufacturing. Prototype photonic sensor systems have been tested in real-world scenarios. (C) 2016 Elsevier B.V. All rights reserved.

  • 10.
    Asiatici, Mikhail
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Ecole Polytech Fed Lausanne, Switzerland.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Karlsruhe Inst Technol,Germany.
    Rodjegard, Henrik
    Haasl, Sjoerd
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Capacitive inertial sensing at high temperatures of up to 400 degrees C2016In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 238, p. 361-368Article in journal (Refereed)
    Abstract [en]

    High-temperature-resistant inertial sensors are increasingly requested in a variety of fields such as aerospace, automotive and energy. Capacitive detection is especially suitable for sensing at high temperatures due to its low intrinsic temperature dependence. In this paper, we present high-temperature measurements utilizing a capacitive accelerometer, thereby proving the feasibility of capacitive detection at temperatures of up to 400 degrees C. We describe the observed characteristics as the temperature is increased and propose an explanation of the physical mechanisms causing the temperature dependence of the sensor, which mainly involve the temperature dependence of the Young's modulus and of the viscosity and the pressure of the gas inside the sensor cavity. Therefore a static electromechanical model and a dynamic model that takes into account squeeze film damping were developed.

  • 11.
    Asiatici, Mikhail
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. The School of Computer and Communication Sciences, École Polytechnique Fédérale de Lausanne (EPFL), 1015 Lausanne, Switzerland.
    Laakso, Miku
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. The Institute of Nanotechnology, Karlsruhe Institute of Technology (KIT), 76344 Karlsruhe, Germany.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    Through Silicon Vias With Invar Metal Conductor for High-Temperature Applications2017In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 26, no 1, p. 158-168Article in journal (Refereed)
    Abstract [en]

    Through silicon vias (TSVs) are key enablers of 3-D integration technologies which, by vertically stacking andinterconnecting multiple chips, achieve higher performances,lower power, and a smaller footprint. Copper is the mostcommonly used conductor to fill TSVs; however, copper hasa high thermal expansion mismatch in relation to the siliconsubstrate. This mismatch results in a large accumulation ofthermomechanical stress when TSVs are exposed to high temperaturesand/or temperature cycles, potentially resulting in devicefailure. In this paper, we demonstrate 300 μm long, 7:1 aspectratio TSVs with Invar as a conductive material. The entireTSV structure can withstand at least 100 thermal cycles from −50 °C to 190 °C and at least 1 h at 365 °C, limited bythe experimental setup. This is possible thanks to matchingcoefficients of thermal expansion of the Invar via conductor andof silicon substrate. This results in thermomechanical stressesthat are one order of magnitude smaller compared to copperTSV structures with identical geometries, according to finiteelement modeling. Our TSV structures are thus a promisingapproach enabling 2.5-D and 3-D integration platforms for hightemperatureand harsh-environment applications.

  • 12. Ayala, Christopher L.
    et al.
    Grogg, Daniel
    Bazigos, Antonios
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fernandez-Bolanos, Montserrat
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Hagleitner, Christoph
    Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 113, p. 157-166Article in journal (Refereed)
    Abstract [en]

    Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

  • 13.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Dubois, Valentin J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Ottonello Briano, Floria
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Adhesive Wafer Bonding for Heterogeneous System Integration2018In: ECS Meeting Abstracts / [ed] The Electrochemical Society, 2018Conference paper (Refereed)
  • 14.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Dubois, Valentin
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Schröder, Stephan
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Adhesive wafer bonding with ultra-thin intermediate polymer layers2017In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 260, p. 16-23Article in journal (Refereed)
    Abstract [en]

    Wafer bonding methods with ultra-thin intermediate bonding layers are critically important in heterogeneous 3D integration technologies for many NEMS and photonic device applications. A promising wafer bonding approach for 3D integration is adhesive bonding. So far however, adhesive bonding processes relied on relatively thick intermediate adhesive layers. In this paper, we present an adhesive wafer bonding process using an ultra-thin intermediate adhesive layer with sub-200 nm thickness. We demonstrate adhesive bonding of silicon wafers with a near perfect bonding yield of >99% and achieve less than ±10% non-uniformity of the intermediate layer thickness across an entire 100 mm-diameter wafer. A bond strength of 4.8 MPa was measured for our polymer adhesive, which is considerably higher than previously reported for other ultra-thin film adhesives. Additionally, the adhesive polymer used in the proposed method features excellent chemical and mechanical stability. We also report on a potential strategy for mitigating the formation of micro-voids in the polymer adhesive at the bond interface. Furthermore, the polymer adhesive can be sacrificially removed by oxygen plasma etching for both isotropic and anisotropic release etching. The characteristics of the adhesive wafer bonding process and its compatibility with CMOS wafers, makes it very attractive for heterogeneous 3D integration processes targeted at CMOS-integrated NEMS and photonic devices.

  • 15.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Karlsruhe Institute of Technology (KIT), Germany.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    High-speed Metal-filling of Through-Silicon Vias (TSVs) by Parallelized Magnetic Assembly of Micro-Wires2016In: 2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS), Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 577-580Conference paper (Refereed)
    Abstract [en]

    This work reports a parallelized magnetic assembly method for scalable and cost-effective through-silicon via (TSV) fabrication. Our fabrication approach achieves high throughput by utilizing multiple magnets below the substrate to assemble TSV structures on many dies in parallel. Experimental results show simultaneous filling of four arrays of TSVs on a single substrate, with 100 via-holes each, in less than 20 seconds. We demonstrate that increasing the degree of parallelization by employing more assembly magnets below the substrate has no negative effect on the TSV filling speed or yield, thus enabling scaled-up TSV fabrication on full wafer-level. This method shows potential for industrial application with an estimated throughput of more than 70 wafers per hour in one single fabrication module. Such a TSV fabrication process could offer shorter processing times as well as higher obtainable aspect ratios compared to conventional TSV filling methods.

  • 16.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Shah, Umer
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Somjit, Nutapong
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Oberhammer, Joachim
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires2015In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 5, no 1, p. 21-27Article in journal (Refereed)
    Abstract [en]

    In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.

  • 17.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Visser Taklo, Maaike Margrete
    Department of Instrumentation, SINTEF ICT, Norway.
    Lietaer, Nicolas
    Department of Microsystems and Nanotechnology, SINTEF ICT, Norway.
    Vogl, Andreas
    Department of Microsystems and Nanotechnology, SINTEF ICT, Norway.
    Bakke, Thor
    Department of Microsystems and Nanotechnology, SINTEF ICT, Norway.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding2016In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 7, no 10, p. 192-Article in journal (Refereed)
    Abstract [en]

    Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  • 18. Braun, Stefan
    et al.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Henrik, Gradin
    Method for the wafer-level integration of shape memory alloy wires2013Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    The present invention relates to a method to attach a shape memory alloy wire to a substrate, where the wire is mechanically attached into a 3D structure on the substrate. The present invention also relates to a device comprising a shape memory alloy wire attached to a substrate, where the wire is mechanically attached into a 3D structure on the substrate.

  • 19.
    Decharat, Adit
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Boers, Marc
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Novel room-temperature wafer-to-wafer attachment and sealing of cavities using cold metal welding2007In: PROCEEDINGS OF THE IEEE TWENTIETH ANNUAL INTERNATIONAL CONFERENCE ON MICRO ELECTRO MECHANICAL SYSTEMS, 2007, p. 754-757Conference paper (Refereed)
    Abstract [en]

    In this paper we present for the first time a wafer-to-wafer attachment and sealing method for wafer level manufacturing of micro-cavities using a room temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs and their impact on the resulting bonds. Experiments are performed to evaluate the sealing properties against liquids and vapors of the different sealing ring structures.

  • 20.
    Decharat, Adit
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    NOVEL ROOM-TEMPERATURE WAFER-TO-WAFER ATTACHMENT AND SEALING OF CAVITIES USING COLD METAL WELDING2008In: Proceedings Micro System Workshop MSW08, 2008Conference paper (Other academic)
  • 21.
    Decharat, Adit
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Yu, Junchun
    Boers, Marc
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Room-Temperature Sealing of Microcavities by Cold Metal Welding2009In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 18, no 6, p. 1318-1325Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a wafer-to-wafer attachment and sealing method for wafer-level manufacturing of micro-cavities using a room-temperature bonding process. The proposed attachment and sealing method is based on plastic deformation and cold welding of overlapping metal rings to create metal-to-metal bonding and sealing. We present the results from experiments using various bonding process parameters and metal sealing ring designs including their impact on the resulting bond quality. The sealing properties against liquids and vapor of different sealing ring structures have been evaluated for glass wafers that are bonded to silicon wafers. In addition, wafer-level vacuum sealing of microcavities was demonstrated when bonding a silicon wafer to another silicon wafer with the proposed room-temperature sealing and bonding technique.

  • 22.
    Dubois, Valentin J.
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Scalable Manufacturing of Nanogaps2018In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 30, no 46, article id 1801124Article, review/survey (Refereed)
    Abstract [en]

    The ability to manufacture a nanogap in between two electrodes has proven a powerful catalyst for scientific discoveries in nanoscience and molecular electronics. A wide range of bottom-up and top-down methodologies are now available to fabricate nanogaps that are less than 10 nm wide. However, most available techniques involve time-consuming serial processes that are not compatible with large-scale manufacturing of nanogap devices. The scalable manufacturing of sub-10 nm gaps remains a great technological challenge that currently hinders both experimental nanoscience and the prospects for commercial exploitation of nanogap devices. Here, available nanogap fabrication methodologies are reviewed and a detailed comparison of their merits is provided, with special focus on large-scale and reproducible manufacturing of nanogaps. The most promising approaches that could achieve a breakthrough in research and commercial applications are identified. Emerging scalable nanogap manufacturing methodologies will ultimately enable applications with high scientific and societal impact, including high-speed whole genome sequencing, electromechanical computing, and molecular electronics using nanogap electrodes.

  • 23.
    Dubois, Valentin J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Design and fabrication of crack-junctions2017In: MICROSYSTEMS & NANOENGINEERING, ISSN 2055-7434, Vol. 3, article id UNSP 17042Article in journal (Refereed)
    Abstract [en]

    Nanogap electrodes consist of pairs of electrically conducting tips that exhibit nanoscale gaps. They are building blocks for a variety of applications in quantum electronics, nanophotonics, plasmonics, nanopore sequencing, molecular electronics, and molecular sensing. Crack-junctions (CJs) constitute a new class of nanogap electrodes that are formed by controlled fracture of suspended bridge structures fabricated in an electrically conducting thin film under residual tensile stress. Key advantages of the CJ methodology over alternative technologies are that CJs can be fabricated with wafer-scale processes, and that the width of each individual nanogap can be precisely controlled in a range from <2 to >100 nm. While the realization of CJs has been demonstrated in initial experiments, the impact of the different design parameters on the resulting CJs has not yet been studied. Here we investigate the influence of design parameters such as the dimensions and shape of the notches, the length of the electrode-bridge and the design of the anchors, on the formation and propagation of cracks and on the resulting features of the CJs. We verify that the design criteria yields accurate prediction of crack formation in electrode-bridges featuring a beam width of 280 nm and beam lengths ranging from 1 to 1.8 mu m. We further present design as well as experimental guidelines for the fabrication of CJs and propose an approach to initiate crack formation after release etching of the suspended electrode-bridge, thereby enabling the realization of CJs with pristine electrode surfaces.

  • 24.
    Dubois, Valentin J.
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Raja, Shyamprasad Natarajan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Gehring, Pascal
    Delft Univ Technol, Kavli Inst Nanosci, Lorentzweg 1, NL-2628 CJ Delft, Netherlands..
    Caneva, Sabina
    Delft Univ Technol, Kavli Inst Nanosci, Lorentzweg 1, NL-2628 CJ Delft, Netherlands..
    van der Zant, Herre S. J.
    Delft Univ Technol, Kavli Inst Nanosci, Lorentzweg 1, NL-2628 CJ Delft, Netherlands..
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Massively parallel fabrication of crack-defined gold break junctions featuring sub-3 nm gaps for molecular devices2018In: Nature Communications, ISSN 2041-1723, E-ISSN 2041-1723, Vol. 9, article id 3433Article in journal (Refereed)
    Abstract [en]

    Break junctions provide tip-shaped contact electrodes that are fundamental components of nano and molecular electronics. However, the fabrication of break junctions remains notoriously time-consuming and difficult to parallelize. Here we demonstrate true parallel fabrication of gold break junctions featuring sub-3 nm gaps on the wafer-scale, by relying on a novel self-breaking mechanism based on controlled crack formation in notched bridge structures. We achieve fabrication densities as high as 7 million junctions per cm(2), with fabrication yields of around 7% for obtaining crack-defined break junctions with sub-3 nm gaps of fixed gap width that exhibit electron tunneling. We also form molecular junctions using dithiol-terminated oligo(phenylene ethynylene) (OPE3) to demonstrate the feasibility of our approach for electrical probing of molecules down to liquid helium temperatures. Our technology opens a whole new range of experimental opportunities for nano and molecular electronics applications, by enabling very large-scale fabrication of solid-state break junctions.

  • 25.
    Dubois, Valentin
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Crack-defined electronic nanogaps2016In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 28, no 11, p. 2178-2182Article in journal (Refereed)
    Abstract [en]

    Achieving near-atomic-scale electronic nanogaps in a reliable and scalable manner will facilitate fundamental advances in molecular detection, plasmonics, and nanoelectronics. Here, a method is shown for realizing crack-defined nanogaps separating TiN electrodes, allowing parallel and scalable fabrication of arrays of sub-10 nm electronic nanogaps featuring individually defined gap widths.

  • 26.
    Dubois, Valentin
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Design optimization and characterization of nanogap crack-junctions2017Conference paper (Refereed)
    Abstract [en]

    A crack-junction (CJ) is a nanogap electrode pair featuring reliable and controlled nanoscale gap widths that can be produced in large numbers with high dimensional accuracy on a substrate. In this paper, we present a discussion on geometrical considerations of CJs made of titanium nitride (TiN) electrodes, which provides guidelines for reliable formation of TiN CJs with well-defined dimensions. We further provide complete electrical characterization of 40 TiN CJs designed as electron tunneling junctions.

  • 27.
    Dubois, Valentin
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Massively parallel fabrication of crack-defined gold break junctions featuring sub-3 nm electrode nanogapsIn: Article in journal (Refereed)
  • 28.
    Enrico, Alessandro
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Dubois, Valentin J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Scalable Manufacturing of Single Nanowire Devices Using Crack-Defined Shadow Mask Lithography2019In: ACS Applied Materials and Interfaces, ISSN 1944-8244, E-ISSN 1944-8252, Vol. 11, no 8, p. 8217-8226Article in journal (Refereed)
    Abstract [en]

    Single nanowires (NWs) have a broad range of applications in nanoelectronics, nanomechanics, and nano photonics, but, to date, no technique can produce single sub 20 nm wide NWs with electrical connections in a scalable fashion. In this work, we combine conventional optical and crack lithographies to generate single NW devices with controllable and predictable dimensions and placement and with individual electrical contacts to the NWs. We demonstrate NWs made of gold, platinum, palladium, tungsten, tin, and metal oxides. We have used conventional i-line stepper lithography with a nominal resolution of 365 nm to define crack lithography structures in a shadow mask for large-scale manufacturing of sub-20 nm wide NWs, which is a 20-fold improvement over the resolution that is possible with the utilized stepper lithography. Overall, the proposed method represents an effective approach to generate single NW devices with useful applications in electrochemistry, photonics, and gas- and biosensing.

  • 29.
    Enrico, Alessandro
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Dubois, Valentin
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Scalable fabrication of single nanowire devices using crack-defined shadow mask lithographyIn: Article in journal (Refereed)
  • 30.
    Ericsson, Per
    et al.
    Acreo AB.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Samel, Björn
    Acreo AB.
    Savage, Susan
    Acreo AB.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Wissmar, Stanley
    Acreo AB.
    Öberg, Olof
    Acreo AB.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Toward 17µm pitch heterogeneously integrated Si/SiGe quantum well bolometer focal plane arrays2011In: Infrared Technology and Applications XXXVII: Proc. of SPIE, Vol. 8012, SPIE - International Society for Optical Engineering, 2011, p. 801216-1-801216-9Conference paper (Refereed)
    Abstract [en]

    Most of today's commercial solutions for un-cooled IR imaging sensors are based on resistive bolometers using either Vanadium oxide (VOx) or amorphous Silicon (a-Si) as the thermistor material. Despite the long history for both concepts, market penetration outside high-end applications is still limited. By allowing actors in adjacent fields, such as those from the MEMS industry, to enter the market, this situation could change. This requires, however, that technologies fitting their tools and processes are developed. Heterogeneous integration of Si/SiGe quantum well bolometers on standard CMOS read out circuits is one approach that could easily be adopted by the MEMS industry. Due to its mono crystalline nature, the Si/SiGe thermistor material has excellent noise properties that result in a state-ofthe- art signal-to-noise ratio. The material is also stable at temperatures well above 450°C which offers great flexibility for both sensor integration and novel vacuum packaging concepts. We have previously reported on heterogeneous integration of Si/SiGe quantum well bolometers with pitches of 40μm x 40μm and 25μm x 25μm. The technology scales well to smaller pixel pitches and in this paper, we will report on our work on developing heterogeneous integration for Si/SiGe QW bolometers with a pixel pitch of 17μm x 17μm.

  • 31.
    Errando-Herranz, Carlos
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Edinger, Pierre
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Colangelo, Marco
    KTH.
    Björk, Joel
    KTH.
    Ahmed, Samy
    KTH.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    New dynamic silicon photonic components enabled by MEMS technology2018In: Proceedings Volume 10537, Silicon Photonics XIII, SPIE - International Society for Optical Engineering, 2018, Vol. 10537, article id 1053711Conference paper (Refereed)
    Abstract [en]

    Silicon photonics is the study and application of integrated optical systems which use silicon as an optical medium, usually by confining light in optical waveguides etched into the surface of silicon-on-insulator (SOI) wafers. The term microelectromechanical systems (MEMS) refers to the technology of mechanics on the microscale actuated by electrostatic actuators. Due to the low power requirements of electrostatic actuation, MEMS components are very power efficient, making them well suited for dense integration and mobile operation. MEMS components are conventionally also implemented in silicon, and MEMS sensors such as accelerometers, gyros, and microphones are now standard in every smartphone. By combining these two successful technologies, new active photonic components with extremely low power consumption can be made. We discuss our recent experimental work on tunable filters, tunable fiber-to-chip couplers, and dynamic waveguide dispersion tuning, enabled by the marriage of silicon MEMS and silicon photonics.

  • 32.
    Errando-Herranz, Carlos
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    A Low-power MEMS Tunable Photonic Ring Resonator for Reconfigurable Optical Networks2015In: Proceedings of The 28th IEEE International Conference on Micro Electro Mechanical Systems (MEMS) Estoril, Portugal. Jan 2015, IEEE conference proceedings, 2015, p. 53-56Conference paper (Refereed)
    Abstract [en]

    We experimentally demonstrate a low-power MEMS tunable photonic ring resonator with 10 selectable channels for wavelength selection in reconfigurable optical networks operating in the C band. The tuning is achieved by changing the geometry of the slot of a silicon slot-waveguide ring resonator, by means of vertical electrostatic parallel-plate actuation. Our device provides static power dissipation below 0.1 μW, a wavelength tuning range of 1 nm, and a narrow bandwidth of 0.1 nm, i.e. 10 nW static power dissipation per selectable channel for TE mode tuning.

  • 33.
    Errando-Herranz, Carlos
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    A MEMS tunable photonic ring resonator with small footprint and large free spectral range2015In: Solid-State Sensors, Actuators and Microsystems (TRANSDUCERS), 2015 Transducers - 2015 18th International Conference on, IEEE conference proceedings, 2015, p. 1001-1004Conference paper (Refereed)
    Abstract [en]

    We demonstrate a MEMS tunable silicon photonic ringresonator with a 20 μm radius and a 5 nm free spectral range (FSR) for wavelength selection in reconfigurable optical networks. The device shows a loaded Q of 12000, and 300 pm tuning at a wavelength of 1544 nm.

  • 34.
    Errando-Herranz, Carlos
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Low-power microelectromechanically tunable silicon photonic ring resonator add-drop filter2015In: Optics Letters, ISSN 0146-9592, E-ISSN 1539-4794, Vol. 40, no 15, p. 3556-3559Article in journal (Refereed)
    Abstract [en]

    We experimentally demonstrate a microelectromechanically (MEMS) tunable photonic ring resonator add-€“drop filter, fabricated in a simple silicon-on-insulator (SOI) based process. The device uses electrostatic parallel plate actuation to perturb the evanescent field of a silicon waveguide, and achieves a 530 pm resonance wavelength tuning, i.e., more than a fourfold improvement compared to previous MEMS tunable ring resonator add-€“drop filters. Moreover, our device has a static power consumption below 100 nW, and a tuning rate of -ˆ’62 €€‰pm/V, i.e., the highest reported rate for electrostatic tuning of ring resonator add-€“drop filters.

  • 35.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems.
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems.
    Wagner, Stefan
    AMO GmbH.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Lemme, Max C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. RWTH Aachen University; AMO GmbH.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligenta system, Micro and Nanosystems.
    Suspended Graphene Membranes with Attached Silicon Proof Masses as Piezoresistive Nanoelectromechanical Systems Accelerometers2019In: Nano letters (Print), ISSN 1530-6984, E-ISSN 1530-6992, Vol. 19, no 10, p. 6788-6799Article in journal (Refereed)
    Abstract [en]

    Graphene is an atomically thin material that features unique electrical and mechanical properties, which makes it an extremely promising material for future nanoelectromechanical systems (NEMS). Recently, basic NEMS accelerometer functionality has been demonstrated by utilizing piezoresistive graphene ribbons with suspended silicon proof masses. However, the proposed graphene ribbons have limitations regarding mechanical robustness, manufacturing yield, and the maximum measurement current that can be applied across the ribbons. Here, we report on suspended graphene membranes that are fully clamped at their circumference and have attached silicon proof masses. We demonstrate their utility as piezoresistive NEMS accelerometers, and they are found to be more robust, have longer life span and higher manufacturing yield, can withstand higher measurement currents, and are able to suspend larger silicon proof masses, as compared to the previous graphene ribbon devices. These findings are an important step toward bringing ultraminiaturized piezoresistive graphene NEMS closer toward deployment in emerging applications such as in wearable electronics, biomedical implants, and internet of things (IoT) devices.

  • 36.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Suspended graphenemembranes with attached proof masses as piezoresistive NEMS accelerometersIn: Article in journal (Refereed)
  • 37.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Rödjegård, Henrik
    Senseair AB .
    Fisher, Andreas
    Silex Microsystems AB.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Graphene beams with suspended masses as electromechanical transducers in ultra-small accelerometersIn: Article in journal (Refereed)
  • 38.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Fredrik, Forsberg
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Senseair AB.
    Wagner, Stefan
    AMO GmbH.
    Rödjegård, Henrik
    Senseair AB.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB, Järfälla, Sweden.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Lemme, Max C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. RWTH Aachen University ; AMO GmbH.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Graphene ribbons with suspended masses as transducers in ultra-small nanoelectromechanical accelerometers2019In: Nature Electronics, ISSN 2520-1131, Vol. 2, no 9, p. 394-404Article in journal (Refereed)
    Abstract [eo]

    Nanoelectromechanical system (NEMS) sensors and actuators could be of use in the development of next-generation mobile, wearable and implantable devices. However, these NEMS devices require transducers that are ultra-small, sensitive and can be fabricated at low cost. Here, we show that suspended double-layer graphene ribbons with attached silicon proof masses can be used as combined spring–mass and piezoresistive transducers. The transducers, which are created using processes that are compatible with large-scale semiconductor manufacturing technologies, can yield NEMS accelerometers that occupy at least two orders of magnitude smaller die area than conventional state-of-the-art silicon accelerometers. With our devices, we also extract the Young’s modulus values of double-layer graphene and show that the graphene ribbons have significant built-in stresses.

  • 39.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Forsberg, Fredrik
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Fisher, Andreas
    Silex Microsystems AB.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Manufacturing of Graphene Membranes with Suspended Silicon Proof Masses forMEMS and NEMSIn: Article in journal (Refereed)
  • 40.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen University, Otto-Blumenthal-Str. 25, 52074 Aachen, Germany.
    Schädlich, Philip
    Institute of Physics, Chemnitz University of Technology, Reichenhainer Straße 70, 09126 Chemnitz, Germany.
    Speck, Florian
    Institute of Physics, Chemnitz University of Technology, Reichenhainer Straße 70, 09126 Chemnitz, Germany.
    Satender, Kataria
    Faculty of Electrical Engineering and Information Technology, Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen University, Otto-Blumenthal-Str. 25, 52074 Aachen, Germany.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Seyller, Thomas
    Institute of Physics, Chemnitz University of Technology, Reichenhainer Straße 70, 09126 Chemnitz, Germany.
    Lemme, Max C.
    Faculty of Electrical Engineering and Information Technology, Rheinisch-Westfälische Technische Hochschule (RWTH) Aachen University, Otto-Blumenthal-Str. 25, 52074 Aachen, Germany ; Gesellschaft für angewandte Mikro- und Optoelektronik mbH (AMO GmbH), Advanced Microelectronic Center Aachen, Otto-Blumenthal Str. 25, 52074 Aachen, Germany.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Direct observation of grain boundaries in graphene through vapor hydrofluoric acid (VHF) exposure2018In: Science advances, ISSN 2375-2548, Vol. 4, no 5, article id eaar5170Article in journal (Refereed)
    Abstract [en]

    The shape and density of grain boundary defects in graphene strongly influence its electrical, mechanical, and chemical properties. However, it is difficult and elaborate to gain information about the large-area distribution of grain boundary defects in graphene. An approach is presented that allows fast visualization of the large-area distribution of grain boundary–based line defects in chemical vapor deposition graphene after transferring graphene from the original copper substrate to a silicon dioxide surface. The approach is based on exposing graphene to vapor hydrofluoric acid (VHF), causing partial etching of the silicon dioxide underneath the graphene as VHF diffuses through graphene defects. The defects can then be identified using optical microscopy, scanning electron microscopy, or Raman spectroscopy. The methodology enables simple evaluation of the grain sizes in polycrystalline graphene and can therefore be a valuable procedure for optimizing graphene synthesis processes.

  • 41.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Belova, Lyubov M.
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    3D Free-Form Patterning of Silicon by Ion Implantation, Silicon Deposition, and Selective Silicon Etching2012In: Advanced Functional Materials, ISSN 1616-301X, E-ISSN 1616-3028, Vol. 22, no 19, p. 4004-4008Article in journal (Refereed)
    Abstract [en]

    A method for additive layer-by-layer fabrication of arbitrarily shaped 3D silicon micro- and nanostructures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The method is demonstrated by fabricating 3D structures made of two and three silicon layers, including suspended beams that are 40 nm thick, 500 nm wide, and 4 μm long, and patterned lines that are 33 nm wide.

  • 42.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires2012In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 10, p. 105001-Article in journal (Refereed)
    Abstract [en]

    Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

  • 43.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Somjit, Nutapong
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    high aspect ratio tsvs fabricated by magnetic self-assembly of gold-coated nickel wires2012In: Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, IEEE conference proceedings, 2012, p. 541-547Conference paper (Refereed)
    Abstract [en]

    Three-dimensional (3D) integration is an emerging technologythat vertically interconnects stacked dies of electronics and/orMEMS-based transducers using through silicon vias (TSVs).TSVs enable the realization of devices with shorter signal lengths,smaller packages and lower parasitic capacitances, which can resultin higher performance and lower costs of the system. Inthis paper we demonstrate a new manufacturing technology forhigh-aspect ratio (> 8) through silicon metal vias using magneticself-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enablesthrough-wafer vias with high aspect ratios and superior electricalcharacteristics. This technique eliminates common issues inTSV fabrication using conventional approaches, such as the metaldeposition and via insulation and hence it has the potential to reducesignificantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications.

  • 44.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES).
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Integrating MEMS and ICs2015In: Microsystems & Nanoengineering, ISSN 2055-7434, Vol. 1, no 1, p. 1-16, article id 15005Article, book review (Refereed)
    Abstract [en]

    The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than-Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

  • 45.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Zimmer, F.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Heterogeneous Integration for Optical MEMS2010In: 2010 23RD ANNUAL MEETING OF THE IEEE PHOTONICS SOCIETY, NEW YORK: IEEE , 2010, p. 487-488Conference paper (Refereed)
    Abstract [en]

    In this paper we present different large-scale heterogeneous integration technologies for optical MEMS that enable the integration of optical MEMS with standard CMOS-based ICs. Examples that are presented include various monocrystalline silicon micro-mirror arrays and infrared bolometer arrays.

  • 46.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Gradin, Henrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Braun, Stefan
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Schröder, Stephan
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Wafer-level integration of NiTi shape memory alloy wires for the fabrication of microactuators using standard wire bonding technology2011In: 24th International Conference on Micro Electro Mechanical Systems (MEMS), 2011 IEEE, IEEE , 2011, p. 348-351Conference paper (Refereed)
    Abstract [en]

    This paper reports on the first integration of SMA wires into silicon based MEMS structures using a standard wire bonder. This approach allows fast and efficient placement, alignment and mechanical attachment of NiTi-based SMA wires to silicon-based MEMS. The wires are mechanically anchored and clamped into deep-etched silicon structures on a wafer. The placement precision is high with an average deviation of 4 #x03BC;m and the mechanical clamping is strong, allowing successful actuation of the SMA wires.

  • 47.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Gradin, Henrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Schröder, Stephan
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Braun, Stefan
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    van der Wijngaart, Wouter
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Wire-bonder-assisted integration of non-bondable SMA wires into MEMS substrates2012In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 5, p. 055025-Article in journal (Refereed)
    Abstract [en]

    This paper reports on a novel technique for the integration of NiTi shape memory alloy wires and other non-bondable wire materials into silicon-based microelectromechanical system structures using a standard wire-bonding tool. The efficient placement and alignment functions of the wire-bonding tool are used to mechanically attach the wire to deep-etched silicon anchoring and clamping structures. This approach enables a reliable and accurate integration of wire materials that cannot be wire bonded by traditional means.

  • 48.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Grange, M.
    Department of Engineering, Centre for Microsystems Engineering, Lancaster University, Lancaster LA1 4YW, UK.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Weerasekera, R.
    Department of Engineering, Centre for Microsystems Engineering, Lancaster University, Lancaster LA1 4YW, UK.
    Pamunuwa, D.
    Department of Engineering, Centre for Microsystems Engineering, Lancaster University, Lancaster LA1 4YW, UK.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Wire-bonded through-silicon vias with low capacitive substrate coupling2011In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 21, no 8, p. 085035-Article in journal (Refereed)
    Abstract [en]

    Three-dimensional integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies with through-silicon vias (TSVs). They enable the realization of circuits with shorter signal path lengths, smaller packages and lower parasitic capacitances, which results in higher performance and lower costs. This paper presents a novel technique for fabricating TSVs from bonded gold wires. The wires are embedded in a polymer, which acts both as an electrical insulator, resulting in low capacitive coupling toward the substrate and as a buffer for thermo-mechanical stress.

  • 49.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Belova, Liubov M.
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Applied Material Physics.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rikers, Yuri G.M.
    FEI Electron Optics.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    3D Patterning of Si Micro and Nano Structures by Focused Ion Beam Implantation, Si Deposition and Selective Si Etching2012Conference paper (Other academic)
  • 50.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Belova, Lyubov M.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, M.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rikers, Y. G. M.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Layer-by-layer 3D printing of Si micro- and nanostructures by Si deposition, ion implantation and selective Si etching2012In: 12th IEEE Conference on Nanotechnology (IEEE-NANO), 2012, IEEE conference proceedings, 2012, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper we report a method for layer-by-layer printing of three-dimensional (3D) silicon (Si) micro- and nanostructures. This fabrication method is based on a sequence of alternating steps of chemical vapor deposition of Si and local implantation of gallium (Ga+) ions by focused ion beam (FIB) writing. The defined 3D structures are formed in a final step by selectively wet etching the non-implanted Si in potassium hydroxide (KOH). We demonstrate the viability of the method by fabricating 2 and 3-layer 3D Si structures, including suspended beams and patterned lines with dimensions on the nm-scale.

1234 1 - 50 of 185
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