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  • 1.
    Bakowski, M.
    et al.
    Acreo AB, Sweden.
    Lim, Jang-Kwon
    Acreo AB, Sweden.
    Kaplan, W.
    Acreo AB, Sweden.
    Merits of Buried Grid Technology for SiC JBS Diodes2012In: GALLIUM NITRIDE AND SILICON CARBIDE POWER TECHNOLOGIES 2, 2012, Vol. 50, no 3, p. 415-424Conference paper (Refereed)
    Abstract [en]

    The SiC Schottky barrier diodes for 200 degrees C to 250 degrees C operation have been developed using buried grid (BG) technology. 2A and 10A, 1700V BG JBS diodes have been fabricated and evaluated. Manufactured 10A, 1700V BG JBS diodes have leakage current at least three orders of magnitude lower compared to the typical data sheet values of the commercial devices. The leakage current at 250 degrees C is of the same order of magnitude as that of the commercial devices at 175 degrees C. The two alternative technologies for realization of BG, implantation and epitaxy, have been compared by simulations. The epitaxial grid is shown to have superior potential for best trade-off between on-state voltage and leakage current.

  • 2.
    Bakowski, M.
    et al.
    Acreo AB, Sweden.
    Lim, Jang-Kwon
    Acreo AB, Sweden.
    Kaplan, W.
    Acreo AB, Sweden.
    Schoener, A.
    Acreo AB, Sweden.
    Merits of Buried Grid Technology for Advanced SiC Device Concepts2011In: GALLIUM NITRIDE AND SILICON CARBIDE POWER TECHNOLOGIES, 2011, Vol. 41, no 8, p. 155-162Conference paper (Refereed)
    Abstract [en]

    Selected examples of the use of buried grid technology for SiC devices are discussed. First example is development of normally-off and normally-on JFETs, Second the development of Schottky barrier diodes for 250 degrees C operation. Other examples are efficient junction termination and avalanche UV detectors. Experimental results are used in support of simulations.

  • 3. Hjort, T.
    et al.
    Schöner, A.
    Zhang, A.
    Bakowski, M.
    Lim, Jang-Kwon
    Acreo.
    Kaplan, W.
    High temperature capable SiC Schottky diodes, based on buried grid design2014In: International Conference and Exhibition on High Temperature Electronics, 2014, p. 158-160Conference paper (Refereed)
    Abstract [en]

    Electrical characteristics of 4H-SiC Schottky barrier diodes, based on buried grid design are presented. The diodes, rated to 1200V/10A and assembled into high temperature capable T0254 packages, have been tested and studied up to 250°C. Compared to conventional SiC Schottky diodes, Ascatron’s buried grid SiC Schottky diode demonstrates several orders of magnitude reduced leakage current at high temperature operation.

  • 4.
    Lim, Jang-Kwon
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion. Acreo Swedish ICT AB.
    Simulation and Electrical Evaluation of 4H-SiC Junction Field Effect Transistors and Junction Barrier Schottky Diodes with Buried Grids2015Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Silicon carbide (SiC) has higher breakdown field strength than silicon (Si), which enables thinner and more highly doped drift layers compared to Si. Consequently, the power losses can be reduced compared to Si-based power conversion systems. Moreover, SiC allows the power conversion systems to operate at high temperatures up to 250 oC. With such expectations, SiC is considered as the material of choice for modern power semiconductor devices for high efficiencies, high temperatures, and high power densities. Besides the material benefits, the typeof the power device also plays an important role in determining the system performance.

    Compared to the SiC metal-oxide semiconductor field-effect transistor (MOSFET) and bipolar junction transistor (BJT), the SiC junction field-effect transistor (JFET) is a very promising power switch, being a voltage-controlled device without oxide reliability issues. Its channel iscontrolled by a p-n junction. However, the present JFETs are not optimized yet with regard to on-state resistance, controllability of threshold voltage, and Miller capacitance.

    In this thesis, the state-of-the-art SiC JFETs are introduced with buried-grid (BG) technology.The buried grid is formed in the channel through epitaxial growth and etching processes. Through simulation studies, the new concepts of normally-on and -off BG JFETs with 1200 V blocking capability are investigated in terms of static and dynamic characteristics. Additionally, two case studies are performed in order to evaluate total losses on the system level. These investigations can be provided to a power circuit designer for fully exploiting the benefit of power devices. Additionally, they can serve as accurate device models and guidelines considering the switching performance.

    The BG concept utilized for JFETs has been also used for further development of SiC junctionbarrier Schottky (JBS) diodes. Especially, this design concept gives a great impact on high temperature operation due to efficient shielding of the Schottky interface from high electric fields. By means of simulations, the device structures with implanted and epitaxial p-grid formations, respectively, are compared regarding threshold voltage, blocking voltage, and maximum electric field at the Schottky interface. The results show that the device with an epitaxial grid can be more efficient at high temperatures than that with an implanted grid. To realize this concept, the device with implanted grid was optimized using simulations, fabricated and verified through experiments. The BG JBS diode clearly shows that the leakage current is four orders of magnitude lower than that of a pure Schottky diode at an operation temperature of 175 oC and 2 to 3 orders of magnitude lower than that of commercial JBS diodes.

    Finally, commercialized vertical trench JFETs are evaluated both in simulations andexperiments, while it is important to determine the limits of the existing JFETs and study their performance in parallel operation. Especially, the influence of uncertain parameters of the devices and the circuit configuration on the switching performance are determined through simulations and experiments.

  • 5.
    Lim, Jang-Kwon
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics.
    Bakowski, M.
    Analysis of 1.2 kV SiC buried-grid VJFETs2010In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T140, p. 014008-Article in journal (Refereed)
    Abstract [en]

    1.2 kV buried-grid vertical 4H-SiC JFET structures with normally-on (N-on) and normally-off (N-off) designs were investigated by simulation. The static and dynamic characteristics of the devices were determined over a wide range of current, voltage and gate drive conditions in the temperature range -50 degrees C to 250 degrees C. In this paper, the properties of the N-on designs with threshold voltages (V-th) -50 and -10 V are compared with the properties of the N-off design (V-th = 0). For constant V-th, on-resistance decreases and output current increases with increasing channel doping and decreasing channel width. Simulations show that an on-resistance lower than 2 m Omega cm(2) at 250 degrees C can be obtained provided the channel width is smaller than 1.5 and 0.5 mu m for N-on JFETs with V-th = -50 V and V-th = -10 V, respectively, and lower than 3 m Omega cm(2) provided the channel width is smaller than 0.3 mu m for the N-off JFET. At the same time, E-on decreases and E-off increases with increased channel doping concentration and reduced channel width. It is shown that E-on decreases with increasing channel doping concentration due to the reduced channel resistance for the faster turn-on process. E-off increases with increasing channel doping concentration due to the increase in gate-drain capacitance, C-GD.

  • 6.
    Lim, Jang-Kwon
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Peftitsis, Dimosthenis
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Rabkowski, Jacek
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Bakowski, Mietek
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Analysis and Experimental Verification of the Influence of Fabrication Process Tolerances and Circuit Parasitics on Transient Current Sharing of Parallel-Connected SiC JFETs2014In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 29, no 5, p. 2180-2191Article in journal (Refereed)
    Abstract [en]

    Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced current waveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimental devices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type.

  • 7.
    Lim, Jang-Kwon
    et al.
    Acreo.
    Peftitsis, Dimosthenis
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Rabkowski, Jacek
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Bakowski, Mietek
    Acreo.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Modeling of the impact of parameter spread on the switching performance of parallel-connected SiC VJFETs2013In: Materials Science Forum, Trans Tech Publications Inc., 2013, p. 1098-1102Conference paper (Refereed)
    Abstract [en]

    Operation of parallel-connected 4H-SiC VJFETs from SemiSouth was measured and modeled using numerical simulations. The unbalanced current waveforms in parallel-connected VJFETs were related to spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The physical device structure was reconstructed based on SEM analysis, electrical characterization, and device simulations. The two hypothetical critical design parameters that were studied with respect to spread were the p-gate doping profile (Case 1) and the emitter doping (Case 2). Variation in both parameters could be related to variation in the emitter breakdown voltage, the on-state characteristics, and the threshold voltage of the experimental devices. The switching performance of the parallel-connected JFETs was measured using a single gate driver in a double pulse test and compared with simulations. In both investigated cases a very good agreement between measurements and simulations was obtained. The modeling of the transient performance relies on good reproduction of transfer characteristics and circuit parasitics.

  • 8.
    Lim, Jang-Kwon
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Acreo Swedish ICT AB, Sweden.
    Peftitsis, Dimosthenis
    KTH, School of Electrical Engineering (EES).
    Sadik, Diane-Perle
    KTH, School of Electrical Engineering (EES).
    Bakowski, M.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Evaluation of buried grid JBS diodes2014In: 15th International Conference on Silicon Carbide and Related Materials, ICSCRM 2013, Trans Tech Publications Inc., 2014, p. 804-807Conference paper (Refereed)
    Abstract [en]

    The 4H-SiC Schottky barrier diodes for high temperature operation over 200 °C have been developed using buried grids formed by implantation. Compared to a conventional JBS-type SBD with surface grid (SG), JBS-type SBD with buried grid (BG) has significantly reduced leakage current at reverse bias due to a better field shielding of the Schottky contact. By introducing the BG technology, the 1.7 kV diodes with an anode area 0.0024 cm2 (1 A) and 0.024 cm2 (10 A) were successfully fabricated, encapsulated in TO220 packages, and electrically evaluated. Two types of buried grid arrangement with different grid spacing dimensions were investigated. The measured IV characteristics were compared with simulation. The best fit was obtained with an active area of approximately 60% and 70% of the anode area in large and small devices, respectively. The measured values of the device capacitances were 1000 pF in large devices and 100 pF in small devices at zero bias. The capacitance values are proportional to the device area. The recovery behavior of big devices was measured in a double pulse tester and simulated. The recovery charge, Qc, was 18 nC and 24 nC in simulation and measurement, respectively. The fabricated BG JBS-type SBDs have a smaller maximum reverse recovery current compared to the commercial devices. No influence of the different grid spacing on the recovery charge was observed.

  • 9.
    Lim, Jang-Kwon
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion. Acreo Swedish ICT AB, Sweden.
    Reshanov, Sergey
    Kaplan, W.
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Zhang, A.
    Hjort, T.
    Schöner, A.
    Bakowski, M.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Temperature-Dependent Characteristics of 4H-SiC Buried Grid JBS Diodes2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821/823, p. 600-603Article in journal (Refereed)
    Abstract [en]

    4H-SiC Schottky Barrier Diodes (SBD) have been developed using p-type buried grids (BGs) formed by Al implantation. In order to reduce on-state resistance and improve forward conduction, the doping concentration of the channel region between the buried grids was increased. The fabricated diodes were encapsulated with TO-254 packages and electrically evaluated. Experimental forward and reverse characteristics were measured in the temperature range from 25 °C to 250 °C. On bare die level, the forward voltage drop was reduced from 5.36 V to 3.90 V at 20 A as the channel doping concentration was increased, which introduced a low channel resistance. By the encapsulation in TO-254 package, the forward voltage drop was decreased approximately 10% due to a lower contact resistance. The on-state resistance of the identical device measured on bare die and in TO-254 package increased with increasing temperature due to the decreased electron mobility in the drift region resulting in higher resistance. The incremental contact resistances of the bare dies were larger than in the packaged devices. One key issue associated with conventional Junction Barrier Schottky (JBS) diodes is a high leakage current at high temperature operation over 200 °C. The developed Buried Grid JBS (BG JBS) diode has significantly reduced leakage current due to a better field shielding at the Schottky contact. The leakage current of the packaged BG JBS diodes is compared to pure SBD and commercial JBS diodes.

  • 10.
    Lim, Jang-Kwon
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics (closed 20110930).
    Tolstoy, Georg
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics (closed 20110930).
    Peftitsis, Dimosthenis
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics (closed 20110930).
    Rabkowski, Jacek
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics (closed 20110930).
    Bakowski, Mietek
    Acreo, Kista.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics (closed 20110930).
    Comparison of total losses of 1.2 kV SiC JFET and BJT in DC-DC converter including gate driver2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679/680, p. 649-652Article in journal (Refereed)
    Abstract [en]

    The 1.2 kV SiC JFET and BJT devices have been investigated and compared with respect to total losses including the gate driver losses in a DC-DC converter configuration. The buried grid, Normally-on JFET devices with threshold voltage of -50 V and -10V are compared to BJT devices with ideal semiconductor and passivating insulator interface and an interface with surface recombination velocity of 4.5·104 cm/s yielding agreement to the reported experimental current gain values. The conduction losses of both types of devices are independent of the switching frequency while the switching losses are proportional to the switching frequency. The driver losses are proportional to the switching frequency in the JFET case but to a large extent independent of the switching frequency in the BJT case. The passivation of the emitter junction modeled here by surface recombination velocity has a significant impact on conduction losses and gate driver losses in the investigated BJT devices.

  • 11.
    Lim, Jang-Kwon
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion. Acreo Swedish ICT AB, Sweden.
    Östlund, L.
    Wang, Q.
    Kaplan, W.
    Reshanov, S. A.
    Schöner, A.
    Bakowski, M.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    A theoretical and experimental comparison of 4H- and 6H-SiC MSM UV photodetectors2012In: Silicon Carbide and Related Materials 2011, Trans Tech Publications Inc., 2012, Vol. 717-720, p. 1207-1210Conference paper (Refereed)
    Abstract [en]

    This paper reports on fabrication and modeling of 4H- and 6H-SiC metal-semiconductor-metal (MSM) photodetectors (PDs). MSM PDs have been fabricated on 4H-SiC and 6H-SiC epitaxial layers, and their performance analyzed by MEDICI simulation and measurements. The simulations were also used to optimize the sensitivity by varying the width and spacing of the interdigitated electrodes. The fabricated PDs with 2 ÎŒm wide metal electrodes and 3 ÎŒm spacing between the electrodes exhibited, under UV illumination, a peak current to dark current ratio of 10 5 and 10 4 in 4H-SiC and 6H-SiC, respectively. The measured spectral responsivity of 6H-SiC PDs was higher compared to that of 4H-SiC PDs, with a cutoff at 407 nm compared to 384 nm in 4H-SiC PDs. Also the peak responsivity occurred at a shorter wavelength in 6H material. A high rejection ratio between the photocurrent and dark current was found in both cases. These experimental results were in agreement with simulation.

  • 12.
    Peftitsis, Dimosthenis
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Tolstoy, Georg
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Antonopoulos, Antonios
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Rabkowski, Jacek
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Lim, Jang-Kwon
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Bakowski, Mietek
    Acreo AB.
    Ängquist, Lennart
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    High-Power Modular Multilevel Converters With SiC JFETs2012In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 27, no 1, p. 28-36Article in journal (Refereed)
    Abstract [en]

    This paper studies the possibility of building a modular multilevel converter (M2C) using silicon carbide (SiC) switches. The main focus is on a theoretical investigation of the conduction losses of such a converter and a comparison to a corresponding converter with silicon-insulated gate bipolar transistors. Both SiC BJTs and JFETs are considered and compared in order to choose the most suitable technology. One of the submodules of a down-scaled 3 kVA prototype M2C is replaced with a submodule with SiC JFETs without antiparallel diodes. It is shown that the diode-less operation is possible with the JFETs conducting in the negative direction, leaving the possibility to use the body diode during the switching transients. Experimental waveforms for the SiC submodule verify the feasibility during normal steady-state operation. The loss estimation shows that a 300 MW M2C for high-voltage direct current transmission would potentially have an efficiency of approximately 99.8% if equipped with future 3.3 kV 1.2 kA SiC JFETs.

  • 13.
    Sadik, Diane-Perle
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Colmenares, Juan
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Peftitsis, Dimosthenis
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Lim, Jang-Kwon
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Rabkowski, Jacek
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Experimental investigations of static and transient current sharing of parallel-connected silicon carbide MOSFETs2013In: 2013 15th European Conference on Power Electronics and Applications, EPE 2013, 2013Conference paper (Refereed)
    Abstract [en]

    An Experimental performance analysis of a parallel connection of two 1200/80 MΩ silicon carbide SiC MOSFETs is presented. Static parallel connection was found to be unproblematic. The switching performance of several pairs of parallel-connected MOSFETs is shown employing a common simple totem-pole driver. Good transient current sharing and high-speed switching waveforms with small oscillations are presented. To conclude this analysis, a dc/dc boost converter using parallel-connected SiC MOSFETs is designed for stepping up a voltage from 50 V to 560 V. It has been found that at high frequencies, a mismatch in switching losses results in thermal unbalance between the devices.

  • 14.
    Sadik, Diane-Perle
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Lim, Jang-Kwon
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Ranstad, P.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Energy Conversion.
    Investigation of long-term parameter variations of SiC power MOSFETs2015In: Power Electronics and Applications (EPE’15 ECCE-Europe), 2015 17th European Conference on, IEEE , 2015, p. 1-10Conference paper (Refereed)
    Abstract [en]

    Experimental investigations on the gate-oxide and body-diode reliability of commercially available Silicon Carbide (SiC) MOSFETs from the second generation are performed. The body-diode conduction test is performed with a current density of 50 A/cm2 in order to determine if the body-diode of the MOSFETs is free from bipolar degradation. The second test is stressing the gate-oxide. A negative bias is applied on the gate oxide in order to detect and quantify potential drifts.

  • 15.
    Tolstoy, Georg
    et al.
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics.
    Peftitsis, Dimosthenis
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics.
    Lim, Jang-Kwon
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics.
    Bakowski, Mietek
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics.
    Nee, Hans-Peter
    KTH, School of Electrical Engineering (EES), Electrical Machines and Power Electronics.
    Circuit Modeling of Vertical Buried-Grid SiC JFETs2010In: SILICON CARBIDE AND RELATED MATERIALS 2009, PTS 1 AND 2   / [ed] Bauer AJ; Friedrichs P; Krieger M; Pensl G; Rupp R; Seyller T, 2010, Vol. 645-648, p. 965-968Conference paper (Refereed)
    Abstract [en]

    The main problem when the conventional PSpice JFET model is used to simulate a vertical short-channel buried-grid JFET is caused by the constant values of Threshold Voltage (VTO) and Transconductance (BETA). This paper presents a new model for the vertical short-channel buried-grid 1200V JEET, where both VTO and BETA vary with respect to the Drain-Source voltage. Simulation data from Medici have been analyzed in order to extract the analytical equations for VTO and BETA. Also other PSpice parameters are extracted from these data. The proposed circuit model has been simulated in Matlab by optimizing the same algorithm that PSpice uses. A variety of results are shown and discussed in this paper.

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