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  • 1.
    Farahini, Nasim
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Sohofi, Hassan
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Physical Design Aware System Level Synthesis of Hardware2015In: Proceedings - Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS), 2015, IEEE , 2015, p. 141-148Conference paper (Refereed)
    Abstract [en]

    In spite of decades of research, only a small percentage of hardware is designed using high-level synthesis because of the large gap between the abstraction levels of standard cells and algorithmic level. We propose a grid-based regular physical design platform composed of large grain hardened building blocks called SiLago blocks. This platform is divided into regions which are specialized for different functionalities like computation, storage, system control, etc. The characterized micro-architectural operations of the SiLago platform serve as the interface to meet-in-the-middle high-level and system-level syntheses framework. This framework was used to generate three hardware macro instances, derived from SiLago platform for three applications from signal processing domain. Results show two orders of magnitude improvements in efficiency of the system-level design space exploration and synthesis time, with average loss in design quality of 18% for energy and 54% for area compared to the commercial SOC flow.

  • 2.
    Farahini, Nasim
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tajammul, Muhammad Adeel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Shami, Muhammad Ali
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Guo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ye, Wei
    Huawei, Wireless Beijing Division, China.
    39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation2013In: 2013 IEEE International Symposium on Circuits and Systems (ISCAS), IEEE , 2013, p. 1448-1451Conference paper (Refereed)
    Abstract [en]

    This paper presents an industrial case study of using a Coarse Grain Reconfigurable Architecture (CGRA) for a multi-mode accelerator for two kernels: FFT for the LTE standard and the Correlation Pool for the UMTS standard to be executed in a mutually exclusive manner. The CGRA multi-mode accelerator achieved computational efficiency of 39.94 GOPS/watt (OP is multiply-add) and silicon efficiency of 56.20 GOPS/mm2. By analyzing the code and inferring the unused features of the fully programmable solution, an in-house developed tool was used to automatically customize the design to run just the two kernels and the two efficiency metrics improved to 49.05 GOPS/watt and 107.57 GOPS/mm2. Corresponding numbers for the ASIC implementation are 63.84 GOPS/watt and 90.91 GOPS/mm2. Though the ASIC’s silicon and computational efficiency numbers are slightly better, the engineering efficiency of the pre-verified/characterized CGRA solution is at least 10X better than the ASIC solution.

  • 3. Ge, C.
    et al.
    Jia, L.
    Zheying, L.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Connecting bridge in SoC used for wireless home healthcare system2008In: Int. Symp. Wirel. Pervasive Comput., ISWPC, Proc., 2008, p. 194-197Conference paper (Refereed)
    Abstract [en]

    A connection bridge for connection of two CPU systems in SoC of the HAB (healthcare apparatus on body/bed) in home healthcare wireless network is addressed. Multi CPU system in a SoC could be divided into different part according with data process function. Therefore the each part of the system can work independently without influence each other. With the discussion of the performance of HAB and home networking, the connection bridge is a suitable technology for reducing dies size and power consumption. The connection bridge designed in the paper connects two CPU systems and two digital circuitry components together. To the CPU system, common digital circuitry is a part of the CPU system with the bridge. The architecture and logic function of the connection bridge is analyzed in detail and simulated. The simulation results demonstrate that the connection bridge can not only supply the connection of two CPU and two common components, display module and RAM, but also increase the running speed and system performance.

  • 4.
    Jafari, Fahimeh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture2011In: Proceedings: 2011 14th Euromicro Conference on Digital System Design: Architectures, Methods and Tools, DSD 2011, 2011, p. 73-80Conference paper (Refereed)
    Abstract [en]

    We have proposed a Dynamically Reconfigurable Resource Array (DRRA), which is a Coarse Grain Reconfigurable Architecture (CGRA). In this paper, we propose a hierarchical method for compiling DSP applications in Simulink into DRRA. In this method, each function in DRRA library can be implemented in different architecture styles and also each architectural style can be implemented in varying degrees of parallelism. Since selecting an appropriate implementation for functions of an application is very effective in performance and cost of architecture, we also formulate an optimization problem that considers implementations of functions as decision variables in order to minimize total energy consumed in the architecture under performance and cost constraints. A realistic case study exhibits up to 89% reduction of total energy consumption. It is worth mentioning that by using the proposed hierarchically compilation method, the design space is reduced dramatically while keeping the solution optimized in term of energy consumption. Hence, the optimization algorithm has low run-time complexity, enabling quick exploration of large design spaces.

  • 5. Jia, L.
    et al.
    Li, Z.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    NoC architecture study with DFG model2010In: Proceedings - 2010 1st International Conference on Pervasive Computing, Signal Processing and Applications, PCSPA 2010, 2010, p. 903-906Conference paper (Refereed)
    Abstract [en]

    Generic reconfigurable network on chip (GRNoC) is an advanced technology of application specified SoC design for digital signal process system (DSPS). A novel GRNoC mapping method based on data flow graph (DFG) is addressed in this paper. For modules of heterogeneous processors, central memory, and IPs (intellectual properties), DFG model analysis shows that DFG model provides important data transmission properties included the direction and contents of data transmitting, requirements of synchronization and speed of data transmission. The DFG model combined with graph model of GRNoC, therefore, can be the base of route mapping design for the GRNoC. In addition, node architecture of simple router used in GRNoC is also proposed in this paper. The simple router can increases the properties of data transmission in GRNoC and is more suitable for mapping design with DFG model.

  • 6. Jia, L.
    et al.
    Zheying, L.
    Li, Shou
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    NoC design for the soc of image process system of road mark recognition2010In: Proceedings - International Conference on Electrical and Control Engineering, ICECE 2010, 2010, p. 3912-3916Conference paper (Refereed)
    Abstract [en]

    With the analysis of basic properties, this paper proposed a SoC design of Image Process System of Road Mark Recognition (IPSRMR) based on data flow graph (DFG) model and generic regulable NoC (GRNoC). It is provided of properties of data transmission and timing for each resource module with building the system DFG model with analyzing functions and algorithm. The basic method for optimizing resources and mapping is shown by analyzing DFG model of the IPSRMR. Following the analysis results of DFG, the SoC for IPSRMR has optimized GRNoC architecture, achieves shortest data transmission paths among the resources, implements straight data transmission, increases the speed of data transmission, and reduced the requirement for data process speed of each resource. In addition, the power consumption is reduced with such a optimized architecture.

  • 7.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    System-Level Architectural Hardware Synthesis for Digital Signal Processing Sub-Systems2015Doctoral thesis, monograph (Other academic)
    Abstract [en]

    This thesis presents a novel system-level synthesis framework called System-Level Architectural Synthesis Framework (SYLVA), which synthesizes DigitalSignal Processing (DSP) sub-systems modeled by synchronous data ?ow intohardware implementations in Application-Specific Integrated Circuit (ASIC),Field-Programmable Gate Array (FPGA) or Coarse-Grained ReconfigurableArchitecture (CGRA) style. SYLVA synthesizes in terms of pre-characterizedFunction Implementations (FIMPs). It explores the design space in threedimensions, number of FIMPs, type of FIMPs, and pipeline parallelism be-tween the producing and consuming FIMPs. SYLVA also introduces timingand interface model of FIMPs to enable reuse and automatic generation ofGlobal Interconnect and Control (GLIC) to glue the FIMPs together into aworking system. SYLVA has been evaluated by applying it to several realand synthetic DSP applications and the experimental results are analyzedfor the design space exploration, the GLIC synthesis, the code generation,and the CGRA floorplanning features. The conclusion from the experimentalresults is that by exploring the multi-dimensional design space in terms ofpre-characterized FIMPs, SYLVA explores a richer design space and does itmore effectively compared to the existing High-Level Synthesis (HLS) toolsto improve both engineering and computational efficiency.

  • 8.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Guo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A code reuse method for many-core coarse-grained reconfigurable architecture function library development2011In: 2011 International Symposium on Integrated Circuits, ISIC 2011, 2011, p. 512-515Conference paper (Refereed)
    Abstract [en]

    In this paper 1, a code reuse method is proposed to enhance the efficiency of the function library development of many core coarse-grained reconfigurable architecture. The method focuses on developing and using the precompiled ReCon-figurable Functions (RCFs) in the function library. By applying this method on the RCF development, functions are objectified like classes in any objective-oriented programming language. Using a function is to instantiate a selected RCF. Similar functions can be instantiated from the same RCF. Thus, the total number of RCFs to be compiled is reduced and the global programming efficiency is increased and the labor requirement for application development is reduced.

  • 9.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Farahini, Nasim
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Global control and storage synthesis for a system level synthesis approach2013In: Proceedings - 21st Annual International IEEE Symposium on Field-Programmable Custom Computing Machines, FCCM 2013, IEEE , 2013, p. 6546036-Conference paper (Refereed)
    Abstract [en]

    SYLVA is a System Level Architectural Synthesis Framework that translates Synchronous Data Flow (SDF) models of DSP sub-systems like modems and codecs into hardware implementation in ASIC/Standard Cells, FPGAs or CGRAs (Coarse Grain Reconfigurable Fabric).

  • 10.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Farahini, Nasim
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Rosvall, Kathrin
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    System level synthesis of hardware for DSP applications using pre-characterized function implementations2013In: 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), IEEE , 2013Conference paper (Refereed)
    Abstract [en]

    SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results.

  • 11.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Accurate and efficient three level design space exploration based on constraints satisfaction optimization problem solver2014In: Proceedings - 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, 2014Conference paper (Refereed)
  • 12.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Case Study: Constraint Programming in a System Level Synthesis Framework2014In: PRINCIPLES AND PRACTICE OF CONSTRAINT PROGRAMMING, CP 2014, 2014, p. 846-861Conference paper (Refereed)
    Abstract [en]

    This article presents a case study of using a constraint programming solver in a system level synthesis framework called SYLVA. The solver is used to find the repetition vector of a synchronous data flow graph and serving as the design space exploration engine, which rapidly finds qualified system implementations by solving a constraint satisfaction optimization problem. Each system implementation is a combination of a number of function implementation instances and their cycle accurate execution schedules. The problem to be solved is automatically generated based on the user inputs: 1) a system model to be synthesized, 2) a library containing all the usable function implementations, 3) the performance/cost constraints, and 4) the optimization objectives. Use of constraints programming technique enabled a low cost development of design space exploration engine in addition to gaining ease of use.

  • 13.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Global interconnect and control synthesis in system level architectural synthesis framework2013In: Proceedings - 16th Euromicro Conference on Digital System Design, DSD 2013, New York: IEEE , 2013, p. 11-17Conference paper (Refereed)
    Abstract [en]

    In this paper, we describe the procedure of the Global Interconnect and Control (GLIC) synthesis step in a system level synthesis framework to automatically generate GLIC logics from a scheduled SDF. The generated GLIC logics consist of control FSMs, interconnect and data buffers to glue existing function implementations to construct the system, which is modeled by the scheduled SDF. The experimental result shows that GLIC synthesis is able to generate compact (5.7%, 0.6% and 0.9% of area usage for three examples implemented in 65nm ASIC) control, interconnect and data buffers while saving huge amount of manual effort and time (0.5s, 2.4s and 4.3s run time on a 2.8GHz x86 microprocessor for the three examples).

  • 14.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Memory allocation and optimization in system-level architectural synthesis2013In: 2013 8th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip, ReCoSoC 2013, New York: IEEE , 2013, p. 6581537-Conference paper (Refereed)
    Abstract [en]

    In this paper, we present a novel approach to optimally allocate memory resources in a system-level synthesis flow, which converts a dataflow style system description (synchronous data flow) into the register-transfer level description in the specified implementation style (ASIC, FPGA or CGRA). The first problem is encountered by the synthesis flow is that since it covers different implementation styles, a generic model is required to support resource allocation and optimization. The second problem is the memory allocation method to optimally allocate memory resources in the RTL model. The contribution of this paper has two parts, which are 1) a generic memory model for different memory architectures in ASIC, FPGA and CGRA, and 2) a memory allocation and optimization method for optimally allocating storage elements in the intermediate representation with actual implementations (e.g. on-chip SRAM for ASIC, memory controller and off-chip SDRAM for FPGA). The memory allocation method is an implementation style dependent procedure and has three steps: architecture independent optimization, resource allocation and architecture depended optimization. The experimental result shows that the proposed method is efficient and effective. The automatically generated implementation uses only approximately 4% more resources compared to manual implementation. The fast and automatic memory allocation method enables fast design space exploration that requires little effort form the system designer.

  • 15.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Three-Dimensional Design Space Exploration for System Level Synthesis2014In: 2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, p. 419-426Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose an efficient and effective three-dimensional design space exploration method for mapping a DSP system in synchronous data flow graph format onto an RTL or lower level hardware description using constraint programming. The three dimensions are 1) schedule level parallelism (The parallelism of the executions for one DSP function, fully parallel, semi-parallel or fully serial), 2) function level parallelism (how many function implementations are used to implement each of the DSP functions), and 3) arithmetic level parallelism (how the function implementations are implemented). The design space exploration problem is formulated as a constraints satisfaction optimization problem and solved by the constraint programming solver in Google's or-tools. The proposed method is compared against two state-of-the-art commercial HLS tools for four realistic examples and one synthetic example. The metrics compared are runtime, accuracy and quality of results in terms of resource usage. We show on average, the proposed method is 85.22% faster compared to HLS tools, 4.3% more accurate and 8.27% better in quality of results. For the latter we have conservatively assumed the same function execution parallelism.

  • 16.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jafari, Fahimeh
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Shashi
    Department of Electronics and Computer Engineering, School of Engineering, Jönköping University.
    Layered Spiral Algorithm for memory-aware mapping and scheduling on Network-on-Chip2010In: 28th Norchip Conference, NORCHIP 2010, 2010Conference paper (Refereed)
    Abstract [en]

    In this paper, Layered Spiral Algorithm (LSA) is proposed for memory-aware application mapping and scheduling onto Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC). The energy consumption is optimized while keeping high task level parallelism. The experimental evaluation indicates that if memory-awareness is not considered during mapping and scheduling, memory overflows may occur. The underlying problem is also modeled as a Mixed Integer Linear Programming (MILP) problem and solved using an efficient branch-and-bound algorithm to compare optimal solutions with results achieved by LSA. Comparing to MILP solutions, the LSA results demonstrate only about 20% and 12% increase of total communication cost in case of a small and middle size synthetic problem, respectively, while it is order of magnitude faster than the MILP solutions. Therefore, the LSA can find acceptable total communication cost with a low run-time complexity, enabling quick exploration of large design spaces, which is infeasible for exhaustive search.

  • 17.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Malik, Jamshaid Sarwar
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Liu, Shaoteng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA2013In: MES '13 Proceedings of the First International Workshop on Many-core Embedded Systems, ACM , 2013, p. 25-32Conference paper (Refereed)
    Abstract [en]

    This paper presents a code generation method that translates an intermediate Register-Transfer Level (RTL) model of a system into its corresponding VHDL code for ASIC and FPGAs and MATLAB functions for manycores CGRAs. The intermediate representation consists of Function Implementation (FIMPs) and the glue logic. FIMPs are VHDL design units for the ASIC and FPGA implementation styles and MATLAB function templates for the CGRA implementation style, while the glue logic is a compact data structure storing Global Interconnect and Control (GLIC) information. The automatically generated implementation codes increase the resource usage by 1.5% on the average while reducing total design effort by two orders of magnitudes.

  • 18.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Malik, Omer
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Automatic test program generation framework for NoC-based MPSoC compiler validation2011In: 2011 International Conference on Instrumentation, Measurement, Circuits and Systems (ICIMCS 2011), vol 1: Instrumentation, Measurement, Circuits and Systems, New York: Amer Soc Mechanical Engineers , 2011, p. 99-103Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a systematic method (a framework) for automatic test program generation for Network-on-Chip (NoC) based Multi-Processor System-on-Chip (MPSoC) compiler validation. This framework consists of three parts: specification reader, program generator and platform simulator. By applying this framework, specified test programs for compiler validation are automatically generated as well as their corresponding run time results. The validation productivity is enhanced and the expertise requirement is reduced. We also present an example tool called Automatic VESYLA Generator (AVG) implementing this framework. This tool is used in the Dynamic Reconfigurable Resource Array (DRRA) assembler development in our research group. The experiment shows that on a personal PC, AVG tool generates bug-free test programs more than 100 times faster than a human programmer.

  • 19. Li, Z.
    et al.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ma, M.
    ECG signal generator design based on DFG model2006In: 2006 8th International Conference on Signal Processing: Volume 4, IEEE , 2006, p. 3245-3248Conference paper (Refereed)
    Abstract [en]

    ECG signals model described by data flow graph (DFG) is addressed in this paper. The model is built on the time processing. The principle of DFG modeling method for ECG signal is based on the idea of ECG time interval. According to the data processing flow, the each wave could be considered as a piece of ECG signal and the pieces could be processed in time sequence. According to the model, the time characters and parameters could be processed by the algorithm. The model is also useful for the design of ECG signal generator.

  • 20. Li, Z.
    et al.
    Liu, J.
    Lv, C.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Data compression and life signal acquisition SoC design2008Conference paper (Refereed)
    Abstract [en]

    A simple data compression method used for designing of SoC architecture of life signal acquisition is proposed in this paper. The health service is an important part of home network following the development of information technology. Considering the parameters of each life signal for information analysis the re-sampling method can be used as a compression method. Re-sampling method is not complex and can be implemented with simple circuit. The SoC is used for a health service system in the home network. The advantage of the method is of a SoC with low power consumption.

  • 21. Li, Z.
    et al.
    Liu, J.
    Wang, S.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    SoC model analysis for ECG data acquisition with wireless sensor network2009In: 3rd International Conference on Bioinformatics and Biomedical Engineering, iCBBE 2009, 2009, p. 1276-1279Conference paper (Refereed)
    Abstract [en]

    Mixed signal SoC for ECG waveform acquisition is designed and discussed in this paper. The SoC is a terminal of a special wireless sensor network (WSN) as a data source. Time parameters and communication band width are discussed. Especially, to satisfy the requirements of ECG waveform data acquisition and transmission the relation of sampling rate and communication band width is discussed. Based on the analysis of ECG frequency characteristics and the real time requirements of the WSN, synchronous data acquisition and transmission architecture of the SoC is designed. The DFG (Data flow graphic) model of the architecture is built for time parameters analysis and circuits design as well.

  • 22. Li, Z.
    et al.
    Luo, L.
    Li, Shou
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Design for mixed-signal SoC with IPv4 for embedded instruments2007In: 2007 8th International Conference on Electronic Measurement and Instruments, ICEMI, IEEE , 2007, p. 269-273Conference paper (Refereed)
    Abstract [en]

    A SoC architecture used for with 8-bit CPU and IPv4 hardware is designed in this paper. The SoC is designed for embedded instrument. In additional, to according with the information transmission requirement of smart control system, the function of IPv4 is simplified to reduce the hardware. A function model used for model checking is also given. The function model is very simple and easy to be used in practice because we only take care about the transceiver function of IPv4 hardware.

  • 23. Li, Z.
    et al.
    Lv, C.
    Liu, J.
    Lu, M.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    SoC architecture with a switch bridge for wireless ECG data acquisition2009In: 2009 1st International Conference on Information Science and Engineering, ICISE 2009, 2009, p. 3701-3704Conference paper (Refereed)
    Abstract [en]

    NoC architecture with a switch bridge is designed for mixed signal SoC of the ETB (ECG T on body) applied in home healthcare wireless network. The SoC including multi CPU systems can be divided into different parts with data process function. Therefore each part of the system can work independently without influence each other. With the discussion of the performances of ETB, the switch bridge is a suitable NoC (network on chip) technology for reducing the dies size and power consumption. The switch bridge designed in this paper connects two CPU systems and two others digital circuitry components together. To the CPU systems, common digital circuitry is a part of the CPU system with the bridge. The architecture and logic function of the switch bridge is analyzed in detail and simulated. The simulation results demonstrate that the connection bridge can not only supply the connection of two CPU and two common modules, include display module and RAM, but also increased the running speed and system performance.

  • 24. Li, Z.
    et al.
    Xiu, L.
    Liu, J.
    Lv, C.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Error analysis of integrated resistor attenuation network2010In: Proceedings - International Conference on Electrical and Control Engineering, ICECE 2010, 2010, p. 3714-3717Conference paper (Refereed)
    Abstract [en]

    The model and synthesis method of integrated linear attenuation network (LAC) used in mixed signal SoC for digital instrument are addressed in this paper. The model and synthesis method of the LAC used for electronics instrument is related with the application and implementation method. To the signal generator used in some electronics instrument, the LAC architecture could be linear and synthesized by resistor network and some additional circuits. Therefore, the spectrum properties of the LAC are relayed on the spectrum properties of additional circuits. The synthesis method is derived the formula of the LAC model. With the model, the integrated resistor network in the LAC used for measurement circuit module could be reduced. The LAC architecture synthesis method is suitable for the application of implementing a LAC with integrated circuit technology.

  • 25. Li, Zheying
    et al.
    Jia, L.
    Li, Shou
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    NoC design with DFG model for DSPS2010In: Proceedings - International Conference on Electrical and Control Engineering, ICECE 2010, 2010, p. 3917-3920Conference paper (Refereed)
    Abstract [en]

    The mapping design of network on chip (NoC) is one of the cores of SoC design for digital signal process system (DSPS). A NoC mapping method based on data flow graph (DFG) is addressed in this paper. For modules of heterogeneous processors, central memory, and IPs (intellectual properties), DFG model analysis shows that DFG model provides important data transmission properties included the direction and contents of data transmitting, requirements of synchronization and speed of data transmission. The DFG model, therefore, can be the base of route mapping design for the NoC. In addition, node architecture of simple router used in generic regulable NoC (GRNoC) is also proposed in this paper. The simple router can increases the properties of data transmission in NoC and is more suitable for mapping design with DFG model.

  • 26. Liu, J.
    et al.
    Lv, C.
    Li, Z.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Switch bridge architecture of NoC for wireless ECG data acquisition2009In: 3rd International Conference on Bioinformatics and Biomedical Engineering, iCBBE 2009, 2009, p. 887-890Conference paper (Refereed)
    Abstract [en]

    A switch bridge is addressed for the interconnection of two CPU systems in the SoC of the ETB (ECG terminal on body) in home healthcare wireless network. The SoC including multi CPU systems can be divided into different parts with data process function. Therefore each part of the system can work independently without influence each other. With the discussion of the performances of HAB and home networking, the switch bridge is a suitable technology for reducing the dies size and power consumption. The switch bridge designed in this paper connects two CPU systems and two others digital circuitry components together. To the CPU systems, common digital circuitry is a part of the CPU system with the bridge. The architecture and logic function of the switch bridge is analyzed in detail and simulated. The simulation results demonstrate that the connection bridge can not only supply the connection of two CPU and two common components, include display module and RAM, but also increased the running speed and system performance.

  • 27. Liu, Y.
    et al.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, Z.
    Prototyping distributed embedded operating system for NoC architecture2010In: 2nd International Conference on Information Science and Engineering, ICISE2010 - Proceedings, 2010, p. 6781-6784Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a light-weighted embedded OS (EOS) for 8051 microcontrollers used in NoC. This EOS is developed in such way that it is able to be extended as a distributed OS for NoC. Along with the development of the NoC, an operating system is demanded for managing resources and task execution flow in computing systems based on NoC architecture. To build the EOS suitable for small C51 core, the model of the EOS is built and discussed first in this paper. With the model, the structure of the EOS mainly involves multi-task management and inter-task communication. Then we verify the model. By reserve interfaces, the tasks in distributed EOS are expected to communication with each other among NoC system via routers.

  • 28. Luo, L.
    et al.
    Li, Z.
    Li, Shou
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    DFG model of real time character for instruments designed with embedded system2007In: 2007 8th International Conference on Electronic Measurement and Instruments, ICEMI, IEEE , 2007, p. 4830-4833Conference paper (Refereed)
    Abstract [en]

    A modeling method for analyzing the real time character of the instruments design with embedded technology was addressed in this paper. Analyzing and verifying of real time property in the instruments with embedded technology design is a crucial challenge. An analog and digital co-analysis method was given after the discussion for describing the real time property of an embedded system with time factors' set. And also, the data flow graph (DFG) is used in the modeling processing. At last of the paper, it is shown that the real time model could be used in mixed-signal SoC design.

  • 29. Luo, L.
    et al.
    Li, Z.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Consistency testing of IP in mixed-signal SoC2007In: 2007 8th International Conference on Electronic Measurement and Instruments, ICEMI, IEEE , 2007, p. 265-268Conference paper (Refereed)
    Abstract [en]

    Based on the discussion, on the consistency description method used for SoC design, the testing method about the operation consistency of IP (Intellectual Property) blocks is addressed in this paper. The method proposed the guidance for designing the test vectors in mixed signal SoC design. With the method, logical description of operation consistency specification can be built in SoC design. This paper indicates that operation consistency design is a key point and will impact both architecture of hardware and software.

  • 30. Luo, L.
    et al.
    Li, Z.
    Zhao, J.
    Li, Shuo
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Safety model of on-line electronic instrument based on embedded system2006In: 2006 8th International Conference on Signal Processing: Volume 4, IEEE , 2006, p. 3249-3252Conference paper (Refereed)
    Abstract [en]

    The safety model of electronics instrument and circuit control over Internet or local network is built in this paper. In industrial area, to keep instrument and circuit in safety is very important. Safety problem is discussed in detail as the base of safety problem description. The safety problem is summarized as denying dangerous operation of executing rules of control commands. A model for the commands executing relation and sequence is built in this paper. To build the model, the executing conditions for each command should be established at first. Based on the executing conditions the relation of different commands could be built. The safety model can be used for the operation safety checking. This model and safety problem description method also can be used for electronic instrument and circuit with embedded architecture.

  • 31. Zheying, L.
    et al.
    Chaxia, L. J. L.
    Shuo, Li
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Study on pervasive computing architecture of electronic instrument2009In: ICIEA 2009. 4th IEEE Conference on Industrial Electronics and Applications, IEEE , 2009, p. 3969-3972Conference paper (Refereed)
    Abstract [en]

    A novel model and architecture of measurement bus system and/or electronic instrument for pervasive computing network are proposed in this paper. With DFG model analysis for measurement bus system and electronic instrument, it is checked for the ability of network communication of measurement bus system and electronic instrument. As the results of model analysis, the bottleneck for data communication of the bus and the instrument is the communication architecture. To meet the requirement of pervasive computing network a communication unit is added on data acquisition subsystem in the bus system and instrument. Such a measurement bus system and/or instrument can satisfy pervasive computing network and make a strong and smart measurement and control system without increase the complexity and memory size requirement of measurement bus system and instrument.

1 - 31 of 31
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