Change search
Refine search result
1 - 20 of 20
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1. Ayala, Christopher L.
    et al.
    Grogg, Daniel
    Bazigos, Antonios
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fernandez-Bolanos, Montserrat
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Hagleitner, Christoph
    Nanoelectromechanical digital logic circuits using curved cantilever switches with amorphous-carbon-coated contacts2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 113, p. 157-166Article in journal (Refereed)
    Abstract [en]

    Nanoelectromechanical (NEM) switches have the potential to complement or replace traditional CMOS transistors in the area of ultra-low-power digital electronics. This paper reports the demonstration of prototype circuits including the first 3-stage ring oscillator built using cell-level digital logic elements based on curved NEM switches. The ring oscillator core occupies an area of 30 mu m x 10 mu m using 6 NEM switches. Each NEM switch device has a footprint of 5 mu m x 3 mu m, an air gap of 60 mu m and is coated with amorphous carbon (a-C) for reliable operation. The ring oscillator operates at a frequency of 6.7 MHz, and confirms the simulated inverter propagation delay of 25 ns. The successful fabrication and measurement of this demonstrator are key milestones on the way towards an optimized, scaled technology with sub-nanosecond switching times, lower operating voltages and VLSI implementation.

  • 2.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Heterogeneous 3D Integration and Packaging Technologies for Nano-Electromechanical Systems2017Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Three-dimensional (3D) integration of micro- and nano-electromechanical systems (MEMS/NEMS) with integrated circuits (ICs) is an emerging technology that offers great advantages over conventional state-of-the-art microelectronics. MEMS and NEMS are most commonly employed as sensor and actuator components that enable a vast array of functionalities typically not attainable by conventional ICs. 3D integration of NEMS and ICs also contributes to more compact device footprints, improves device performance, and lowers the power consumption. Therefore, 3D integration of NEMS and ICs has been proposed as a promising solution to the end of Moore’s law, i.e. the slowing advancement of complementary metal-oxide-semiconductor (CMOS) technology.In this Ph.D. thesis, I propose a comprehensive fabrication methodology for heterogeneous 3D integration of NEM devices directly on top of CMOS circuits. In heterogeneous integration, the NEMS and CMOS components are fully or partially fabricated on separate substrates and subsequently merged into one. This enables process flexibility for the NEMS components while maintaining full compatibility with standard CMOS fabrication. The first part of this thesis presents an adhesive wafer bonding method using ultra-thin intermediate bonding layers which is utilized for merging the NEMS components with the CMOS substrate. In the second part, a novel NEM switch concept is introduced and the performance of CMOS-integrated NEM switch circuits for logic and computation applications is discussed. The third part examines two different packaging approaches for integrated MEMS and NEMS devices with either hermetic vacuum cavities or low-cost glass lids for optical applications. Finally, a novel fabrication approach for through silicon vias (TSVs) by magnetic assembly is presented, which is used to establish an electrical connection from the packaged devices to the outside world.

  • 3.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Dubois, Valentin J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Ottonello Briano, Floria
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Adhesive Wafer Bonding for Heterogeneous System Integration2018In: ECS Meeting Abstracts / [ed] The Electrochemical Society, 2018Conference paper (Refereed)
  • 4.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Dubois, Valentin
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Schröder, Stephan
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Adhesive wafer bonding with ultra-thin intermediate polymer layers2017In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 260, p. 16-23Article in journal (Refereed)
    Abstract [en]

    Wafer bonding methods with ultra-thin intermediate bonding layers are critically important in heterogeneous 3D integration technologies for many NEMS and photonic device applications. A promising wafer bonding approach for 3D integration is adhesive bonding. So far however, adhesive bonding processes relied on relatively thick intermediate adhesive layers. In this paper, we present an adhesive wafer bonding process using an ultra-thin intermediate adhesive layer with sub-200 nm thickness. We demonstrate adhesive bonding of silicon wafers with a near perfect bonding yield of >99% and achieve less than ±10% non-uniformity of the intermediate layer thickness across an entire 100 mm-diameter wafer. A bond strength of 4.8 MPa was measured for our polymer adhesive, which is considerably higher than previously reported for other ultra-thin film adhesives. Additionally, the adhesive polymer used in the proposed method features excellent chemical and mechanical stability. We also report on a potential strategy for mitigating the formation of micro-voids in the polymer adhesive at the bond interface. Furthermore, the polymer adhesive can be sacrificially removed by oxygen plasma etching for both isotropic and anisotropic release etching. The characteristics of the adhesive wafer bonding process and its compatibility with CMOS wafers, makes it very attractive for heterogeneous 3D integration processes targeted at CMOS-integrated NEMS and photonic devices.

  • 5.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Karlsruhe Institute of Technology (KIT), Germany.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    High-speed Metal-filling of Through-Silicon Vias (TSVs) by Parallelized Magnetic Assembly of Micro-Wires2016In: 2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS), Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 577-580Conference paper (Refereed)
    Abstract [en]

    This work reports a parallelized magnetic assembly method for scalable and cost-effective through-silicon via (TSV) fabrication. Our fabrication approach achieves high throughput by utilizing multiple magnets below the substrate to assemble TSV structures on many dies in parallel. Experimental results show simultaneous filling of four arrays of TSVs on a single substrate, with 100 via-holes each, in less than 20 seconds. We demonstrate that increasing the degree of parallelization by employing more assembly magnets below the substrate has no negative effect on the TSV filling speed or yield, thus enabling scaled-up TSV fabrication on full wafer-level. This method shows potential for industrial application with an estimated throughput of more than 70 wafers per hour in one single fabrication module. Such a TSV fabrication process could offer shorter processing times as well as higher obtainable aspect ratios compared to conventional TSV filling methods.

  • 6.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Shah, Umer
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Somjit, Nutapong
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Oberhammer, Joachim
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires2015In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 5, no 1, p. 21-27Article in journal (Refereed)
    Abstract [en]

    In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.

  • 7.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Visser Taklo, Maaike Margrete
    Department of Instrumentation, SINTEF ICT, Norway.
    Lietaer, Nicolas
    Department of Microsystems and Nanotechnology, SINTEF ICT, Norway.
    Vogl, Andreas
    Department of Microsystems and Nanotechnology, SINTEF ICT, Norway.
    Bakke, Thor
    Department of Microsystems and Nanotechnology, SINTEF ICT, Norway.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding2016In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 7, no 10, p. 192-Article in journal (Refereed)
    Abstract [en]

    Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS) transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS) compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  • 8.
    Dubois, Valentin J.
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Scalable Manufacturing of Nanogaps2018In: Advanced Materials, ISSN 0935-9648, E-ISSN 1521-4095, Vol. 30, no 46, article id 1801124Article, review/survey (Refereed)
    Abstract [en]

    The ability to manufacture a nanogap in between two electrodes has proven a powerful catalyst for scientific discoveries in nanoscience and molecular electronics. A wide range of bottom-up and top-down methodologies are now available to fabricate nanogaps that are less than 10 nm wide. However, most available techniques involve time-consuming serial processes that are not compatible with large-scale manufacturing of nanogap devices. The scalable manufacturing of sub-10 nm gaps remains a great technological challenge that currently hinders both experimental nanoscience and the prospects for commercial exploitation of nanogap devices. Here, available nanogap fabrication methodologies are reviewed and a detailed comparison of their merits is provided, with special focus on large-scale and reproducible manufacturing of nanogaps. The most promising approaches that could achieve a breakthrough in research and commercial applications are identified. Emerging scalable nanogap manufacturing methodologies will ultimately enable applications with high scientific and societal impact, including high-speed whole genome sequencing, electromechanical computing, and molecular electronics using nanogap electrodes.

  • 9.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires2012In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 10, p. 105001-Article in journal (Refereed)
    Abstract [en]

    Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

  • 10.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Somjit, Nutapong
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    high aspect ratio tsvs fabricated by magnetic self-assembly of gold-coated nickel wires2012In: Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, IEEE conference proceedings, 2012, p. 541-547Conference paper (Refereed)
    Abstract [en]

    Three-dimensional (3D) integration is an emerging technologythat vertically interconnects stacked dies of electronics and/orMEMS-based transducers using through silicon vias (TSVs).TSVs enable the realization of devices with shorter signal lengths,smaller packages and lower parasitic capacitances, which can resultin higher performance and lower costs of the system. Inthis paper we demonstrate a new manufacturing technology forhigh-aspect ratio (> 8) through silicon metal vias using magneticself-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enablesthrough-wafer vias with high aspect ratios and superior electricalcharacteristics. This technique eliminates common issues inTSV fabrication using conventional approaches, such as the metaldeposition and via insulation and hence it has the potential to reducesignificantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications.

  • 11.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES).
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Integrating MEMS and ICs2015In: Microsystems & Nanoengineering, ISSN 2055-7434, Vol. 1, no 1, p. 1-16, article id 15005Article, book review (Refereed)
    Abstract [en]

    The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than-Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

  • 12. Grogg, Daniel
    et al.
    Ayala, Christopher L.
    Drechsler, Ute
    Sebastian, A.
    Koelmans, W. W.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fernandez-Bolanos, Montserrat
    Hagleitner, Christoph
    Despont, Michel
    Duerig, Urs T.
    Amorphous carbon active contact layer for reliable nanoelectromechanical switches2014In: 2014 IEEE 27th International Conference on Micro Electro Mechanical Systems (MEMS), IEEE conference proceedings, 2014, p. 143-146Conference paper (Refereed)
    Abstract [en]

    This paper reports an amorphous carbon (a-C) contact coating for ultra-low-ower curved nanoelectromechanical (NEM) switches. a-C addresses important problems in miniaturization and low-ower operation of mechanical relays: i) the surface energy is lower than that of metals, ii) active formation of highly localized a-C conducting filaments offers a way to form nanoscale contacts, and iii) high reliability is achieved through the excellent wear properties of a-C, demonstrated in this paper with more than 100 million hot switching cycles. Finally, a full inverter using a-C contacts is fabricated to demonstrate the viability of the concept.

  • 13.
    Laakso, Miku
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Liljeholm, Jessica
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB.
    Mårtensson, Gustaf
    Mycronic AB.
    Asiatici, Mikhail
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. EPFL École polytechnique fédérale de Lausanne, Processor Architecture Laboratory.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Ebefors, Thorbjörn
    Silex Microsystems AB.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Through-Glass Vias for MEMS Packaging2018Conference paper (Other academic)
    Abstract [en]

    Novelty / Progress Claims We have developed a new method for fabrication of through-glass vias (TGVs). The method allows rapid filling of via holes with metal rods both in thin and thick glass substrates.

    Background Vertical electrical feedthroughs in glass substrates, i.e. TGVs, are often required in wafer-scale packaging of MEMS that utilizes glass lids. The current methods of making TGVs have drawbacks that prevent the full utilization of the excellent properties of glass as a package material, e.g. low RF losses. Magnetic assembly has been used earlier to fabricate through-silicon vias (TSVs), and in this work we extend this method to realize TGVs [1].

    Methods The entire TGV fabrication process is maskless, and the processes used include: direct patterning of wafer metallization using femtosecond laser ablation, magnetic-fieldassisted self-assembly of metal wires into via holes, and solder-paste jetting of bump bonds on TGVs.

    Results We demonstrate that: (1) the magnetically assembled TGVs have a low resistance, which makes them suitable even for low-loss and high-current applications; (2) the magneticassembly process can be parallelized in order to increase the wafer-scale fabrication speed; (3) the magnetic assembly produces void-free metal filling for TGVs, which allows solder placement directly on top of the TGV for the purpose of high integration density; and (4) good thermal-expansion compatibility between TGV metals and glass substrates is possible with the right choice of materials, and several suitable metals-glass pairs are identified for possible improvement of package reliability [2].

    [1] M. Laakso et al., IEEE 30th Int. Conf. on MEMS, 2017. DOI:10.1109/MEMSYS.2017.7863517

    [2] M. Laakso et al., “Through-Glass Vias for Glass Interposers and MEMS Packaging Utilizing Magnetic Assembly of Microscale Metal Wires,” manuscript in preparatio

  • 14.
    Laakso, Miku J.
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Liljeholm, Jessica
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Mårtensson, Gustaf E.
    Mycronic AB, S-18353 Taby, Sweden..
    Asiatici, Mikhail
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Ecole Polytech Fed Lausanne, Sch Comp & Commun Sci, CH-1015 Lausanne, Switzerland..
    Fischer, Andreas C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Ebefors, Thorbjorn
    Silex Microsyst AB, S-17543 Jarfalla, Sweden.;MyVox AB, S-12938 Hagersten, Sweden..
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires2018In: IEEE Access, E-ISSN 2169-3536, Vol. 6, p. 44306-44317Article in journal (Refereed)
    Abstract [en]

    A through-glass via (TGV) provides a vertical electrical connection through a glass substrate. TGVs are used in advanced packaging solutions, such as glass interposers and wafer-level packaging of microelectromechanical systems (MEMS). However, TGVs are challenging to realize because via holes in glass typically do not have a sufficiently high-quality sidewall profile for super-conformal electroplating of metal into the via holes. To overcome this problem, we demonstrate here that the via holes can instead be filled by magnetically assembling metal wires into them. This method was used to produce TGVs with a typical resistance of 64 m Omega, which is comparable with other metal TGV types reported in the literature. In contrast to many TGV designs with a hollow center, the proposed TGVs can be more area efficient by allowing solder bump placement directly on top of the TGVs, which was demonstrated here using solder-paste jetting. The magnetic assembly process can be parallelized using an assembly robot, which was found to provide an opportunity for increased wafer-scale assembly speed. The aforementioned qualities of the magnetically assembled TGVs allow the realization of glass interposers and MEMS packages in different thicknesses without the drawbacks associated with the current TGV fabrication methods.

  • 15.
    Niklaus, Frank
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Dubois, Valentin
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Fischer, Andreas
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Grogg, Daniel
    Despont, Michel
    Wafer-level heterogeneous 3D integration for MEMS and NEMS2012In: Proceedings of 2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2012, IEEE conference proceedings, 2012, p. 247-252Conference paper (Refereed)
    Abstract [en]

    In this paper the state-of-the-art in wafer-level heterogeneous 3D integration technologies for micro-electromechanical systems (MEMS) and nano-electromechanical systems (NEMS) is reviewed. Various examples of commercial and experimental heterogeneous 3D integration processes for MEMS and NEMS devices are presented and discussed.

  • 16.
    Qin, Tian
    et al.
    Department of Electrical and Electronic Engineering, University of Bristol.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Rana, Sunil
    Department of Electrical and Electronic Engineering, University of Bristol.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Pamunuwa, Dinesh
    Department of Electrical and Electronic Engineering, University of Bristol.
    Performance Analysis of Nanoelectromechanical Relay-Based Field-Programmable Gate Arrays2018In: IEEE Access, E-ISSN 2169-3536, Vol. 6, p. 15997-16009Article in journal (Refereed)
    Abstract [en]

    The energy consumption of field-programmable gate arrays (FPGA) is dominated by leakage currents and dynamic energy associated with programmable interconnect. An FPGA built entirely from nanoelectromechanical (NEM) relays can effectively eliminate leakage energy losses, reduce the interconnect dynamic energy, operate at temperatures >225 °C and tolerate radiation doses in excess of 100 Mrad, while hybrid FPGAs comprising both complementary metal-oxide-semiconductor (CMOS) transistors and NEM relays (NEM-CMOS) have the potential to realize improvements in performance and energy efficiency. Large-scale integration of NEM relays, however, poses a significant engineering challenge due to the presence of moving parts. We discuss the design of FPGAs utilizing NEM relays based on a heterogeneous 3-D integration scheme, and carry out a scaling study to quantify key metrics related to performance and energy efficiency in both NEM-only and NEM-CMOS FPGAs. We show how the integration scheme has a profound effect on these metrics by changing the length of global wires. The scaling regime beyond which net performance and energy benefits is seen in NEM-CMOS over a baseline 90 nm CMOS technology is defined by an effective relay beam length of 0.5 μm , on-resistance of 200 kΩ , and a via pitch of 0.4 μm , all achievable with existing process technology. For ultra-low energy applications that are not performance critical, NEM-only FPGAs can provide close to 15× improvement in energy efficiency.

  • 17.
    Rana, Sunil
    et al.
    University of Bristol.
    Mouro, João
    University of Bristol.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Micro and Nanosystems.
    Reynolds, Jamie D.
    University of Southampton.
    Chong, Harold M. H.
    University of Southampton.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Micro and Nanosystems.
    Pamunuwa, Dinesh
    University of Bristol.
    Nanoelectromechanical relay without pull-in instability for high-temperature non-volatile memory2020In: Nature Communications, ISSN 2041-1723, E-ISSN 2041-1723, Vol. 11, no 1, article id 1181Article in journal (Refereed)
    Abstract [en]

    Emerging applications such as the Internet-of-Things and more-electric aircraft require electronics with integrated data storage that can operate in extreme temperatures with high energy efficiency. As transistor leakage current increases with temperature, nanoelectromechanical relays have emerged as a promising alternative. However, a reliable and scalable non-volatile relay that retains its state when powered off has not been demonstrated. Part of the challenge is electromechanical pull-in instability, causing the beam to snap in after traversing a section of the airgap. Here we demonstrate an electrostatically actuated nanoelectromechanical relay that eliminates electromechanical pull-in instability without restricting the dynamic range of motion. It has several advantages over conventional electrostatic relays, including low actuation voltages without extreme reduction in critical dimensions and near constant actuation airgap while the device moves, for improved electrostatic control. With this nanoelectromechanical relay we demonstrate the first high-temperature non-volatile relay operation, with over 40 non-volatile cycles at 200 °C.

  • 18.
    Wang, Xiaojing
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Antelius, Mikael
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Narrow footprint copper sealing rings for low-temperature hermetic wafer-level packaging2017In: TRANSDUCERS 2017 - 19th International Conference on Solid-State Sensors, Actuators and Microsystems, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 423-426, article id 7994077Conference paper (Refereed)
    Abstract [en]

    This paper reports a narrow footprint sealing ring design for low-temperature, hermetic, and mechanically stable wafer-level packaging. Copper (Cu) sealing rings that are as narrow as 8 μm successfully seal the enclosed cavities on the wafers after bonding at a temperature of 250 °C. Different sealing structure designs are evaluated and demonstrate excellent hermeticity after 3 months of storage in ambient atmosphere. A leak rate of better than 3.6×10'16 mbarL/s is deduced based on results from residual gas analysis measurements. The sealing yield after wafer bonding is found to be not limited by the Cu sealing ring width but by a maximum acceptable wafer-to-wafer misalignment.

  • 19.
    Wang, Xiaojing
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Antelius, Mikael
    APR Technologies AB.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Wafer-level vacuum packaging enabled by plastic deformation and low-temperature welding of copper sealing rings with a small footprint2017In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 26, no 2, p. 357-365, article id 7845563Article in journal (Refereed)
    Abstract [en]

    Wafer-level vacuum packaging is vital in the fabrication of many microelectromechanical systems (MEMS) devices and enables significant cost reduction in high-volume MEMS production. In this paper, we propose a low-temperature wafer-level vacuum packaging method based on plastic deformation and low-temperature welding of copper sealing rings with a small footprint. A device wafer with copper ring structures and a cap wafer with corresponding metalized grooves are placed inside a vacuum chamber and pressed together at a temperature of 250 ̊C, resulting in low-temperature welding of the copper, and thus, hermetic sealing of the cavities enclosed by the sealing rings. The vacuum pressure inside the fabricated cavities 146 days after bonding was measured using residual gas analysis to be as low as 2.6×10-2 mbar. Based on this value, the leak rate is calculated to be smaller than 3.6×10-16 mbarL/s using the most conservative assumptions, demonstrating the excellent hermeticity of the seals. Shear testing was used to demonstrate that the seals are mechanically stable with over 90 MPa in shear strength for 5.2 μm-high Cu sealing rings with widths down to 8 μm. The reported method is potentially compatible with complementary metaloxide-semiconductor (CMOS) substrates and may be applied to vacuum packaging of 3-D heterogeneously integrated MEMS on state-of-the-art CMOS substrates.

  • 20.
    Wang, Xiaojing
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Edinger, Pierre
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Errando-Herranz, Carlos
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Gylfason, Kristinn
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages2019In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 28, no 3, p. 460-471Article in journal (Refereed)
    Abstract [en]

    Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electro-mechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a wafer-level vacuum packaging method featuring transfer bonding of 25-μm-thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold-aluminum (Au-Al) thermo-compression bonding at a low temperature of 250 °C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 μm, respectively. Despite the small sealing footprint, the Si caps with 9-μm-wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than 2.8x10-14 mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 μm by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip-chip interfaces, thereby avoiding the need of through-cap-vias in conventional MEMS packages.

1 - 20 of 20
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf