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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density2016In: ECS Transactions, Electrochemical Society, 2016, no 8, p. 615-621Conference paper (Refereed)
    Abstract [en]

    Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 4.
    Garidis, Konstantinos
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration2015In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 165-168Conference paper (Refereed)
    Abstract [en]

    We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

  • 5.
    Garidis, Konstantinos
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Pret, A. V.
    Gronheid, R.
    Mask roughness impact on extreme UV and 193 nm immersion lithography2012In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 98, p. 138-141Article in journal (Refereed)
    Abstract [en]

    The contribution of mask absorber line edge roughness on printed resist lines is studied for extreme UV and 193 nm immersion lithography. Programmed roughness modules were designed for roughness transfer function evaluation on 88 nm pitch line space patterns. The tested modules were designed applying variations of roughness amplitude and spatial frequency. Power spectral density analysis was performed on top-down SEM images. The effect of frequency roughness filtering by the lithographic optical system was studied with different illumination settings. It was found that, except for the degradation of the aerial image due to the filtering effect, less performing illuminations show an increased deterioration of the aerial image quality and thus contribute further to line edge roughness. A comparison with previous work was completed on different mask architectures and photoresist platforms. Resist performance can attenuate the roughness transfer from mask but at the cost of worse chemical gradient at the edges of the exposed regions.

  • 6.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon Nanowires Integrated in a Fully Depleted CMOS Process for Charge Based Biosensing2013In: ULIS 2013: The 14th International Conference on Ultimate Integration on Silicon, Incorporating the 'Technology Briefing Day', IEEE , 2013, p. 81-84Conference paper (Refereed)
    Abstract [en]

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of 32 by 32 pixel matrix (1024 pixels or test sites) and 8 input-output (I/O) pins. In each pixel single crystalline SiNW with 60 by 20 nm cross-section area is defined using sidewall transfer lithography (STL) in the SOI layer. The key advantage of the design is that 1024 individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  • 7.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Silicon nanowires integrated with CMOS circuits for biosensing application2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 26-31Article in journal (Refereed)
    Abstract [en]

    We describe a silicon nanowire (SiNW) biosensor fabricated in a fully depleted SOI CMOS process. The sensor array consists of N by N pixel matrix (N-2 pixels or test sites) and 8 input-output (I/O) pins. In each pixel a single crystalline SiNW with 75 by 20 nm cross-section area is defined using sidewall transfer lithography in the SOI layer. The key advantage of the design is that each individual SiNWs can be read-out sequentially and used for real-time charge based detection of molecules in liquids or gases.

  • 8.
    Jayakumar, Ganesh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellstrom, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication and characterization of silicon nanowires using STL for biosensing applications2014In: INT CONF ULTI INTEGR, ISSN 2330-5738, p. 109-112Article in journal (Refereed)
    Abstract [en]

    We present a sidewall transfer lithography (STL) process to fabricate silicon nanowires using the CMOS compatible materials SiO2, SiN and alpha-Si. The STL process is implemented using a single cluster tool for reactive ion etching (RIE) and plasma enhanced chemical vapor deposition (PECVD) with a maximum process temperature of 400 degrees C. Using three lithography masks, single and multiple silicon nanowires connected to contact areas can be defined. By optimizing layer thicknesses, RIE and deposition conformity we demonstrate wafer scale definition of 60 nm wide silicon nanowires using I-line stepper lithography. The silicon nanowires exhibit excellent characteristics for biosensing applications with subthreshold slopes of 75 mV/dec and a high on/off current ratio of more than 10(5).

  • 9. Pret, Alessandro Vaglio
    et al.
    Gronheid, Roel
    Engelen, Jan
    Yan, Pei-Yang
    Leeson, Michael J.
    Younkin, Todd R.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Biafore, John
    Mask Effects on Resist Variability in Extreme Ultraviolet Lithography2013In: Japanese Journal of Applied Physics, ISSN 0021-4922, E-ISSN 1347-4065, Vol. 52, no 6, p. UNSP 06GC02-Article in journal (Refereed)
    Abstract [en]

    Resist variability is one of the challenges that must to be solved in extreme UV lithography. One of the root causes of the resist roughness are the mask contributions. Three different effects may plays a non-negligible role: mask pattern roughness transfer-or mask line edge roughness, speckle effects caused by mask surface roughness, and mask layout which causes local flare amplification at wafer level. In this paper, mask contributions to the pattern variability are individually assessed experimentally and via stochastic simulations for both lines/spaces and contact holes. It was found that the predominant effect is the mask layout, while the speckle contribution is barely detectable.

1 - 9 of 9
CiteExportLink to result list
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Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
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  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
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Output format
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  • text
  • asciidoc
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