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  • 1.
    Castañeda Lozano, Roberto
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS (Swedish Institute of Computer Science).
    Carlsson, Mats
    SICS (Swedish Institute of Computer Science).
    Hjort Blindell, Gabriel
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Register allocation and instruction scheduling in Unison2016In: Proceedings of CC 2016: The 25th International Conference on Compiler Construction, Association for Computing Machinery (ACM), 2016, p. 263-264Conference paper (Refereed)
    Abstract [en]

    This paper describes Unison, a simple, flexible, and potentially optimal software tool that performs register allocation and instruction scheduling in integration using combinatorial optimization. The tool can be used as an alternative or as a complement to traditional approaches, which are fast but complex and suboptimal. Unison is most suitable whenever high-quality code is required and longer compilation times can be tolerated (such as in embedded systems or library releases), or the targeted processors are so irregular that traditional compilers fail to generate satisfactory code.

  • 2.
    Castañeda Lozano, Roberto
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS (Swedish Institute of Computer Science) and KTH (Royal Institute of Technology).
    Hjort Blindell, Gabriel
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Carlsson, Mats
    SICS (Swedish Institute of Computer Science).
    Drejhammar, Frej
    SICS (Swedish Institute of Computer Science).
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Constraint-based Code Generation2013In: Proceedings of the 16th International Workshop on Software and Compilers for Embedded Systems, M-SCOPES 2013, Association for Computing Machinery (ACM), 2013, p. 93-95Conference paper (Refereed)
    Abstract [en]

    Compiler back-ends generate assembly code by solving three main tasks: instruction selection, register allocation and instruction scheduling. We introduce constraint models and solving techniques for these code generation tasks and describe how the models can be composed to generate code in unison. The use of constraint programming, a technique to model and solve combinatorial problems, makes code generation simple, flexible, robust and potentially optimal.

  • 3.
    Hjort Blindell, Gabriel
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. Swedish Institute of Computer Science.
    Instruction Selection: Principles, Methods, & Applications2016Book (Refereed)
    Abstract [en]

    This book presents a comprehensive, structured, up-to-date survey on instruction selection. The survey is structured according to two dimensions: approaches to instruction selection from the past 45 years are organized and discussed according to their fundamental principles and according to the characteristics of the supported machines instructions. The fundamental principles are macro expansion, tree covering, DAG covering, and graph covering. The machine instruction characteristics introduced are single-output, multi-output, disjoint-output, inter-block, and interdependent machine instructions. The survey also examines problems that have yet to be addressed by existing approaches.

    The book is suitable for advanced undergraduate students in computer science, graduate students, practitioners, and researchers.

  • 4.
    Hjort Blindell, Gabriel
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Survey on Instruction Selection: An Extensive and Modern Literature Review2013Report (Other academic)
    Abstract [en]

    Instruction selection is one of three optimization problems – the other two areinstruction scheduling and register allocation – involved in codegeneration. The task of the instruction selector is to transform an inputprogram from its target-independent representation into a target-specific formby making best use of the available machine instructions. Hence instructionselection is a crucial component of generating code that is both correct andruns efficiently on a specific target machine.

    Despite on-going research since the late 1960s, the last comprehensive survey onthis field was written more than 30 years ago. As many new approaches andtechniques have appeared since its publication, there is a need for anup-to-date review of the current body of literature; this report addresses thatneed by presenting an extensive survey and categorization of both dated methodand the state-of-the-art of instruction selection. The report thereby supersedesand extends the previous surveys, and attempts to identify where future researchcould be directed.

  • 5.
    Hjort Blindell, Gabriel
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. KTH, School of Electrical Engineering and Computer Science (EECS). RISE SICS.
    Universal Instruction Selection2018Doctoral thesis, monograph (Other academic)
    Abstract [en]

    In code generation, instruction selection chooses instructions to implement a given program under compilation, global code motion moves computations from one part of the program to another, and block ordering places program blocks in a consecutive sequence. Local instruction selection chooses instructions one program block at a time while global instruction selection does so for the entire function. This dissertation introduces a new approach called universal instruction selection that integrates global instruction selection with global code motion and block ordering. By doing so, it addresses limitations of existing instruction selection techniques that fail to exploit many of the instructions provided by modern processors.

    To handle the combinatorial nature of these problems, the approach is based on constraint programming, a combinatorial optimization method. It relies on a novel model that is simpler and more flexible compared to the techniques used in modern compilers and that captures crucial features ignored by other combinatorial approaches. The dissertation also proposes extensions to the model for integrating instruction scheduling and register allocation, two other important problems of code generation.

    The model is enabled by a novel, graph-based representation that unifies data and control flow for entire functions. The representation is crucial for integrating instruction selection with global code motion and for modeling sophisticated instructions, whose behavior contains both data and control flow, as graphs.

    Through experimental evaluation, universal instruction selection is demonstrated to handle architectures with a rich instruction set and scales up to functions with hundreds of operations. For these functions, it generates code of equal or better quality compared to the state of the art. The dissertation also demonstrates that there is sufficient data parallelism to be exploited through selection of SIMD instructions and that this exploitation benefits from global code motion. With these results, it is argued that constraint programming is a flexible, practical, competitive, and extensible approach for combining global instruction selection, global code motion, and block ordering.

  • 6.
    Hjort Blindell, Gabriel
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. SICS RISE.
    Carlsson, Mats
    RISE SICS.
    Castañeda Lozano, Roberto
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. RISE SICS.
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS. RISE SICS.
    Complete and Practical Universal Instruction Selection2017In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465Article in journal (Refereed)
    Abstract [en]

    In code generation, instruction selection chooses processor instructions to implement a program under compilation where code quality crucially depends on the choice of instructions. Using methods from combinatorial optimization, this paper proposes an expressive model that integrates global instruction selection with global code motion.The model introduces (1) handling of memory computations and function calls, (2) a method for inserting additional jump instructions where necessary, (3) a dependency-based technique to ensure correct combinations of instructions, (4) value reuse to improve code quality, and (5) an objective function that reduces compilation time and increases scalability by exploiting bounding techniques. The approach is demonstrated to be complete and practical, competitive with LLVM, and potentially optimal (w.r.t. the model) for medium-sized functions. The results show that combinatorial optimization for instruction selection is well-suited to exploit the potential of modern processors in embedded systems.

  • 7.
    Hjort Blindell, Gabriel
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Castañeda Lozano, Roberto
    Swedish Institute of Computer Science.
    Carlsson, Mats
    Swedish Institute of Computer Science.
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Modeling Universal Instruction Selection2015In: Principles and Practice of Constraint Programming: 21st International Conference, CP 2015, Cork, Ireland, August 31 -- September 4, 2015, Proceedings / [ed] Gilles Pesant, Springer, 2015, Vol. 9255, p. 609-626Conference paper (Refereed)
    Abstract [en]

    Instruction selection implements a program under compilation by selecting  processor instructions and has tremendous impact on the performance of the  code generated by a compiler. This paper introduces a graph-based  universal representation that unifies data and control flow for both  programs and processor instructions. The representation is the essential  prerequisite for a constraint model for instruction selection introduced in  this paper. The model is demonstrated to be expressive in that it supports many processor  features that are out of reach of state-of-the-art approaches, such as  advanced branching instructions, multiple register banks, and SIMD  instructions. The resulting model can be solved for small to medium size  input programs and sophisticated processor instructions and is competitive with LLVM in code quality. Model and representation are significant due to their  expressiveness and their potential to be combined with models for other code  generation tasks.

  • 8.
    Hjort Blindell, Gabriel
    et al.
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Menne, Christian
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Synthesizing Code for GPGPUs from abstract formal models2016In: 16th Conference on Languages, Design Methods, and Tools for Electronic System Design, FDL 2014, Springer, 2016, p. 115-134Conference paper (Refereed)
    Abstract [en]

    Today multiple frameworks exist for elevating the task of writing programs for GPGPUs, which are massively data-parallel execution platforms. These are needed as writing correct and high-performing applications for GPGPUs is notoriously difficult due to the intricacies of the underlying architecture. However, the existing frameworks lack a formal foundation that makes them difficult to use together with formal verification, testing, and design space exploration. We present in this chapter a novel software synthesis tool—called f2cc—which is capable of generating efficient GPGPU code from abstract formal models based on the synchronous model of computation. These models can be built using high-level modeling methodologies that hide low-level architecture details from the developer. The correctness of the tool has been experimentally validated on models derived from two applications. The experiments also demonstrate that the synthesized GPGPU code yielded a 28× speedup when executed on a graphics card with 96 cores and compared against a sequential version that uses only the CPU.

  • 9.
    Hjort Blindell, Gabriel
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Menne, Christian
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Synthesizing Code for GPGPUs from Abstract Formal Models2014In: Forum on specification and Design Languages (FDL), Munich, Germany, October 14-16, 2014 / [ed] Dr. Adam Morawiec and Jinnie Hinderscheit, IEEE conference proceedings, 2014Conference paper (Refereed)
    Abstract [en]

    Today multiple frameworks exist for elevating thetask of writing programs for GPGPUs, which are massively data-parallel execution platforms. These are needed as writing correctand high-performing applications for GPGPUs is notoriouslydifficult due to the intricacies of the underlying architecture.However, the existing frameworks lack a formal foundation thatmakes them difficult to use together with formal verification,testing, and design space exploration. We present in this papera novel software synthesis tool – called f2cc – which is capableof generating efficient GPGPU code from abstract formal modelsbased on the synchronous model of computation. These modelscan be built using high-level modeling methodologies that hidelow-level architecture details from the developer. The correctnessof the tool has been experimentally validated on models derivedfrom two applications. The experiments also demonstrate that thesynthesized GPGPU code yielded a 28× speedup when executedon a graphics card with 96 cores and compared against asequential version that uses only the CPU.

  • 10.
    Lozano, Roberto Castaneda
    et al.
    SCALE, Swedish Institute of Computer Science, Sweden .
    Carlsson, Mats
    Hjort Blindell, Gabriel
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Schulte, Christian
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    Combinatorial Spill Code Optimization and Ultimate Coalescing2014In: SIGPLAN notices, ISSN 0362-1340, E-ISSN 1558-1160, Vol. 49, no 5, p. 23-32Article in journal (Refereed)
    Abstract [en]

    This paper presents a novel combinatorial model that integrates global register allocation based on ultimate coalescing, spill code optimization, register packing, and multiple register banks with instruction scheduling (including VLIW). The model exploits alternative temporaries that hold the same value as a new concept for ultimate coalescing and spill code optimization. The paper presents Unison as a code generator based on the model and advanced solving techniques using constraint programming. Thorough experiments using MediaBench and a processor (Hexagon) that are typical for embedded systems demonstrate that Unison: is robust and scalable; generates faster code than LLVM (up to 4 1 % with a mean improvement of 7 %); possibly generates optimal code (for 2 9 % of the experiments); effortlessly supports different optimization criteria (code size on par with LLVM). Unison is significant as it addresses the same aspects as traditional code generation algorithms, yet is based on a simple integrated model and robustly can generate optimal code.

1 - 10 of 10
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  • ieee
  • modern-language-association-8th-edition
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  • en-GB
  • en-US
  • fi-FI
  • nn-NO
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  • Other locale
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