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  • 1. Gorgen, Ralph
    et al.
    Gruttner, Kim
    Herrera, Fernando
    Panil, Pablo
    Medina, Julio
    Villar, Eugenio
    Palermo, Gianluca
    Fornaciari, William
    Brandolese, Carlo
    Gadioli, Davide
    Bocchio, Sara
    Ceva, Luca
    Azzoni, Paolo
    Poncino, Massimo
    Vinco, Sara
    Macii, Enrico
    Cusenza, Salvatore
    Favaro, John
    Valencia, Raul
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Rosvall, Kathrin
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Quaglia, Davide
    CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties2016In: 19TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD 2016), IEEE, 2016, p. 286-293Conference paper (Refereed)
    Abstract [en]

    The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels.

  • 2. Grüttner, K.
    et al.
    Görgen, R.
    Schreiner, S.
    Herrera, F.
    Peñil, P.
    Medina, J.
    Villar, E.
    Palermo, G.
    Fornaciari, W.
    Brandolese, C.
    Gadioli, D.
    Vitali, E.
    Zoni, D.
    Bocchio, S.
    Ceva, L.
    Azzoni, P.
    Poncino, M.
    Vinco, S.
    Macii, E.
    Cusenza, S.
    Favaro, J.
    Valencia, R.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rosvall, Kathrin
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Moghaddami Khalilzad, Nima
    KTH, School of Information and Communication Technology (ICT).
    Quaglia, D.
    CONTREX: Design of embedded mixed-criticality CONTRol systems under consideration of EXtra-functional properties2017In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 51, p. 39-55Article in journal (Refereed)
    Abstract [en]

    The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels. This article presents an overview of the CONTREX European project, its main innovative technology (extension of a model based design approach, functional and extra-functional analysis with executable models and run-time management) and the final results of three industrial use-cases from different domain (avionics, automotive and telecommunication).

  • 3. Herrera, F.
    et al.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Rosvall, Katrin
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Paone, E.
    Palermo, G.
    An efficient joint analytical and simulation-based design space exploration flow for predictable multi-core systems2015In: ACM International Conference Proceeding Series, ACM Digital Library, 2015Conference paper (Refereed)
    Abstract [en]

    Recent work has proposed two-phase joint analytical and simulation-based design space exploration (JAS-DSE) approaches. In such approaches, a first analytical phase relies on static performance estimation and either on exhaustive or heuristic search, to perform a very fast filtering of the design space. Then, a second phase obtains the Pareto solutions after an exhaustive simulation of the solutions found as compliant by the analytical phase. However, the capability of such approaches to find solutions close to the actual Pareto set at a reasonable time cost is compromised by current system complexities. This limitation is due to the fact that such approaches do not support an heuristic exploration on the simulation-based phase. It is not straightforward because in the second phase the heuristic is constrained to consider only the custom set of solutions found in the first phase. This set is in general unconnected and irregularly distributed, which prevents the application of existing heuristics. This paper provides as a solution a novel search heuristic called ARS (Adaptive Random Sampling). The ARS strategy enables the application of heuristic search in the two phases of the JAS-DSE flow, by enabling the application of heuristic in the second phase, regardless the type of performance estimation done at each phase. Moreover, it enables the definition of N-phase DSE flows. The paper shows on an experiment focused on predictable multi-core systems how this enhanced JAS-DSE is capable to find more efficient solutions and to tune the trade-off between exploration time and accuracy in finding actual Pareto solutions.

  • 4.
    Khalilzad, Nima
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rosvall, Kathrin
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics.
    A modular design space exploration framework for multiprocessor real-time systems2017In: Forum on Specification and Design Languages, IEEE, 2017, article id 7880377Conference paper (Refereed)
    Abstract [en]

    Embedded system designers often face a large number of design alternatives when designing complex systems. A designer must select an alternative which satisfies application constraints (e.g. timing requirements) while optimizing system level objectives such as overall energy consumption. The size of design space is often very large giving rise to the need for systematic Design Space Exploration (DSE) methods. In this paper we address the DSE problem for real-time applications that belong to two different domains: (i) streaming applications modeled using the synchronous dataflow graphs; (ii) feedback control tasks modeled using the periodic task model. We consider a heterogeneous multiprocessor platform in which processors communicate through a predictable bus architecture. We present our DSE tool in which the DSE problem is modeled as a constraint satisfaction problem, and it is solved using a constraint programming solver. This approach provides a modular framework in which different constraints such as deadline, throughput and energy consumption can easily be plugged depending on the system being designed.

  • 5.
    Li, Shuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Farahini, Nasim
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Rosvall, Kathrin
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    System level synthesis of hardware for DSP applications using pre-characterized function implementations2013In: 2013 International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), IEEE , 2013Conference paper (Refereed)
    Abstract [en]

    SYLVA is a system level synthesis framework that transforms DSP sub-systems modeled as synchronous data flow into hardware implementations in ASIC, FPGAs or CGRAs. SYLVA synthesizes in terms of pre-characterized function implementations (FTMPs). It explores the design space in three dimensions, number of FTMPs, type of FTMPs and pipeline parallelism between the producing and consuming FTMPs. We introduce timing and interface model of FTMPs to enable reuse and automatic generation of Global Interconnect and Control (GLIC) to glue the FTMPs together into a working system. SYLVA has been evaluated by applying it to five realistic DSP applications and results analyzed for design space exploration, efficacy in generating GLIC by comparing to manually generated GLIC and accuracy of design space exploration by comparing the area and energy costs considered during the design space exploration based on pre-characterized FIMPs and the final results.

  • 6.
    Rosvall, Kathrin
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Mohammadat, Tage
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Ungureanu, George
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Öberg, Johnny
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Sander, Ingo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors2018Conference paper (Refereed)
    Abstract [en]

    System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.

  • 7.
    Rosvall, Kathrin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A constraint-based design space exploration framework for real-time applications on MPSoCs2014In: Proceedings -Design, Automation and Test in Europe, DATE 2014, IEEE Computer Society, 2014, p. 1-6Conference paper (Refereed)
    Abstract [en]

    Design space exploration (DSE) is a critical step in the design process of real-time multiprocessor systems. Combining a formal base in form of SDF graphs with predictable platforms providing guaranteed QoS, the paper proposes a flexible and extendable DSE framework that can provide performance guarantees for multiple applications implemented on a shared platform. The DSE framework is formulated in a declarative style as interprocess communication-aware constraint programming (CP) model. Apart from mapping and scheduling of application graphs, the model supports design constraints on several cost and performance metrics, as e.g. memory consumption and achievable throughput. Using constraints with different compliance level, the framework introduces support for mixed criticality in the CP model. The potential of the approach is demonstrated by means of experiments using a Sobel filter, a SUSAN filter, a RASTA-PLP application and a JPEG encoder.

  • 8.
    Rosvall, Kathrin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Flexible and Tradeoff-Aware Constraint-Based Design Space Exploration for Streaming Applications on Heterogeneous Platforms2018In: ACM Transactions on Design Automation of Electronic Systems, ISSN 1084-4309, E-ISSN 1557-7309, Vol. 23, no 2, article id 21Article in journal (Refereed)
    Abstract [en]

    Due to its complexity, the problem of mapping and scheduling streaming applications on heterogeneous MPSoCs under real-time and performance constraints has traditionally been tackled by incomplete heuristic algorithms. In recent years, approaches based on Constraint Programming (CP) have shown promising results as complete methods for finding optimal mappings, in particular concerning throughput. However, so far none of the available CP approaches consider the tradeoff between throughput and buffer requirements or throughput and power consumption. This article integrates tradeoff awareness into the CP model and introduces a two-step solving approach that utilizes the advantages of heuristics, while still keeping the completeness property of CP. With a number of experiments considering several streaming applications and different platform models, the article illustrates not only the efficiency of the presented model but also its suitability for solving different problems with various combinations of performance constraints.

1 - 8 of 8
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  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
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  • en-US
  • fi-FI
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  • nn-NB
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  • Other locale
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  • text
  • asciidoc
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