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  • 1.
    Alizadeh, Razieh
    et al.
    ShahidBahonar Univ Kerman, Dept Elect Engn, Kerman, Iran..
    Saneei, Mohsen
    ShahidBahonar Univ Kerman, Dept Elect Engn, Kerman, Iran..
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering (EES).
    Fault-Tolerant Circular Routing Algorithm for 3D-NoC2014In: 2014 INTERNATIONAL CONGRESS ON TECHNOLOGY, COMMUNICATION AND KNOWLEDGE (ICTCK), IEEE , 2014Conference paper (Refereed)
    Abstract [en]

    ExpandingNetworks-on-Chip (NoCs) to the third dimension (3D-NoC) has been known as a promising solution for the latency challenges of future many-core Systems-on-Chip. 3D-NoC may take advantages of TSVsfor vertical links which are shorter and faster than horizontal ones. Faults may occur in TSVs as well as the horizontal links though faults inTSVs are more costly. In this paper, we present a fault-tolerant routing algorithm targeting faults in both TSVs and horizontal links. The proposed routing algorithm is based on defining some circular routing paths which offers a deadlock-free routing for packets in mesh-based topologies. In addition to tolerating faults, these circular pathshelp in reducing congestion in the centralpart of the network at high injection rates. The proposed circular routing algorithm is able to tolerate all one-faulty links. In addition, it is shown that its performance is better than those of traditional methods.

  • 2. Charif, Amir
    et al.
    Coelho, Alexandre
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. KTH.
    Bagherzadeh, Nader
    Zergainoh, Nacer-Eddine
    First-Last: A Cost-Effective Adaptive Routing Solution for TSV-Based Three-Dimensional Networks-on-Chip2018In: IEEE transactions on computer, ISSN 0018-9340, Vol. 67, no 10, p. 1430-1444Article in journal (Refereed)
    Abstract [en]

    3D integration opens up new opportunities for future multiprocessor chips by enabling fast and highly scalable 3DNetwork-on-Chip (NoC) topologies. However, in an aim to reduce the cost of Through-silicon via (TSV), partially vertically connectedNoCs, in which only a few vertical TSV links are available, have been gaining relevance. To reliably route packets under suchconditions, we introduce a lightweight, efficient and highly resilient adaptive routing algorithm targeting partially vertically connected3D-NoCs named First-Last. It requires a very low number of virtual channels (VCs) to achieve deadlock-freedom (2 VCs in the Eastand North directions and 1 VC in all other directions), and guarantees packet delivery as long as one healthy TSV connecting all layersis available anywhere in the network. An improved version of our algorithm, named Enhanced-First-Last is also introduced and shownto dramatically improve performance under low TSV availability while still using less virtual channels than state-of-the-art algorithms. Acomprehensive evaluation of the cost and performance of our algorithms is performed to demonstrate their merits with respects toexisting solutions.

  • 3. Chen, Kun-Chih (Jimmy)
    et al.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Wang, Ting-Yi
    Yang, Yuch-Chi
    NoC-based DNN Accelerator: A Future Design Paradigm2019Conference paper (Refereed)
    Abstract [en]

    Deep Neural Networks (DNN) have shown significant advantagesin many domains such as pattern recognition, prediction, and controloptimization. The edge computing demand in the Internet-of-Things era has motivated many kinds of computing platforms toaccelerate the DNN operations. The most common platforms areCPU, GPU, ASIC, and FPGA. However, these platforms suffer fromlow performance (i.e., CPU and GPU), large power consumption(i.e., CPU, GPU, ASIC, and FPGA), or low computational flexibilityat runtime (i.e., FPGA and ASIC). In this paper, we suggest theNoC-based DNN platform as a new accelerator design paradigm.The NoC-based designs can reduce the off-chip memory accessesthrough a flexible interconnect that facilitates data exchange betweenprocessing elements on the chip. We first comprehensivelyinvestigate conventional platforms and methodologies used in DNNcomputing. Then we study and analyze different design parametersto implement the NoC-based DNN accelerator. The presentedaccelerator is based on mesh topology, neuron clustering, randommapping, and XY-routing. The experimental results on LeNet, MobileNet,and VGG-16 models show the benefits of the NoC-basedDNN accelerator in reducing off-chip memory accesses and improvingruntime computational flexibility.

  • 4. Ebrahimi, Masoumeh
    Fully adaptive routing algorithms and region-based approaches for two-dimensional and three-dimensional networks-on-chip2013In: IET Computers & Digital Techniques, ISSN 1751-8601, E-ISSN 1751-861X, ISSN 1751-8601, no 6, p. 264-273Article in journal (Refereed)
    Abstract [en]

    Network congestion has negative impact on the performance of networks-on-chip (NoC). In traditional congestionawaretechniques, congestion is measured at a router level and delivered to other routers, either local or non-local. One of thecontributions of this study is to show that performance can be improved if the congestion level is measured for a group ofrouters, called cluster, and propagated over the network, rather than considering the congestion level of a single router. Thepresented approach is discussed in both two-dimensional (2D) and three-dimensional (3D) mesh networks. To collect andpropagate the congestion information of different clusters, a distributed approach is presented. The gathered information isutilised at routing units to deliver packets through the less congested regions. To distribute packets over the network withoutforming deadlock, routing algorithms should be carefully designed. The authors take advantage of fully adaptive routingalgorithms, providing the maximum degree of adaptiveness for distributing packets. For 2D NoCs, a conventional fullyadaptive routing algorithm, named dynamic XY (DyXY), is utilised. However, for 3D NoCs a fully adaptive routingalgorithm is proposed and this method is called 3D-FAR. On top of each fully adaptive routing algorithm, a region-basedapproach is developed.

  • 5.
    Ebrahimi, Masoumeh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Chang, Xin
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Plosila, Juha
    Univ Turku, Dept Informat Technol, SF-20500 Turku, Finland..
    In-Order Delivery Approach for 3D NoCs2013In: 2013 17TH CSI INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS 2013), IEEE , 2013, p. 87-+Conference paper (Refereed)
    Abstract [en]

    Routing algorithms can be classified into deterministic and adaptive methods. In deterministic methods, a single path is selected for each pair of source and destination nodes, and thus they are unable to distribute the traffic load over the network. Using deterministic routing, packets reach a destination in the same order they are delivered from a source node. Adaptive routing algorithms can greatly improve the performance by distributing packets over different routes. However, it requires a mechanism to reorder packets at destinations. Thereby, a large reordering buffer and a complex control mechanism are required at each node. This motivated us to propose a method guaranteeing in-order delivery while sending packets through alternative paths. The proposed method combines the advantages of both deterministic and adaptive routing algorithms. We introduce several routing algorithms working together in the network without creating cycles. By using these algorithms, packets of different flows use different routes while packets belonging to the same flow follow a single path. In this way, traffic is distributed over the network while addressing in-order delivery. We employ this approach on three-dimensional Networks-on-Chip.

  • 6.
    Ebrahimi, Masoumeh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Chen, K. -CJ.
    Reshadi, M.
    NoCArc 2018 Message from the Chairs2018In: 11th International Workshop on Network on Chip Architectures, NoCArc 2018, article id 8541230Article in journal (Refereed)
  • 7.
    Ebrahimi, Masoumeh
    et al.
    KTH.
    Daneshtalab, Masoud
    Malardalen Univ, Vasteras, Sweden..
    A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks2018In: IEEE Micro, ISSN 0272-1732, E-ISSN 1937-4143, Vol. 38, no 3, p. 79-85Article in journal (Refereed)
    Abstract [en]

    For the past three decades, the interconnection network has been developed based on two major theories, one by Dally and the other by Duato. In this article, we introduce EbDa with a simplified theoretical basis, which directly allows for designing an acyclic channel dependency graph and verifying algorithms on their freedom from deadlock. EbDa is composed of three theorems that enable extracting all allowable turns without dealing with turn models.

  • 8. Ebrahimi, Masoumeh
    et al.
    Daneshtalab, Masoud
    A Light-weight fault-tolerant routing algorithm tolerating faulty links and routers2013In: Computing, ISSN 0010-485X, E-ISSN 1436-5057, Vol. 97, p. 631-648Article in journal (Refereed)
    Abstract [en]

    Faults at either the link or router level may result in the failure of the system. Fault-tolerant routing algorithms attempt to tolerate faults by rerouting packets around the faulty region. This rerouting would be at the cost of significant performance loss. The proposed algorithm in this paper is able to tolerate both faulty routers and links with negligible impact on the performance. In fact, the proposed algorithm avoids taking unnecessary longer paths and the shortest paths are always taken as long as a path exists. On the other hand, fault-tolerant routing algorithms might be based on deterministic routing in which all packets use a single path between each pair of source and destination routers. Using deterministic routing, packets reach the destination in the same order they have been delivered from the source so that no reordering buffer is needed at the destination. For improving the performance, fault-tolerant algorithms might be based on adaptive routing in which packets are delivered through multiple paths to destinations. In this case, packets should be reordered at the destinations demanding reordering buffers. The proposed algorithm can be configured in both working modes, such that it can be based on deterministic or adaptive routing.

  • 9. Ebrahimi, Masoumeh
    et al.
    Daneshtalab, Masoud
    Liljeberg, Pasi
    Plosila, Juha
    Flich, Jose
    Tenhunen, Hannu
    Path-Based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing2014In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 63, no 3, p. 718-733Article in journal (Refereed)
    Abstract [en]

    Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain in ChipMultiprocessors (CMPs) architectures. As multicast communication is commonly used in cache coherence protocols for CMPs and invarious parallel applications, the performance of these systems can be significantly improved if multicast operations are supported at thehardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs,each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore theefficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose theMinimal and Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show thatan advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the networkuntil all partitions contain a comparable number of switches and thus the multicast traffic is equally distributed among several subsetsand the network latency is considerably decreased. The simulation results reveal that the RP method can achieve performanceimprovement across all workloads while performance can be further improved by utilizing the MAR algorithm. Nineteen percent averageand 42 percent maximum latency reduction are obtained on SPLASH-2 and PARSEC benchmarks running on a 64-core CMP.

  • 10.
    Ebrahimi, Masoumeh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Kelati, Amleset
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Nkonoki, Emma
    Kondoro, Aron
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rwegasira, Diana
    KTH.
    Ben Dhaou, Imed
    Taajamaa, Ville
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Creation of CERID: Challenge, Education, Research, Innovation, and Deployment: in the context of smart MicroGrid2019Conference paper (Refereed)
    Abstract [en]

    The iGrid project deals with the design and implementation of a solar-powered smart microgrid to supply electric power to small rural communities. In this paper, we discuss the roadmap of the iGrid project, which forms by merging the roadmaps of KIC (knowledge and Innovation Community) and CDE (Challenge-Driven Education). We introduce and explain a five-gear chain as Challenge, Education, Research, Innovation, and Deployment, called CERID, to reach the main goals of this project. We investigate the full chain in the iGrid project, which is established between KTH Royal Institute of Technology (Sweden) and University of Dar es Salam (Tanzania). We introduce the key stakeholders and explain how CERID goals can be accomplished in higher educations and through scientific research. Challenges are discussed, some innovative ideas are introduced and deployment solutions are recommended.

  • 11.
    Ebrahimi, Masoumeh
    et al.
    KTH.
    Weldezion, Awet Yemane
    Hangofay AB, Stockholm, Sweden..
    Daneshtalab, Masoud
    Malardalen Univ, Vasteras, Sweden..
    NoD: Network-on-Die as a Standalone NoC for Heterogeneous Many-core Systems in 2.5D ICs2017In: 2017 19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS), IEEE , 2017, p. 28-33Conference paper (Refereed)
    Abstract [en]

    Due to a high cost of 3D IC process technology, the semiconductor industry is targeting 2.5D ICs with interposer as a fast and low-cost alternative to integrate dissimilar technologies. In this paper, we propose an independent network-on-chip die, called Network-on-Die (NoD), for 2.5D ICs that operates as a communication backbone for heterogeneous many-core systems on interposer. NoD is responsible for routing packets from a source router to a destination router, and the connections between routers and cores pass through the interposer. This technique eliminates the complexity of the routing algorithms in heterogeneous systems by turning the irregular form of NoC in 2.5D ICs into a regular/optimized one in NoD. The performance evaluation is verified through RTL simulations for a heterogeneous many-core system of varying die sizes and with asymmetric shapes. We provide the theoretical justification for our simulation results.

  • 12. Farahnakian, Fahimeh
    et al.
    Ebrahimi, Masoumeh
    Daneshtalab, Masoud
    Liljeberg, Pasi
    Plosila, Juha
    Adaptive Load Balancing in Learning-based Approaches for Many-core Embedded Systems2014In: Journal of Supercomputing, ISSN 0920-8542, E-ISSN 1573-0484, ISSN 0920-8542, Vol. 68, no 3, p. 1214-1234Article in journal (Refereed)
    Abstract [en]

    Adaptive routing algorithms improve network performance by distributingtraffic over the whole network. However, they require congestion information to facilitateload balancing. To provide local and global congestion information, we proposea learning method based on dual reinforcement learning approach. This informationcan be dynamically updated according to the changing traffic condition in the networkby propagating data and learning packets. We utilize a congestion detection methodwhich updates the learning rate according to the congestion level. This method calculatesthe average number of free buffer slots in each switch at specific time intervalsand compares it with maximum and minimum values. Based on the comparison result,the learning rate sets to a value between 0 and 1. If a switch gets congested, the learningrate is set to a high value, meaning that the global information is more important thanlocal. In contrast, local is more emphasized than global information in non-congestedswitches. Results show that the proposed approach achieves a significant performanceimprovement over the traditional Q-routing, DRQ-routing, DBAR and Dynamic XYalgorithms.

  • 13. Farahnakian, Fahimeh
    et al.
    Ebrahimi, Masoumeh
    Daneshtalab, Masoud
    Liljeberg, Pasi
    Plosila, Juha
    Bi-LCQ: A Low-weight Clustering-based Q-learning Approach for NoCs2014In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, ISSN 0141-9331, Vol. 38, no 1, p. 64-75Article in journal (Refereed)
    Abstract [en]

    Network congestion has a negative impact on the performance of on-chip networks due to the increasedpacket latency. Many congestion-aware routing algorithms have been developed to alleviate trafficcongestion over the network. In this paper, we propose a congestion-aware routing algorithm basedon the Q-learning approach for avoiding congested areas in the network. By using the learning method,local and global congestion information of the network is provided for each switch. This information canbe dynamically updated, when a switch receives a packet. However, Q-learning approach suffers fromhigh area overhead in NoCs due to the need for a large routing table in each switch. In order to reducethe area overhead, we also present a clustering approach that decreases the number of routing tablesby the factor of 4. Results show that the proposed approach achieves a significant performance improvementover the traditional Q-learning, C-routing, DBAR and Dynamic XY algorithms.

  • 14. Huang, L.
    et al.
    Zhang, X.
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
    Li, G.
    Tolerating transient illegal turn faults in NoCs2016In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 43, no SI, p. 104-115Article in journal (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is becoming a competitive solution to connect hundreds of processing elements in modern computing platforms. Under the trend of shrinking feature sizes, circuits are likely to suffer from faults which lead to degraded performance and erroneous behaviour. Compared to permanent faults, transient faults happen even more frequently and seriously while they are hidden within complex on chip behaviours. One of the serious consequences caused by transient faults is taking illegal turns by the packets after the damage of control logic in on-chip routers which may lead to a deadlock situation and eventually crashing the entire system. To avoid this situation, in this paper, we propose a comprehensive scheme called ODT including an improved router architecture, an illegal-turn-resilient routing algorithm, online fault-detect units and a fault classification method. By applying ODT, more turns are supported on routing level and the deadlock situations can be significantly reduced. Experimental results indicate up to 22% increase of the survived packets in the network when 4% of routing computation units in failure. The extra area overhead and power consumption of ODT method is around 9.22% and 9.63%.

  • 15. Huang, Letian
    et al.
    Chen, Shuyu
    Wu, Qiong
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Wang, Junshi
    Jiang, Shuyan
    Li, Qiang
    A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip2018In: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 147-152Conference paper (Refereed)
    Abstract [en]

    Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.

  • 16. Jiang, Shuyan
    et al.
    Wu, Qiong
    Chen, Shuyu
    Wang, Junshi
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Huang, Letian
    Li, Qiang
    Optimizing Dynamic Mapping Techniques for On-Line NoC Test2018In: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), IEEE , 2018, p. 227-232Conference paper (Refereed)
    Abstract [en]

    With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the main goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring about the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle links are identified and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from when the application leaves the platform and a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping. This leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF, NN, CoNA, and WeNA.

  • 17.
    Jiang, Shuyan
    et al.
    University of Electronic Science and Technology of China, Chengdu, China.
    Wu, Qiong
    University of Electronic Science and Technology of China, Chengdu, China.
    Chen, Shuyu
    University of Electronic Science and Technology of China, Chengdu, China.
    Zhan, Junkai
    University of Electronic Science and Technology of China, Chengdu, China.
    Wang, Junshi
    University of Electronic Science and Technology of China, Chengdu, China.
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Huang, Letian
    University of Electronic Science and Technology of China, Chengdu, China.
    Testing aware dynamic mapping for path-centric network-on-chip test2019In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 67, p. 134-143Article in journal (Refereed)
    Abstract [en]

    With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the primary goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle paths are identified, and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from the time when the application leaves the platform to the time when a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping, which leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF(Fiexitrst Free), NN(Nearest Neighbor), CoNA(Contiguous Neighborhood Allocation), and WeNA(Weighted-based Neighborhood Allocation).

  • 18. Patti, D.
    et al.
    Ebrahimi, Masoumeh
    KTH.
    Hollstein, T.
    Daneshtalab, M.
    Palesi, M.
    Wang, X.
    Message from the Chairs2017In: 10th International Workshop on Network on Chip Architectures, NoCArc 2017, article id a10Article in journal (Refereed)
  • 19. Sahebi, G.
    et al.
    Majd, A.
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Plosila, J.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    A reliable weighted feature selection for auto medical diagnosis2017In: Proceedings - 2017 IEEE 15th International Conference on Industrial Informatics, INDIN 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 985-991, article id 8104907Conference paper (Refereed)
    Abstract [en]

    Feature selection is a key step in data analysis. However, most of the existing feature selection techniques are serial and inefficient to be applied to massive data sets. We propose a feature selection method based on a multi-population weighted intelligent genetic algorithm to enhance the reliability of diagnoses in e-Health applications. The proposed approach, called PIGAS, utilizes a weighted intelligent genetic algorithm to select a proper subset of features that leads to a high classification accuracy. In addition, PIGAS takes advantage of multi-population implementation to further enhance accuracy. To evaluate the subsets of the selected features, the KNN classifier is utilized and assessed on UCI Arrhythmia dataset. To guarantee valid results, leave-one-out validation technique is employed. The experimental results show that the proposed approach outperforms other methods in terms of accuracy and efficiency. The results of the 16-class classification problem indicate an increase in the overall accuracy when using the optimal feature subset. Accuracy achieved being 99.70% indicating the potential of the algorithm to be utilized in a practical auto-diagnosis system. This accuracy was obtained using only half of features, as against an accuracy of66.76% using all the features.

  • 20. Sahebi, Golnaz
    et al.
    Majd, Amin
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits. Univ Turku, Finland.
    Plosila, Juha
    Karimpour, Japer
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits. Univ Turku, Finland.
    SEECC: A Secure and Efficient Elliptic Curve Cryptosystem for E-health Applications2016In: 2016 INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING & SIMULATION (HPCS 2016), IEEE, 2016, p. 492-500Conference paper (Refereed)
    Abstract [en]

    Security is an essential factor in wireless sensor networks especially for E-health applications. One of the common mechanisms to satisfy the security requirements is cryptography. Among the cryptographic methods, elliptic curve cryptography is well-known, as by having a small key length it provides the same security level in comparison with the other public key cryptosystems. The small key sizes make ECC very interesting for devices with limited processing power or memory such as wearable devices for E-health applications. It is vitally important that elliptic curves are protected against all kinds of attacks concerning the security of elliptic curve cryptography. Selection of a secure elliptic curve is a mathematically difficult problem. In this paper, an efficient elliptic curve selection framework, called SEECC, is proposed to select a secure and efficient curve front all the available elliptic curves. This method enhances the security and efficiency of elliptic curve cryptosystems by using a parallel genetic algorithm.

  • 21. Salamat, Ronak
    et al.
    Khayambashi, Misagh
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
    Bagherzadeh, Nader
    A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs2016In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 11, p. 3265-3279Article in journal (Refereed)
    Abstract [en]

    3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a 40 - 50% improvement in the fraction of intact inter-level communications when the fault tolerant algorithm is used. This routing algorithm is lightweight and has only one virtual channel along the Y dimension.

  • 22.
    Salamat, Ronak
    et al.
    Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA..
    Khayambashi, Misagh
    Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA..
    Ebrahimi, Masoumeh
    KTH. Univ Turku, SF-20500 Turku, Finland..
    Bagherzadeh, Nader
    Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA..
    LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification2018In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 67, no 8, p. 1153-1166Article in journal (Refereed)
    Abstract [en]

    2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin.

  • 23. Wang, J.
    et al.
    Huang, Y.
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
    Huang, L.
    Li, Q.
    Jantsch, A.
    Li, G.
    VisualNoC: A visualization and evaluation environment for simulation and mapping2016In: ACM International Conference Proceeding Series, Association for Computing Machinery (ACM), 2016, p. 18-25Conference paper (Refereed)
    Abstract [en]

    Simulation is the most common approach to evaluate Network on Chip (NoC) designs and many simulators at different abstraction levels have been developed so far. However, researchers have to spend a considerable amount of time and effort to debug, analyze, and extract meaningful information from the simulator reports. In this work, we propose a full-system visualization framework, called VisualNoC, that support both network simulation and task mapping. VisualNoC operates in a cycle-accurate mode and is based on an event-based trace model which can record the behaviors of routers, processing elements and packets. The visualization interface can provide efficient debugging and analysis platform by representing the simulation process and results in a variety of ways. One of the main features of VisualNoC is providing an intuitive way of analyzing the efficiency of different mapping algorithms that helps in finding bottlenecks and optimizing the design.

  • 24.
    Wang, Junshi
    et al.
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China.;Beijing Zhaoxin Elect Technol Co Ltd, Beijing 100084, Peoples R China..
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Huang, Letian
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
    Xie, Xuan
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
    Li, Qiang
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
    Li, Guangjun
    Univ Elect Sci & Technol China, Chengdu 610054, Sichuan, Peoples R China..
    Jantsch, Axel
    Tech Univ Wien, A-1040 Vienna, Austria..
    Efficient Design-for-Test Approach for Networks-on-Chip2019In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 68, no 2, p. 198-213Article in journal (Refereed)
    Abstract [en]

    To achieve high reliability in on-chip networks, it is necessary to test the network continuously with Built-in Self-Tests (BIST) so that the faults can be detected quickly and the number of affected packets can be minimized. However, BISTcauses significant performance loss due to data dependencies. We propose EsyTest, a comprehensive test strategy with minimized influence on system performance. EsyTest tests the data path and the control path separately. The data path test starts periodically, but the actual test performs in the free time slots to avoid deactivating the router for testing. A reconfigurable router architecture and an adaptive fault-tolerant routing algorithm are proposed to guarantee the access to the processing core when the associated router is under test. During the whole test procedure of the network, all processing cores are accessible, and thus the system performance is maintained during the test. At the same time, EsyTest provides a full test coverage for the NoC and a better hardware compatibility comparing with the existing test strategies. Under the PARSEC benchmark and different test frequencies, the execution time increases less than 5 percent at the cost of 9.9 percent more area and 4.6 percent more power in comparison with the execution where no test procedure is applied.

  • 25.
    Zhan, Junkai
    et al.
    Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Sichuan, Peoples R China..
    Huang, Letian
    Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Sichuan, Peoples R China..
    Wang, Junshi
    Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Sichuan, Peoples R China..
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Li, Qiang
    Univ Elect Sci & Technol China, Inst Integrated Circuits & Syst, Chengdu, Sichuan, Peoples R China..
    Online Path-based Test Method for Network-on-Chip2019In: 2019 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2019Conference paper (Refereed)
    Abstract [en]

    A considerable amount of routers and links remains idle after each mapping application onto the Network-on-Chip based many-core systems. Online path-based test method is a kind of self-test for these idle components. In this paper, a path-based fabric for NoC is firstly proposed. A path serves as the basic component, covering one link and its associated control logic in the routers. One possibility is to apply fault detection on the idle paths, while the other paths continue to operate normally. Moreover, this paper details the hardware implementation, targeting the stuck-at and bridging faults. It suggests a good trade-off between fault coverage, hardware overhead and test time. Experimental results show that the approach achieves 93% of the stuck-at faults in control unit and cover 100% of the stuck-at and bridging faults on the global link within 256 clock cycles.

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