Change search
Refine search result
1 - 11 of 11
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Ebrahimi, Masoumeh
    et al.
    KTH.
    Daneshtalab, Masoud
    Malardalen Univ, Vasteras, Sweden..
    A General Methodology on Designing Acyclic Channel Dependency Graphs in Interconnection Networks2018In: IEEE Micro, ISSN 0272-1732, E-ISSN 1937-4143, Vol. 38, no 3, p. 79-85Article in journal (Refereed)
    Abstract [en]

    For the past three decades, the interconnection network has been developed based on two major theories, one by Dally and the other by Duato. In this article, we introduce EbDa with a simplified theoretical basis, which directly allows for designing an acyclic channel dependency graph and verifying algorithms on their freedom from deadlock. EbDa is composed of three theorems that enable extracting all allowable turns without dealing with turn models.

  • 2.
    Ebrahimi, Masoumeh
    et al.
    KTH.
    Weldezion, Awet Yemane
    Hangofay AB, Stockholm, Sweden..
    Daneshtalab, Masoud
    Malardalen Univ, Vasteras, Sweden..
    NoD: Network-on-Die as a Standalone NoC for Heterogeneous Many-core Systems in 2.5D ICs2017In: 2017 19TH INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE AND DIGITAL SYSTEMS (CADS), IEEE , 2017, p. 28-33Conference paper (Refereed)
    Abstract [en]

    Due to a high cost of 3D IC process technology, the semiconductor industry is targeting 2.5D ICs with interposer as a fast and low-cost alternative to integrate dissimilar technologies. In this paper, we propose an independent network-on-chip die, called Network-on-Die (NoD), for 2.5D ICs that operates as a communication backbone for heterogeneous many-core systems on interposer. NoD is responsible for routing packets from a source router to a destination router, and the connections between routers and cores pass through the interposer. This technique eliminates the complexity of the routing algorithms in heterogeneous systems by turning the irregular form of NoC in 2.5D ICs into a regular/optimized one in NoD. The performance evaluation is verified through RTL simulations for a heterogeneous many-core system of varying die sizes and with asymmetric shapes. We provide the theoretical justification for our simulation results.

  • 3. Huang, Letian
    et al.
    Chen, Shuyu
    Wu, Qiong
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Wang, Junshi
    Jiang, Shuyan
    Li, Qiang
    A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip2018In: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 147-152Conference paper (Refereed)
    Abstract [en]

    Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.

  • 4. Jiang, Shuyan
    et al.
    Wu, Qiong
    Chen, Shuyu
    Wang, Junshi
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Huang, Letian
    Li, Qiang
    Optimizing Dynamic Mapping Techniques for On-Line NoC Test2018In: 2018 23RD ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC), IEEE , 2018, p. 227-232Conference paper (Refereed)
    Abstract [en]

    With the aggressive scaling of submicron technology, intermittent faults are becoming one of the limiting factors in achieving a high reliability in Network-on-Chip (NoC). Increasing test frequency is necessary to detect intermittent faults, which in turn interrupts the execution of applications. On the other hand, the main goal of traditional mapping algorithms is to allocate applications to the NoC platform, ignoring about the test requirement. In this paper, we propose a novel testing-aware mapping algorithm (TAMA) for NoC, targeting intermittent faults on the paths between crossbars. In this approach, the idle links are identified and the components between two crossbars are tested when the application is mapped to the platform. The components can be tested if there is enough time from when the application leaves the platform and a new application enters it. The mapping algorithm is tuned to give a higher priority to the tested paths in the next application mapping. This leaves enough time to test the links and the belonging components that have not been tested in the expected time. Experiment results show that the proposed testing-aware mapping algorithm leads to a significant improvement over FF, NN, CoNA, and WeNA.

  • 5. Patti, D.
    et al.
    Ebrahimi, Masoumeh
    KTH.
    Hollstein, T.
    Daneshtalab, M.
    Palesi, M.
    Wang, X.
    Message from the Chairs2017In: 10th International Workshop on Network on Chip Architectures, NoCArc 2017, article id a10Article in journal (Refereed)
  • 6. Sahebi, G.
    et al.
    Majd, A.
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Plosila, J.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    A reliable weighted feature selection for auto medical diagnosis2017In: Proceedings - 2017 IEEE 15th International Conference on Industrial Informatics, INDIN 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 985-991, article id 8104907Conference paper (Refereed)
    Abstract [en]

    Feature selection is a key step in data analysis. However, most of the existing feature selection techniques are serial and inefficient to be applied to massive data sets. We propose a feature selection method based on a multi-population weighted intelligent genetic algorithm to enhance the reliability of diagnoses in e-Health applications. The proposed approach, called PIGAS, utilizes a weighted intelligent genetic algorithm to select a proper subset of features that leads to a high classification accuracy. In addition, PIGAS takes advantage of multi-population implementation to further enhance accuracy. To evaluate the subsets of the selected features, the KNN classifier is utilized and assessed on UCI Arrhythmia dataset. To guarantee valid results, leave-one-out validation technique is employed. The experimental results show that the proposed approach outperforms other methods in terms of accuracy and efficiency. The results of the 16-class classification problem indicate an increase in the overall accuracy when using the optimal feature subset. Accuracy achieved being 99.70% indicating the potential of the algorithm to be utilized in a practical auto-diagnosis system. This accuracy was obtained using only half of features, as against an accuracy of66.76% using all the features.

  • 7. Sahebi, Golnaz
    et al.
    Majd, Amin
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits. Univ Turku, Finland.
    Plosila, Juha
    Karimpour, Japer
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Elektronics, Integrated devices and circuits. Univ Turku, Finland.
    SEECC: A Secure and Efficient Elliptic Curve Cryptosystem for E-health Applications2016In: 2016 INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING & SIMULATION (HPCS 2016), IEEE, 2016, p. 492-500Conference paper (Refereed)
    Abstract [en]

    Security is an essential factor in wireless sensor networks especially for E-health applications. One of the common mechanisms to satisfy the security requirements is cryptography. Among the cryptographic methods, elliptic curve cryptography is well-known, as by having a small key length it provides the same security level in comparison with the other public key cryptosystems. The small key sizes make ECC very interesting for devices with limited processing power or memory such as wearable devices for E-health applications. It is vitally important that elliptic curves are protected against all kinds of attacks concerning the security of elliptic curve cryptography. Selection of a secure elliptic curve is a mathematically difficult problem. In this paper, an efficient elliptic curve selection framework, called SEECC, is proposed to select a secure and efficient curve front all the available elliptic curves. This method enhances the security and efficiency of elliptic curve cryptosystems by using a parallel genetic algorithm.

  • 8. Salamat, Ronak
    et al.
    Khayambashi, Misagh
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
    Bagherzadeh, Nader
    A Resilient Routing Algorithm with Formal Reliability Analysis for Partially Connected 3D-NoCs2016In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 11, p. 3265-3279Article in journal (Refereed)
    Abstract [en]

    3D ICs can take advantage of a scalable communication platform, commonly referred to as the Networks-on-Chip (NoC). In the basic form of 3D-NoC, all routers are vertically connected. Partially connected 3D-NoC has emerged because of physical limitations of using vertical links. Routing is of great importance in such partially connected architectures. A high-performance, fault-tolerant and adaptive routing strategy with respect to the communication flow among the cores is crucial while freedom from livelock and deadlock has to be guaranteed. In this paper we introduce a new routing algorithm for partially connected 3D-NoCs. The routing algorithm is adaptive and tolerates the faults on vertical links as compared to the predesigned routing algorithms. Our results show a 40 - 50% improvement in the fraction of intact inter-level communications when the fault tolerant algorithm is used. This routing algorithm is lightweight and has only one virtual channel along the Y dimension.

  • 9.
    Salamat, Ronak
    et al.
    Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA..
    Khayambashi, Misagh
    Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA..
    Ebrahimi, Masoumeh
    KTH. Univ Turku, SF-20500 Turku, Finland..
    Bagherzadeh, Nader
    Univ Calif Irvine, Dept Elect Engn & Comp Sci, Irvine, CA 92697 USA..
    LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification2018In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 67, no 8, p. 1153-1166Article in journal (Refereed)
    Abstract [en]

    2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin.

  • 10. Salamat, Ronak
    et al.
    Khayambashi, Misagh
    Ebrahimi, Masoumeh
    KTH.
    Bagherzadeh, Nader
    LEAD: An Adaptive 3D-NoC Routing Algorithm with Queuing-Theory Based Analytical Verification2018In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 67, no 8, p. 1153-1166Article in journal (Refereed)
    Abstract [en]

    2D-NoCs have been the mainstream approach used to interconnect multi-core systems. 3D-NoCs have emerged to compensate for deficiencies of 2D-NoCs such as long latency and power overhead. A low-latency routing algorithm for 3D-NoC is designed to accommodate high-speed communication between cores. Both simulation and analytical models are applied to estimate the communication latency of NoCs. Generally, simulations are time-consuming and slow down the design process. Analytical models provide, within a fraction of the time, nearly accurate results which can be used by simulation to fine-tune the design. In this paper, a high performance and adaptive routing algorithm has been proposed for partially connected 3D-NoCs. Latency of the routing algorithm under different traffic patterns, different number of elevators and different elevator assignment mechanisms are reported. An analytical model, tailored to the adaptivity of the algorithm and under low traffic scenarios, has been developed and the results have been verified by simulation. According to the results, simulation and analytical results are consistent within a 10 percent margin.

  • 11. Wang, J.
    et al.
    Huang, Y.
    Ebrahimi, Masoumeh
    KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
    Huang, L.
    Li, Q.
    Jantsch, A.
    Li, G.
    VisualNoC: A visualization and evaluation environment for simulation and mapping2016In: ACM International Conference Proceeding Series, Association for Computing Machinery (ACM), 2016, p. 18-25Conference paper (Refereed)
    Abstract [en]

    Simulation is the most common approach to evaluate Network on Chip (NoC) designs and many simulators at different abstraction levels have been developed so far. However, researchers have to spend a considerable amount of time and effort to debug, analyze, and extract meaningful information from the simulator reports. In this work, we propose a full-system visualization framework, called VisualNoC, that support both network simulation and task mapping. VisualNoC operates in a cycle-accurate mode and is based on an event-based trace model which can record the behaviors of routers, processing elements and packets. The visualization interface can provide efficient debugging and analysis platform by representing the simulation process and results in a variety of ways. One of the main features of VisualNoC is providing an intuitive way of analyzing the efficiency of different mapping algorithms that helps in finding bottlenecks and optimizing the design.

1 - 11 of 11
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf