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  • 1.
    Albertsson, Dagur Ingi
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Zahedinejad, Mohammad
    Department of Physics, University of Gothenburg.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics. Department of Physics, University of Gothenburg.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Compact Macrospin-Based Model of Three-Terminal Spin-Hall Nano Oscillators2019In: IEEE transactions on magnetics, ISSN 0018-9464, E-ISSN 1941-0069, Vol. 55, no 10, article id 4003808Article in journal (Refereed)
    Abstract [en]

    Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

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  • 2.
    Atallah, Jad. G.
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    A direct conversion WiMAX RF receiver front-end in CMOS technology2007In: ISSCS 2007: International Symposium on Signals, Circuits and Systems, Vols 1 and 2, NEW YORK: IEEE , 2007, p. 37-40Conference paper (Refereed)
    Abstract [en]

    This paper presents a direct conversion RF receiver front-end supporting the WiMAX standard. The front-end is implemented in 0.18um CMOS technology and designed using the ARCHER software. It shows how the design flow can be accelerated starting from the standard specifications and going down to schematics. All this is accompanied by test benches to extract the relevant metrics. This front-end provides a total gain of 31dB, a noise figure of 3.3dB, an IIP2 of 49.5dBm, and an IIP3 of -13.8dBm.

  • 3.
    Chaourani, Panagiotis
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Onet, Raul
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Enabling Area Efficient RF ICs through Monolithic 3D Integration2017In: Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017, Institute of Electrical and Electronics Engineers (IEEE), 2017, p. 610-613, article id 7927059Conference paper (Refereed)
    Abstract [en]

    The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

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  • 4.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines2019In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed)
    Abstract [en]

    Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

  • 5.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Stathis, Dimitrios
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018In: IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S), IEEE conference proceedings, 2018Conference paper (Refereed)
    Abstract [en]

    The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

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  • 6.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dürrenfeld, P.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. University of Gothenburg, Sweden.
    A highly tunable microwave oscillator based on MTJ STO technology2014In: Microwave and optical technology letters (Print), ISSN 0895-2477, E-ISSN 1098-2760, Vol. 56, no 9, p. 2092-2095Article in journal (Refereed)
    Abstract [en]

    This article presents a fully ESD-protected, highly tunable microwave oscillator based on magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology. The oscillator consists of a compact MTJ STO and a 65 nm CMOS wideband amplifier, which amplifies the RF signal of the MTJ STO to a level that can be used to drive a PLL. The (MTJ STO+amplifier IC) pair shows a measured quality factor (Q) of 170 and a wide tunability range from 3 to 7 GHz, which demonstrate its potential to be used as a microwave oscillator in multiband, multistandard radios.

  • 7.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part I: Analytical Model of the MTJ STO2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1037-1044Article in journal (Refereed)
    Abstract [en]

    Magnetic tunnel junction (MTJ) spin torque oscillators (STOs) have shown the potential to be used in a wide range of microwave and sensing applications. To evaluate the potential uses of MTJ STO technology in various applications, an analytical model that can capture MTJ STO's characteristics, while enabling system-and circuit-level designs, is of great importance. An analytical model based on macrospin approximation is necessary for these designs since it allows implementation in hardware description languages. This paper presents a new macrospin-based, comprehensive, and compact MTJ STO model, which can be used for various MTJ STOs to estimate the performance of MTJ STOs together with their application-specific integrated circuits. To adequately present the complete model, this paper is divided into two parts. In Part I, the analytical model is introduced and verified by comparing it against measured data of three different MTJ STOs, varying the angle and magnitude of the magnetic field, as well as the DC biasing current. The proposed analytical model is suitable for being implemented in Verilog-A and used for efficient simulations at device, circuit, and system levels. In Part II, the full Verilog-A implementation of the analytical model with accurate phase noise generation is presented and verified by simulations.

  • 8.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Iacocca, Ezio
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Comprehensive and Macrospin-Based Magnetic Tunnel Junction Spin Torque Oscillator Model-Part II: Verilog-A Model Implementation2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 3, p. 1045-1051Article in journal (Refereed)
    Abstract [en]

    The rapid development of the magnetic tunnel junction (MTJ) spin torque oscillator (STO) technology demands an analytical model to enable building MTJ STO-based circuits and systems so as to evaluate and utilize MTJ STOs in various applications. In Part I of this paper, an analytical model based on the macrospin approximation has been introduced and verified by comparing it with the measurements of three different MTJ STOs. In Part II, the full Verilog-A implementation of the proposed model is presented. To achieve a reliable model, an approach to reproducing the phase noise generated by the MTJ STO has been proposed and successfully employed. The implemented model yields a time domain signal, which retains the characteristics of operating frequency, linewidth, oscillation amplitude, and DC operating point, with respect to the magnetic field and applied DC current. The Verilog-A implementation is verified against the analytical model, providing equivalent device characteristics for the full range of biasing conditions. Furthermore, a system that includes an MTJ STO and CMOS RF circuits is simulated to validate the proposed model for system-and circuit-level designs. The simulation results demonstrate that the proposed model opens the possibility to explore STO technology in a wide range of applications.

  • 9.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Eklund, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Redjai Sani, Sohrab
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF. University of Gothenburg, Sweden.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Integration of GMR-based spin torque oscillators and CMOS circuitry2015In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 111, p. 91-99Article in journal (Refereed)
    Abstract [en]

    This paper demonstrates the integration of giant magnetoresistance (GMR) spin torque oscillators (STO) with dedicated high frequency CMOS circuits. The wire-bonding-based integration approach is employed in this work, since it allows easy implementation, measurement and replacement. A GMR STO is wire-bonded to the dedicated CMOS integrated circuit (IC) mounted on a PCB, forming a (GMR STO + CMOS IC) pair. The GMR STO has a lateral size of 70 nm and more than an octave of tunability in the microwave frequency range. The proposed CMOS IC provides the necessary bias-tee for the GMR STO, as well as electrostatic discharge (ESD) protection and wideband amplification targeting high frequency GMR STO-based applications. It is implemented in a 65 nm CMOS process, offers a measured gain of 12 dB, while consuming only 14.3 mW and taking a total silicon area of 0.329 mm2. The measurement results show that the (GMR STO + CMOS IC) pair has a wide tunability range from 8 GHz to 16.5 GHz and improves the output power of the GMR STO by about 10 dB. This GMR STO-CMOS integration eliminates wave reflections during the signal transmission and therefore exhibits good potential for developing high frequency GMR STO-based applications, which combine the features of CMOS and STO technologies.

  • 10.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Alarcon, Eduard
    UPC Universitat Politecnica de Catalunya Barcelona, Spain.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 2 GHz - 8.7 GHz Wideband Balun-LNA with Noise Cancellation and Gain Boosting2012In: PRIME 2012: Proceedings of the 8th Coference on Ph.D. Research in Microelectronics and Electronics, 2012, IEEE conference proceedings, 2012, p. 59-62Conference paper (Refereed)
    Abstract [en]

    A wideband Balun-LNA covering the operation frequency range of magnetic tunnel junction Spin Torque Oscillator is presented. The LNA is a combination of common-source and cross-coupled common-gate stages, which provides wideband matching and noise cancellation, as well as gain boosting. The internal feedback introduced by the cross-coupling allows an additional degree of freedom to select transistor sizes and bias by decoupling the impedance matching, noise, and gain imbalance trade-offs which are present in similar topologies. Two LNAs using the proposed technique are designed in 65nm CMOS. The LNAs have a simulated bandwidth of  2 GHz - 8.7 GHz, gain of 16 dB, IIP3 of -3.5 dBm,  and NF < 3.8 dB while consuming 3.72 mW from a 1.2 V power supply.

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  • 11.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Wideband Amplifier Design for Magnetic Tunnel JunctionBased Spin Torque Oscillators2012In: Proc. of GigaHertz Symposium 2012, 2012Conference paper (Refereed)
    Abstract [en]

    Spin torque oscillator (STO) is a novel current-control-oscillator (CCO), based on two spintronic effects: spin momentum transfer torque and magneto-resistance (MR). It features large tunability, miniature size, high integration level, high quality factor, high operation frequency, etc., which makes it a promising technology for microwave and radar applications. However, the STO is still an immature technology, which requires intensive research for improving the spectrum purity and the output power performance [1]. This paper proposes a wideband amplifier targeting magnetic tunnel junction (MTJ) type of STO device, which compensates the low output power of the STO.

        The MTJ STO devices can cover a large part of ultra-wideband (UWB) from 3 - 8 GHz and provide an output power from -60 dBm to -40 dBm by tuning the bias DC current and the magnetic field [2][3]. One important and potential application of STO device is a local oscillator (LO) in an RF transceiver. To achieve this task, the amplifier requires a gain of 45 - 65 dB. In addition, the source impedance of different MTJ STO devices varies from a dozen to several hundred Ohms, which makes the amplifier design challenging. An universal amplifier, which fulfills the extracted design requirements, is proposed. It is composed of two types of Balun-LNAs depending on the MR of STO devices as the input stages, a broadband limiting amplifier chain and an output buffer. A combination of a common source (CS) stage and a cross-coupled common gate (CG) stage is employed for the input Balun-LNA in the low impedance case while a cascoded CS stage is used in the high impedance case. The output of both LNAs is connected to a limiting amplifier chain, which provides enough voltage gain. An output buffer is used as the output stage to convert the balanced output to single-ended output and to match the output impedance to 50 Ohms.

        The proposed wideband amplifier for MTJ STO is implemented in a 65nm CMOS process with   1.2 V supply. In the band of interest, it exhibits 55 dB gain with a maximum noise figure (NF) of    4.5 dB in the small MR case, and a 59 dB gain with a maximum NF of 3 dB in the large MR case. Besides the low noise performance and the high gain, the simulation results of the proposed amplifier also show that it has low power consumption and moderate impedance matching in the frequency range of 3 - 8 GHz, which is suitable for MTJ STO applications.

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    Gigahertz2012_tingsu
  • 12.
    Chen, Tingsu
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An Inductorless Wideband Balun-LNA for Spin Torque Oscillator-based Field Sensing2014In: Electronics, Circuits and Systems (ICECS), 2014 21st IEEE International Conference on, IEEE conference proceedings, 2014, p. 36-39Conference paper (Refereed)
    Abstract [en]

    This paper presents a wideband inductorless Balun-LNA targeting spin torque oscillator-based magnetic field sensing applications. The LNA consistsof a CS stage combined with a cross-coupled CG stage, which offers wideband matching, noise/distortion cancellation and gain boosting, simultaneously. The Balun-LNA is implemented in a 65 nm CMOS technology, and it is fully ESD-protected and packaged. Measurement results show a bandwidth of 2 GHz - 7 GHz, a voltage gain of 20 dB, an IIP3 of +2 dBm, and a maximum NF of 5 dB. The LNA consumes 3.84 mW from a 1.2 V power supply and occupies a total silicon area of 0.0044 mm2. The measurement results demonstrate that the proposed Balun-LNA is highly suitable for the STO-based field sensing applications.

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  • 13.
    Dora, Ayadi
    et al.
    University of Sfax, Tunisia .
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Loulou, Mourad
    University of Sfax, Tunisia.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    System level design of radio frequency receiver for IEEE 802.16 standard2008In: 3rd International Design and Test Workshop, 2008, IDT 2008, 2008, p. 82-86Conference paper (Refereed)
    Abstract [en]

    this paper presents a system level design of radio frequency receiver supporting WiMAX mobile standard. Based on direct conversion receiver, the distribution of the total radio system specifications to the individual receiver components is discussed. System level design techniques and theoretical calculation are developed. Simulation results and system simulation level are introduced for noise figure (NF), gain and linearity (third order intercept point, IIP3). Specifications obtained from the received budget can indicate that the noise and the linearity depend on the gain performance of the corresponding circuit blocks. The receiver achieves a total gain of 23dB and an IIP3 of -7.8dBm for low gain mode. It provides up to 68dB gain, 6.5dB noise figure and -16dBm IIP3 for high gain mode.

  • 14.
    Fernández Schrunder, Alejandro
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Huang, Yu-Kai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    A Bioimpedance Spectroscopy Interface for EIM Based on IF-Sampling and Pseudo 2-Path SC Bandpass ΔΣ ADC2024In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, p. 1-13Article in journal (Refereed)
    Abstract [en]

    This paper presents a low-noise bioimpedance (bio-Z) spectroscopy interface for electrical impedance myography (EIM) over the 1 kHz to 2 MHz frequency range. The proposed interface employs a sinusoidal signal generator based on direct-digital-synthesis (DDS) to improve the accuracy of the bio-Z reading, and a quadrature low-intermediate frequency (IF) readout to achieve a good noise-to-power efficiency and the required data throughput to detect muscle contractions. The readout is able to measure baseline and time-varying bio-Z by employing robust and power-efficient low-gain IAs and sixth-order single-bit bandpass (BP) ΔΣ ADCs. The proposed bio-Z spectroscopy interface is implemented in a 180 nm CMOS process, consumes 344.3 - 479.3 μ W, and occupies 5.4 mm 2 area. Measurement results show 0.7 mΩ/√Hz sensitivity at 15.625 kHz, 105.8 dB SNR within 4 Hz bandwidth, and a 146.5 dB figure-of-merit. Additionally, recording of EIM in time and frequency domain during contractions of the bicep brachii muscle demonstrates the potential of the proposed bio-Z interface for wearable EIM systems.

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  • 15.
    Fernández Schrunder, Alejandro
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    A Finite Element Analysis and Circuit Modelling Methodology for Studying Electrical Impedance Myography of Human Limbs2022In: IEEE Transactions on Biomedical Engineering, ISSN 0018-9294, E-ISSN 1558-2531, Vol. 69, no 1, p. 244-255Article in journal (Refereed)
    Abstract [en]

    Objective: Electrical impedance myography (EIM) measures bioimpedance over muscles. This paper proposes a circuit-based modelling methodology originated from finite element analysis (FEA), to emulate tissues and effects from anthropometric variations, and electrode placements, on EIM measurements. The proposed methodology is demonstrated on the upper arms and lower legs. Methods: FEA evaluates impedance spectra (Z-parameters), sensitivity, and volume impedance density for variations of subcutaneous fat thickness (tf), muscle thickness (tm), and inter-electrode distance (IED), on limb models over 1Hz-1MHz frequency range. The limbs models are based on simplified anatomical data and dielectric properties from published sources. Contributions of tissues to the total impedance are computed from impedance sensitivity and density. FEA Z-parameters are imported into a circuit design environment, and used to develop a three Cole dispersion circuit-based model. FEA and circuit model simulation results are compared with measurements on ten human subjects. Results: Muscle contributions are maximized at 31.25kHz and 62.5kHz for the upper arm and lower leg, respectively, at 4cm IED. The circuit model emulates variations in tf and tm, and simulates up to 89 times faster than FEA. The circuit model matches subjects measurements with RMS errors < 36.43 and < 17.28, while FEA does with < 36.59 and < 4.36. Conclusions: We demonstrate that FEA is able to estimate the optimal frequencies and electrode placements, and circuit-based modelling can accurately emulate the limbs bioimpedance. Significance: The proposed methodology facilitates studying the impact of biophysical principles on EIM, enabling the development of future EIM acquisition systems.

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  • 16.
    Garcia, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Low-Power CT Incremental 3rd Order Sigma Delta ADC for Biosensor Applications2013In: IEEE Transactions on Circuits and Systems. Part 1: Regular Papers, ISSN 1549-8328, Vol. 60, no 1, p. 25-36Article in journal (Refereed)
    Abstract [en]

    This paper proposes a 3rd order single-loop continuous-time incremental sigma-delta analogue-to-digital converter (ADC) for time-multiplexed signals. Incremental sigma-delta modulation is used to address medium to high resolution requirements of multi-channel applications, while a 3rd order continuous-time implementation is investigated as an alternative for low-power solutions. A prototype of the proposed modulator, running at 320 kHz, has been fabricated in a 0.15- mCMOStechnology,while the synchronization circuitry to allow incremental operation was built on-board. Measurement results show that the ADC achieves 65.3 dB peak SNR, 64 dB peak SNDR and 68.2 dB dynamic range over a 2 kHz bandwidth. The modulator’s power dissipation is 96 W from a 1.6 V power supply. This translates into the best figure-ofmerit when compared to recently published continuous-time alternatives, while being competitive with respect to state-of-the-art discrete-time counterparts.

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  • 17.
    Garcia, Julian
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    On Continuous-Time Incremental Sigma Delta ADCs With Extended Range2013In: IEEE Transactions on Instrumentation and Measurement, ISSN 0018-9456, E-ISSN 1557-9662, Vol. 62, no 1, p. 60-70Article in journal (Refereed)
    Abstract [en]

    In this paper, the use of continuous-time implementation in extended-range (ER) incremental sigma-delta analog-to-digital converters is analyzed in order to explore a possible solution to low-power multichannel applications. The operation principle, possible loop filter topologies, and critical issues are considered using a general approach. It is demonstrated that, in order to fully benefit from ER, careful attention has to be paid to the analog-digital transfer function mismatches. A third-order single-bit topology validates the theoretical analysis. Its performance is evaluated while the impact of key circuit nonidealities is quantified through behavioral-level simulations. It is shown that, by applying analog-digital mismatch compensation in the digital domain, it is possible to relax the amplifiers' finite gain-bandwidth product and finite dc gain requirements, thus allowing a power-conscious alternative.

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    fulltext
  • 18.
    Grimaldi, Rocco
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A 10-bit 5kHz level-crossing ADC2011In: 2011 20th European Conference on Circuit Theory and Design, ECCTD 2011, 2011, p. 564-567Conference paper (Refereed)
  • 19.
    Hedayati, Raheleh
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lanni, Luigia
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Monolithic, 500 degrees C Operational Amplifier in 4H-SiC Bipolar Technology2014In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 35, no 7, p. 693-695Article in journal (Refereed)
    Abstract [en]

    A monolithic bipolar operational amplifier (opamp) fabricated in 4H-SiC technology is presented. The opamp has been used in an inverting negative feedback amplifier configuration. Wide temperature operation of the amplifier is demonstrated from 25 degrees C to 500 degrees C. The measured closed loop gain is around 40 dB for all temperatures whereas the 3 dB bandwidth increases from 270 kHz at 25 degrees C to 410 kHz at 500 degrees C. The opamp achieves 1.46 V/mu s slew rate and 0.25% total harmonic distortion. This is the first report on high temperature operation of a fully integrated SiC bipolar opamp which demonstrates the feasibility of this technology for high temperature analog integrated circuits.

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    A Monolithic 500C Operational Amplifier in 4H-SiC Bipolar Technology
  • 20.
    Huang, Yu-Kai
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    An Inductorless 40.5V High-Voltage Generator for Integrated Neuromuscular Electrical Stimulators2023In: Proceedings 2023 IEEE Biomedical Circuits and Systems Conference (BioCAS), Institute of Electrical and Electronics Engineers (IEEE) , 2023Conference paper (Refereed)
    Abstract [en]

    Neuromuscular electrical stimulation (NMES) requires voltages exceeding several tens of volts which are typically obtained by using DC-DC boost converters. However, these converters incorporate a large external inductor, which hinders integration and severely restricts the minimum size of the stimulator. This paper presents a charge pump (CP) high-voltage generator particularly designed for NMES applications. The proposed hybrid CP comprises a low-voltage latched CP followed by a high-voltage Dickson CP with boosted pumping clocks. This architecture generates an output voltage of 40.5 V from a 3.3 V supply, enabling the delivery of up to 30 mA stimulation pulses at a maximum frequency of 50 Hz. The circuit is designed in a 180 nm HV CMOS process and occupies a silicon area of 2.7 mm 2 . By eliminating the inductor and requiring only one external storage capacitor, this design has the potential of being used in compact stimulators for wearable medical applications.

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    fulltext
  • 21.
    Huang, Yu-Kai
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Noise Analysis and Design Methodology of Chopper Amplifiers With Analog DC-Servo Loop for Biopotential Acquisition Applications2023In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, p. 1-13Article in journal (Refereed)
    Abstract [en]

    Biopotential acquisition chopper instrumentation amplifiers require a dc-servo loop (DSL) in order to filter electrode dc offsets. However, the noise performance degradation due to the addition of the DSL is often overlooked despite that it can be very detrimental at the frequencies of interest. This article presents an in-depth noise analysis of biopotential acquisition chopper instrumentation amplifiers with analog DSLs. Analytical expressions that predict the noise of different DSL implementations are found and a design flow to minimize their noise contribution is proposed. The design methodology is demonstrated with example circuits targeting biopotential recording systems. These circuits are implemented using a standard 180 nm CMOS technology, and their performance is verified through postlayout simulations. The findings of this work provide a comprehensive understanding of the noise characteristics of a DSL, its impact on noise performance, and design strategies for noise optimization.

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    fulltext
  • 22.
    Huang, Yu-Kai
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Noise Analysis of Current-Feedback DC-Servo Loop in Current-Balancing Chopper Amplifiers2022In: 2022 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS) / [ed] Nurmi, J Wisland, DT Aunet, S Kjelgaard, K, Institute of Electrical and Electronics Engineers (IEEE) , 2022Conference paper (Refereed)
    Abstract [en]

    Chopper amplifiers for biopotential acquisition commonly suppress differential electrode DC offsets by using a DC-servo loop (DSL). However, the noise contribution of the DSL is always neglected in noise analysis. The noise introduced by the DSL, in particular at low frequencies, is of great importance in biosensor applications. This work presents the noise modeling of a current-balancing chopper amplifier with DSL and describes the effect of the DSL on the noise performance. Two different DSL implementations are analyzed. It is found that the exact placement of the chopper in the DSL has a strong impact in the noise performance; therefore, its placement can not be arbitrarily selected. A circuit topology to minimize its noise contribution is then proposed and verified by simulation.

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  • 23.
    Huang, Yu-Kai
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    A 4-Channel NMES IC for Wearable Applications2021In: BioCAS 2021 - IEEE Biomedical Circuits and Systems Conference, Proceedings, Institute of Electrical and Electronics Engineers Inc. , 2021Conference paper (Refereed)
    Abstract [en]

    This paper presents an integrated circuit solution for multi-channel neuromuscular electrical stimulation (NMES). The stimulation waveform is digitally controlled and supports monophasic pulses, and both symmetric and asymmetric biphasic pulses. In addition, the current intensity is programmable, ranging from 0 mA to 31 mA with 5-bit resolution. The integrated circuit occupies an area of 1 mm2and it is designed and simulated in a 180 nm high-voltage CMOS technology. The circuits are powered using standard 1.8 V and 3.3 V power supplies for the digital control and digital-to-analog converter, and a single 40 V power supply for the output drivers. The simulation results show that the design achieves a voltage compliance of up to 35 V, meeting the requirements for NMES applications while offering a very compact and scalable solution.

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    fulltext
  • 24.
    Huang, Yu-Kai
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    A Current Monitoring and Over-Current Detection Circuit for Safe Electrical Stimulation2023In: IEEE Transactions on Circuits and Systems - II - Express Briefs, ISSN 1549-7747, E-ISSN 1558-3791, Vol. 70, no 5, p. 1684-1688Article in journal (Refereed)
    Abstract [en]

    This brief presents an integrated solution to over-current protection in neuromuscular stimulators. The proposed approach provides fast detection of a single-fault condition, i.e., unintentional electrode short circuit or malfunction of the stimulator, thereby preventing prolonged high-intensity currents from flowing into tissues. In addition, a programmable current threshold enables the system to be also used for monitoring the stimulation intensity. The proposed solution was designed in a 180 nm high-voltage CMOS technology, and its functionality was verified by post-layout simulations in which the safety mechanisms were tested under fault conditions. The implementation only occupies an area of 0.286 mm2, making it feasible to be embedded in fully integrated NMES stimulators while providing the required patient safety.

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    fulltext
  • 25.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. Ascatron AB.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Silicon Carbide BJT Oscillator Design Using S-Parameters2018In: European Conference on Silicon Carbide and Related Materials (ECSCRM), Birmingham September 2-6, 2018., 2018Conference paper (Refereed)
    Abstract [en]

    Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation isfurther aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, analternative small-signal, S-parameter based design method can be employed directly without goinginto complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 0C) was accessed by on-wafer probing and connectedby RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

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    fulltext
  • 26.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Silicon carbide BJT oscillator design using S-parameters2019In: Silicon Carbide and Related Materials 2018, Trans Tech Publications Ltd , 2019, p. 674-678Conference paper (Refereed)
    Abstract [en]

    Radio frequency (RF) oscillator design typically requires large-signal, high-frequency simulation models for the transistors. The development of such models is generally difficult and time consuming due to a large number of measurements needed for parameter extraction. The situation is further aggravated as the parameter extraction process has to be repeated at multiple temperature points in order to design a wide-temperature range oscillator. To circumvent this modelling effort, an alternative small-signal, S-parameter based design method can be employed directly without going into complex parameter extraction and model fitting process. This method is demonstrated through design and prototyping a 58 MHz, high-temperature (HT) oscillator, based on an in-house 4H-SiC BJT. The BJT at elevated temperature (up to 300 °C) was accessed by on-wafer probing and connected by RF-cables to the rest of circuit passives, which were kept at room temperature (RT).

  • 27.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH.
    Schröder, Stephan
    KTH.
    Rodriguez, Saul
    KTH.
    Malm, B. Gunnar
    KTH.
    Östling, Mikael
    KTH.
    Rusu, Ana
    KTH.
    An Intermediate Frequency Amplifier for High-Temperature Applications2018In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 65, no 4, p. 1411-1418Article in journal (Refereed)
    Abstract [en]

    This paper presents a two-stage small signal intermediate frequency amplifier for high-temperature communication systems. The proposed amplifier is implemented using in-house silicon carbide bipolar technology. Measurements show that the proposed amplifier can operate from room temperature up to 251 °C. At a center frequency of 54.6 MHz, the amplifier has a gain of 22 dB at room temperature, which decreases gradually to 16 dB at 251 °C. Throughout the measured temperature range, it achieves an input and output return loss of less than-7 and-11 dB, respectively. The amplifier has a 1-dB output compression point of about 1.4 dBm, which remains fairly constant with temperature. Each amplifier stage is biased with a collector current of 10 mA and a base-collector voltage of 3 V. Under the aforementioned biasing, the maximum power dissipation of the amplifier is 221 mW.

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  • 28.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Malm, Bengt Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    An Intermediate Frequency Amplifier for High-Temperature Applications (vol 65, pg 1411, 2018)2019In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, no 8, p. 3694-3694Article in journal (Refereed)
    Abstract [en]

    This correspondence highlights an error in the above-titled paper. The corrected material is presented here.

  • 29.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits. Ascatron AB.
    Zumbro, John E.
    University of Arkansas.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications2019In: IEEE Journal of the Electron Devices Society, E-ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed)
    Abstract [en]

    This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

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  • 30.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Zumbro, John E.
    University of Arkansas.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Intelligent systems, Micro and Nanosystems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)
    Abstract [en]

    This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

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    fulltext
  • 31.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Pandey, Himadri
    University of Siegen.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    University of Siegen.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Optimization of a Compact I–V Model forGraphene FETs: Extending Parameter Scalability for Circuit Design Exploration2015In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 62, no 11, p. 3870-3875Article in journal (Refereed)
    Abstract [en]

    An optimization of the current-to-voltage transfer characteristic of a graphene FET (GFET) compact model, based on drift-diffusion carrier transport, is presented. The improved accuracy at Dirac point extends the model usability for GFETs when scaling parameters, such as voltage supply, gate length, oxide thickness, and mobility, for circuit design exploration. The model's accuracy is demonstrated through fitting to GFETs processed in-house. The model has been written in a standard behavioral language, and extensively run in an analog circuit simulator for designing basic circuits, such as inverters and cascode cells, demonstrating its robustness.

  • 32.
    Iannazzo, Mario
    et al.
    Technical University of Catalonia.
    Lo Muzzo, Valerio
    STMicroelectronics.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. Department of Electrical Engineering and Computer Science Technology, University of Siegen, Siegen, Germany.
    Alarcon, Eduard
    Tech. Univ. of Catalunya.
    Design exploration of graphene-FET based ring-oscillator circuits: A test-bench for large-signal compact models2015In: IEEE International Symposium on Circuits and Systems (ISCAS), IEEE Communications Society, 2015, p. 2716-2719Conference paper (Refereed)
    Abstract [en]

    This paper presents a design-oriented characterization of ring-oscillator (RO) circuits based on complementary-inverters (INVs) implemented with graphene-FET (GFET) devices. A large-signal GFET compact model based on drift-diffusion transport is benchmarked at the circuit level against a second GFET compact model based on virtual source. Transient-based simulations of a 3-cell RO yield performance metrics in terms of operating frequency and voltage dynamic range. Against these metrics, a comprehensive design space exploration covering as input design variables parameters as GFET gate-oxide thickness tOX and channel-length L is presented. Methodologically, the work presents a general-purpose design framework, illustrated for ROs, which establishes a vertical circuit-device co-design environment. Its double-fold outcome is to provide guidelines both to bottom-up dimension and size the circuit, as well as top-down refine GFET device models and in turn GFET technology.

  • 33.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed)
    Abstract [en]

    This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

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  • 34.
    Ivanisevic, Nikola
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    A 96.4 dB High-Pass Delta-Sigma Modulator with Dynamic Biasing and Tree-Structured DEM2016In: 2016 14TH IEEE INTERNATIONAL NEW CIRCUITS AND SYSTEMS CONFERENCE (NEWCAS), Vancouver, Canada: IEEE, 2016, article id 7604762Conference paper (Refereed)
    Abstract [en]

    This paper presents a switched-capacitor high-pass delta-sigma modulator that can directly convert a chopper modulated signal to the digital domain. Low power consumption is achieved by employing inverter-based amplifiers and dynamic biasing in the first amplifier with relaxed slew-rate requirements as a result of the multi-bit quantization. The mismatch errors in the switched-capacitor DAC are first-order noise shaped by a tree-structured dynamic element matching encoder. Schematic level simulations show that the high-pass modulator achieves a peak SNDR of 96.4 dB and a SFDR of 101 dBc over a bandwidth of 300 Hz. The total estimated power consumption of the modulator is 19.56 mu W leading to a figure-of-merit of 0.6 pJ/conv.

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    fulltext
  • 35.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation2018Conference paper (Refereed)
    Abstract [en]

    A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

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  • 36.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Impedance Spectroscopy Based on Linear System Identification2019In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990, Vol. 13, no 2, p. 396-402Article in journal (Refereed)
    Abstract [en]

    Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

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  • 37.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Integrated devices and circuits.
    Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach2017In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper (Refereed)
    Abstract [en]

    Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

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    fulltext
  • 38.
    Juthberg, R.
    et al.
    Department of Molecular Medicine and Surgery, Karolinska Institutet, Stockholm, Sweden.
    Flodin, J.
    Department of Molecular Medicine and Surgery, Karolinska Institutet, Stockholm, Sweden.
    Guo, L.
    Smart Textiles and Polymeric E-textiles, Swedish School of Textiles, University of Borås, Borås, Sweden.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems, Electronic and embedded systems.
    Persson, N. K.
    Smart Textiles and Polymeric E-textiles, Swedish School of Textiles, University of Borås, Borås, Sweden.
    Ackermann, P. W.
    Department of Molecular Medicine and Surgery, Karolinska Institutet, Stockholm, Sweden; Department of Trauma, Acute Surgery and Orthopaedics, Karolinska University Hospital, Stockholm, Sweden.
    Neuromuscular electrical stimulation in garments optimized for compliance2023In: European Journal of Applied Physiology, ISSN 1439-6319, E-ISSN 1439-6327, Vol. 123, no 8, p. 1739-1748Article in journal (Refereed)
    Abstract [en]

    Purpose: Physical inactivity is associated with muscle atrophy and venous thromboembolism, which may be prevented by neuromuscular electrical stimulation (NMES). This study aimed to investigate the effect on discomfort, current amplitude and energy consumption when varying the frequency and phase duration of low-intensity NMES (LI-NMES) via a sock with knitting-integrated transverse textile electrodes (TTE). Methods: On eleven healthy participants (four females), calf-NMES via a TTE sock was applied with increasing intensity (mA) until ankle-plantar flexion at which point outcomes were compared when testing frequencies 1, 3, 10 and 36 Hz and phase durations 75, 150, 200, 300 and 400 µs. Discomfort was assessed with a numerical rating scale (NRS, 0–10) and energy consumption was calculated and expressed in milli-Joule (mJ). Significance set to p ≤ 0.05. Results: 1 Hz yielded a median (inter-quartile range) NRS of 2.4 (1.0–3.4), significantly lower than both 3 Hz with NRS 2.8 (1.8–4.2), and 10 Hz with NRS 3.4 (1.4–5.4) (both p ≤.014). Each increase in tested frequency resulted in significantly higher energy consumption, e.g. 0.6 mJ (0.5–0.8) for 1 Hz vs 14.9 mJ (12.3–21.2) for 36 Hz (p =.003). Longer phase durations had no significant effect on discomfort despite generally requiring significantly lower current amplitudes. Phase durations 150, 200 and 400 µs required significantly lower energy consumption compared to 75 µs (all p ≤.037). Conclusion: LI-NMES applied via a TTE sock produces a relevant plantar flexion of the ankle with the best comfort and lowest energy consumption using 1 Hz and phase durations 150, 200 or 400 µs.

  • 39. Kargarrazi, S.
    et al.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT).
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT).
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT).
    500 °c, High Current Linear Voltage Regulator in 4H-SiC BJT Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 4, p. 548-551Article in journal (Refereed)
    Abstract [en]

    This letter reports on a fully integrated 2-linear voltage regulator operational in a wide temperature range from 25 °C up to 500 °C fabricated in 4H-SiC technology. The circuit provides a stable output voltage with less than 1% variation in the entire temperature range. This letter demonstrates the first power supply solution providing both high-temperature (up to 500 °C) and high-load driving capabilities (up to 2).

  • 40.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Dual-Output Thermoelectric Energy Harvesting Interface with 86.6% Peak Efficiency at 30 μW and Total Control Power of 160 nW2016In: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173XArticle in journal (Refereed)
    Abstract [en]

    A thermoelectric energy harvesting interface based on a single-inductor dual-output (SIDO) boost converter is presented. A system-level design methodology combined with ultra-low power circuit techniques reduce the power consumption and minimize the losses within the converter. Additionally, accurate zero-current switching (ZCS) and zero-voltage switching (ZVS) techniques are employed in the control circuit to ensure high conversion efficiency at μW input power levels. The proposed SIDO boost converter is implemented in a 0.18 μm CMOS process and can operate from input voltages as low as 15 mV. The measurement results show that the converter achieves a peak conversion efficiency of 86.6% at 30 μW input power.

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    EH_Interface
  • 41.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT).
    A High-Efficiency Energy Harvesting Interface for Implanted Biofuel Cell and Thermal Harvesters2017In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 33, no 5, p. 4125-4134, article id 7940053Article in journal (Refereed)
    Abstract [en]

    A dual-source energy harvesting interface that combines energy from implanted glucose biofuel cell and thermoelectric generator is presented. A single-inductor dual-input dual-output boost converter topology is employed to efficiently transfer the extracted power to the output. A dual-input feature enables the simultaneous maximum power extraction from two harvesters, while a dual-output allows a control circuit to perform complex digital functions at nW power levels. The control circuit reconfigures the converter to improve the efficiency and achieve zero-current and zero-voltage switching. The measurement results of the proposed boost converter, implemented in a 0.18 μm CMOS process, show a peak efficiency of 89.5% when both sources provide a combined input power of 66 μW. In the single-source mode, the converter achieves a peak efficiency of 85.2% at 23 μW for the thermoelectric source and 90.4% at 29 μW for the glucose biofuel cell. The converter can operate from minimum input voltages of 10 mV for the thermoelectric source and 30 mV for the glucose biofuel cell. 

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    EH_MS_JK
  • 42.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    An Adaptive FET Sizing Technique for HighEfficiency Thermoelectric Harvesters2016In: 2016 IEEE International Conference on Electronics, Circuits and Systems (ICECS), Monte Carlo: IEEE, 2016, p. 504-507Conference paper (Refereed)
    Abstract [en]

    A theoretical analysis of losses in low power thermoelectric harvester interfaces is used to find expressions for properly sizing the power transistors according to the input voltage level. These expressions are used to propose an adaptive FET sizing technique that tracks the input voltage level and automatically reconfigures the converter in order to improve its conversion efficiency. The performance of a low-power thermoelectric energy harvesting interface with and without the proposed technique is evaluated by circuit simulations under different input voltage/power conditions. The simulation results show that the proposed technique improves the conversion efficiency of the energy harvesting interface up to 12% at the lowest input voltage/power levels.

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    fulltext
  • 43.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    An Efficient Boost Converter Control for Thermoelectric Energy Harvesting2013In: Electronics, Circuits, and Systems (ICECS), 2013 IEEE 20th International Conference on, IEEE conference proceedings, 2013, p. 385-388Conference paper (Refereed)
    Abstract [en]

    This paper presents an ultra-low power controlcircuit for a DC-DC boost converter targeting implantablethermoelectric energy harvesting applications. Efficiency of theinput converter is enhanced by utilizing zero-current switchingtechnique. Adaptive delay between ON states of switches assureszero-voltage switching of synchronous rectifier and reducesswitching losses. The control circuit employing both techniquesconsumes an average power of 620nW. This allows the converterto operate from harvested power below 5μW. For voltageconversion ratios above 20, the proposed circuits and techniquesdemonstrate efficiency improvement compared to the state-of-the-art solutions.

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    fulltext
  • 44.
    Katic, Janko
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Analysis of Dead Time Losses in Energy Harvesting Boost Converters for Implantable Biosensors2014In: NORCHIP, 2014, IEEE conference proceedings, 2014, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Efficiency of an ultra-low power energy harvesting dc-dc converter depends on its losses and the power consumption of the control circuit. Unlike other loss mechanisms, losses related to dead times have not been thoroughly studied. Therefore, in most cases these losses are not adequately suppressed. This paper investigates dead time losses and their impact on the overall system efficiency. Simple expressions for fast estimation of dead time losses are derived. Analysis shows that in many applications where high voltage conversions are required, such as implantable biosensors, the efficiency reduction due to these losses can easily exceed 2%. The analysis is validated using an adaptive dead time circuit which minimizes the associated losses and improves the overall system efficiency according to the calculated values.

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    fulltext
  • 45.
    Lemme, Max C.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Li, Jiantong
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Graphene for More Moore and More Than Moore applications2012In: IEEE Silicon Nanoelectronics Workshop, SNW, IEEE , 2012, p. 6243322-Conference paper (Refereed)
    Abstract [en]

    Graphene has caught the attention of the electronic device community as a potential future option for More Moore and More Than Moore devices and applications. This is owed to its remarkable material properties, which include ballistic conductance over several hundred nanometers or charge carrier mobilities of several 100.000 cm 2/Vs in pristine graphene. Furthermore, standard CMOS technology may be applied to graphene in order to make devices. Integrated graphene devices, however, are performance limited by scattering due to defects in the graphene and its dielectric environment [1, 2] and high contact resistance [3, 4]. In addition, graphene has no energy band gap (Figure 1) and hence graphene MOSFETs (GFETs) cannot be switched off, but instead show ambipolar behaviour [5]. This has steered interest away from logic to analog radio frequency (RF) applications [6, 7]. This talk will systematically compare the expected RF performance of realistic GFETs with current silicon CMOS technology [8]. GFETs slightly lag behind in maximum cut-off frequency F T,max (Figure 2) up to a carrier mobility of 3000 cm 2/Vs, where they can achieve similar RF performance as 65nm silicon FETs. While a strongly nonlinear voltage-dependent gate capacitance inherently limits performance, other parasitics such as contact resistance are expected to be optimized as GFET process technology improves.

  • 46.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Security and Privacy Issues in a GPS-enabled Mobile Application for Smart Traffic2010In: Proceedings of Smart Mobility Conference, 2010, 2010Conference paper (Refereed)
  • 47.
    Manolopoulos, Vasileios
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tao, Sha
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    MobiTraS: a mobile application for a Smart Traffic System2010In: Proceedings of the 8th IEEE International NEWCAS Conference, IEEE , 2010, p. 365-368Conference paper (Refereed)
    Abstract [en]

    Traffic monitoring systems deployed until now, use data collected mainly through fixed sensors. Advances on the modern mobile devices have made possible the development of S mart Traffic Systems, which use the traffic information g athered by the drivers' mobile devices to provide route guidance. Our work is focused on building a Real-Time Traffic Information System based mobile devices, which are used for both acquiring traffic information data and for providing feedback and guidance to drivers. This paper presents an analysis of the system, its security risks and requirements for dynamic route guidance together with possible solutions. A key component of the system is the mobile application that gathers data in an encrypted way and displays information to the users. The developed JavaME mobile application and its security/privacy features are also described.

  • 48.
    Morici, Andrea
    et al.
    Universita Politecnica delle Marche.
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Ismail, Mohammed
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Turchetti, C.
    Universita Politecnica delle Marche.
    A 3.6 mW 90 nm CMOS 2.4 GHz Receiver Front-End Design for IEEE 802.15.4 WSNs2009In: ISSCS 2009: INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS, VOLS 1 AND 2, PROCEEDINGS, New York: IEEE , 2009, p. 77-80Conference paper (Refereed)
    Abstract [en]

    In this paper a low-power design of an integrated RF receiver for Wireless Sensor Networks (WSNs) in 90nm CMOS technology is proposed. The receiver is IEEE 802.15.4 physical specifications compliant. It is designed to operate in ISM band at 2.45 GHz center frequency. Target devices for this kind of transceiver are low-cost battery powered smart embedded devices and sensors. The receiver is designed to reduce the count of external components in the final system, integrating on silicon the balun for single-ended to differential conversion. The receiver is composed of an inductorless Low Noise Amplifier (LNA), a buffer stage, I and Q passive mixers and Variable Gain Amplifiers (VGAs) that also act as second order filters. A novel integration of balun into the LNA is described. The system is designed to have direct conversion from RF to 6 MHz low-IF. Voltage supply is 1.2 V with a current consumption of 3 mA including necessary biasing networks, and the total power consumption is 3.6 mW. The complete voltage gain is more than 41.5 dB with a Noise Figure (NF) of 12.6 dB. The receiver layout exhibits an area of only 0.12 mm(2). Simulations are provided, including mismatch scenarios.

  • 49.
    Ollmar, Stig
    et al.
    Department of Clinical Science, Intervention and Technology, Karolinska Institute, Stockholm, Sweden.
    Fernández Schrunder, Alejandro
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Birgersson, Ulrik
    Department of Clinical Science, Intervention and Technology, Karolinska Institute, Stockholm, Sweden.
    Kristoffersson, Tomas
    Prevas AB, Stockholm, Sweden.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    Thorsson, Elina
    Pathology Unit, Department of Biomedical Science and Veterinary Public Health, Swedish University of Agricultural Sciences, Uppsala, Sweden.
    Hedenqvist, Patricia
    Department of Clinical Sciences, Swedish University of Agricultural Sciences, Uppsala, Sweden.
    Manell, Elin
    Department of Clinical Sciences, Swedish University of Agricultural Sciences, Uppsala, Sweden..
    Rydén, Anneli
    Department of Clinical Sciences, Swedish University of Agricultural Sciences, Uppsala, Sweden..
    Jensen-Waern, Marianne
    Department of Clinical Sciences, Swedish University of Agricultural Sciences, Uppsala, Sweden.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.
    A battery-less implantable glucose sensor based on electrical impedance spectroscopy2023In: Scientific Reports, E-ISSN 2045-2322, Vol. 13, no 1, article id 18122Article in journal (Refereed)
    Abstract [en]

    The ability to perform accurate continuous glucose monitoring without blood sampling has revolutionised the management of diabetes. Newer methods that can allow measurements during longer periods are necessary to substantially improve patients’ quality of life. This paper presents an alternative method for glucose monitoring which is based on electrical impedance spectroscopy. A battery-less implantable bioimpedance spectroscope was designed, built, and used in an in vivo study on pigs. After a recovery period of 14 days post surgery, a total of 236 subcutaneous bioimpedance measurements obtained from intravenous glucose tolerance tests, with glucose concentration ranges between 77.4 and 523.8 mg/dL, were analyzed. The results show that glucose concentrations estimated by subcutaneous bioimpedance measurements correlate very well to the blood glucose reference values. The pigs were clinically healthy throughout the study, and the postmortem examinations revealed no signs of adverse effects related to the sensor. The implantation of the sensor requires minor surgery. The implant, being externally powered, could in principle last indefinitely. These encouraging results demonstrate the potential of the bioimpedance method to be used in future continuous glucose monitoring systems.

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    fulltext
  • 50. Onet, Raul
    et al.
    Neag, Marius
    Kovacs, Istvan
    Topa, Marina Dana
    Rodriguez, Saul
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rusu, Ana
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Compact Variable Gain Amplifier for a Multistandard WLAN/WiMAX/LTE Receiver2014In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 61, no 1, p. 247-257Article in journal (Refereed)
    Abstract [en]

    This paper presents a novel single-stage VGA architecture that employs two Gm cells, a voltage-controlled current attenuator, resistors and capacitors. The gain can be changed in three large steps by using digital controls, and continuously within these steps. The VGA bandwidth and output-related IP3 and 1dBCP are independent of the gain setting; the bandwidth can be programmed through a digitally-controlled capacitor array placed at its output. The proposed architecture was employed to realize the VGA for a WLAN/WiMAX/LTE radio receiver. Die area and power consumption were reduced by implementing the two Gm cells with one instantiation of a high-linearity Gm-core and scaled outputs; also, the current attenuator was implemented with a simple differential current steering circuit; finally, the load resistors were also used to sense the output common-mode level. The VGA was fabricated in 0.15 um standard CMOS process. Measurement results show the gain varying between 5 dB to 30 dB and the max bandwidth surpasses 60 MHz; 11.14 nV/root Hz input referred noise; O1dBCP of 8.6 dBm while taking 4.2 mA from a 1.8 V supply; it settles within 20 ns after a min-max step-change of the gain; it occupies 0.05 mm(2).

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