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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Garidis, Konstantinos
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Epitaxial growth of Ge strain relaxed buffer on Si with low threading dislocation density2016In: ECS Transactions, Electrochemical Society, 2016, no 8, p. 615-621Conference paper (Refereed)
    Abstract [en]

    Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 4.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Ekström, Mattias
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    A wafer-scale Ni-salicide contact technology on n-type 4H-SiC2017In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, E-ISSN 2162-8777, Vol. 6, no 4, p. P197-P200Article in journal (Refereed)
    Abstract [en]

    A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

1 - 4 of 4
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