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  • 1. Bethge, O.
    et al.
    Pozzovivo, G.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Abermann, S.
    Bertagnolli, E.
    Fabrication of highly ordered nanopillar arrays and defined etching of ALD-grown all-around platinum films2012In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 8, p. 085013-Article in journal (Refereed)
    Abstract [en]

    Highly ordered arrays of silicon nanopillars are etched by means of induced-coupled-plasma reactive-ion etching (RIE). The sulfur hexafluoride/oxygen (SF6/O-2)-based cryogenic process allows etching of nanopillars with an aspect ratio higher than 20:1 and diameters down to 30 nm. Diameters can be further reduced by a well-controllable oxidation process in O-2-ambient and a subsequent etching in hydrofluoric acid. This approach effectively removes surface contaminations induced by former RIE, as shown by x-ray photoelectron spectroscopy. Atomic layer deposition (ALD) is used to establish an all-around Al2O3/Pt stack onto the vertically aligned nanorods. Two approaches are successfully applied to remove the resistant Pt coating from the nanopillar tips.

  • 2. Bethge, O.
    et al.
    Zimmermann, C.
    Lutzer, B.
    Simsek, S.
    Smoliner, J.
    Stoeger-Pollach, M.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bertagnolli, E.
    Effective reduction of trap density at the Y2O3/Ge interface by rigorous high-temperature oxygen annealing2014In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 116, no 21, p. 214111-Article in journal (Refereed)
    Abstract [en]

    The impact of thermal post deposition annealing in oxygen at different temperatures on the Ge/Y2O3 interface is investigated using metal oxide semiconductor capacitors, where the yttrium oxide was grown by atomic layer deposition from tris(methylcyclopentadienyl) yttrium and H2O precursors on n-type (100)-Ge substrates. By performing in-situ X-ray photoelectron spectroscopy, the growth of GeO during the first cycles of ALD was proven and interface trap densities just below 1 x 10(11) eV(-1) cm(-2) were achieved by oxygen annealing at high temperatures (550 degrees C-600 degrees C). The good interface quality is most likely driven by the growth of interfacial GeO2 and thermally stabilizing yttrium germanate.

  • 3.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Valerio, Sven
    KTH, School of Information and Communication Technology (ICT).
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Deposition-Rate Atomic Layer Deposition of Thulium Oxide from TmCp3 and H2O2013In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 160, no 11, p. D538-D542Article in journal (Refereed)
    Abstract [en]

    A novel process for atomic layer deposition of thulium oxide (Tm2O3) has been developed, employing TmCp3 as metal precursor and H2O as oxidizing agent. The use of a highly reactive oorganometallic precursor eliminates the need for a strong oxidizing agent (such as O-3) and provides a high deposition rate of similar to 1.5 angstrom/cycle. A thorough characterization of the process has been performed, identifying true ALD-type film growth in the temperature range 200-300 degrees C. The ALD process has been further investigated by extensive physical and electrical characterization of the deposited films in terms of-composition, crystalline phase, surface roughness and extraction of the dielectric constant. The films were found to be oxygen-rich Tm2O3, with low carbon impurity content at low deposition temperature and after annealing at 600 degrees C. The developed process produced polycrystalline films, with a surface roughness <1 nm RMS. Integration in MOS capacitors demonstrated well-behaved CV curves after annealing at 600 degrees C, with a relative dielectric constant of similar to 16.

  • 4.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of thulium silicate interfacial layer for high-k/metal gate MOSFETs2013In: 2013 14th International Conference On Ultimate Integration On Silicon (ULIS), IEEE , 2013, p. 122-125Conference paper (Refereed)
    Abstract [en]

    The possibility of integrating thulium silicate as IL (interfacial layer) in scaled high-klmetal gate stacks is explored. Electrical properties of the silicate IL are investigated in MOS capacitor structures for the silicate formation temperature range 500-900 degrees C. Results are compared to lanthanum silicate. A CMOS-compatible process flow for silicate formation is demonstrated, providing EOT of the IL as low as 0.1-0.3 nm and interface state density at flatband below 2.10(11) cm(-2)eV(-1). The silicate IL is found to be compatible with both gate-last and gate-first process flows, with a maximum thermal budget of 1000 degrees C.

  • 5.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Electrical characterization of thulium silicate interfacial layers for integration in high-k/metal gate CMOS technology2014In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 98, p. 20-25Article in journal (Refereed)
    Abstract [en]

    This work presents a characterization of the electrical properties of thulium silicate thin films, within the scope of a possible application as IL (interfacial layer) in scaled high-k/metal gate CMOS technology. Silicate formation is investigated over a wide temperature range (500-900 degrees C) through integration in MOS capacitor structures and analysis of the resulting electrical properties. The results are compared to those obtained from equivalent devices integrating lanthanum silicate interfacial layers. The thulium silicate IL is formed through a gate-last CMOS-compatible process flow, providing IL EOT of 0.1-0.3 nm at low formation temperature and interface state density at flatband condition below 2 x 10(11) cm(-2) eV(-1). The effects of a possible integration in a gate-first process flow with a maximum thermal budget of 1000 degrees C are also evaluated, achieving an IL EOT of 0.2-0.5 nm, an interface state density at flatband condition similar to 1 x 10(11) cm(-2) eV(-1) and a reduction in gate leakage current density of one order of magnitude compared to the same stack without IL.

  • 6.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    In situ SiOx interfacial layer formation for scaled ALD high-k/metal gate stacks2012In: 2012 13th International Conference on Ultimate Integration on Silicon, ULIS 2012, IEEE , 2012, p. 105-108Conference paper (Refereed)
    Abstract [en]

    This work addresses the issue of interfacial layer formation in scaled high-k/metal gate stacks: the possibility of growing a thin SiOx interfacial layer in situ in a commercial ALD reactor has been evaluated, employing ozone-based Si oxidation. Three techniques (O3, O3/H2O and Pulsed) have been developed to grow scaled sub-nm interfacial layers and have been integrated in MOS capacitors and MOSFETs. A comparison based on electrical characterization shows that the performance of the proposed in situ methods is comparable or superior to that of existing ex situ techniques; specifically, the O3 method can grow aggressively scaled interfacial layers (4-5 A) while preserving the electrical quality of the stack.

  • 7.
    Dentoni Litta, Eugenio
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Thulium silicate interfacial layer for scalable high-k/metal gate stacks2013In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, no 10, p. 3271-3276Article in journal (Refereed)
    Abstract [en]

    Interfacial layer (IL) control in high-k/metal gate stacks is crucial in achieving good interface quality, mobility, and reliability. A process is developed for the formation of a thulium silicate IL that can be integrated as a replacement for conventional chemical oxide ILs in gate-last high-k/metal gate CMOS process. A straightforward process integration scheme for thulium silicate IL is demonstrated, based on self-limiting silicate formation in inert gas atmosphere and with good selectivity of the etching step. The thulium silicate IL is shown to provide 0.25~{!@~}0.15 nm equivalent oxide thickness of the IL while preserving excellent electrical quality of the interface with Si. An interface state density ~0.7-21011 cm-2eV-1 was obtained at flat-band condition, and the nFET and pFET subthreshold slopes were 70 mV/dec. The inversion layer mobility was 20% higher than for the reference SiOx/HfO2 gate stack. Specifically, the measured mobility values were 230 cm2/ Vs for nFET and 60 cm2/Vs for pFET devices, at an inversion charge density of 1013 cm?2 and at a total capacitance equivalent thickness of 1.6 nm.

  • 8.
    Hallén, Anders
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Usman, M.
    Suvanam, Sethu Saveda
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Martin, David M.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Linnarsson, Margareta K.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Passivation of SiC device surfaces by aluminum oxide2014In: IOP Conference Series: Materials Science and Engineering, ISSN 1757-8981, E-ISSN 1757-899X, Vol. 56, no 1, p. 012007-Article in journal (Refereed)
    Abstract [en]

    A steady improvement in material quality and process technology has made electronic silicon carbide devices commercially available. Both rectifying and switched devices can today be purchased from several vendors. This successful SiC development over the last 25 years can also be utilized for other types of devices, such as light emitting and photovoltaic devices, however, there are still critical problems related to material properties and reliability that need to be addressed. This contribution will focus on surface passivation of SiC devices. This issue is of utmost importance for further development of SiC MOSFETs, which so far has been limited by reliability and low charge carrier surface mobilities. Also bipolar devices, such as BJTs, LEDs, or PV devices will benefit from more efficient and reliable surface passivation techniques in order to maintain long charge carrier lifetimes. Silicon carbide material enables the devices to operate at higher electric fields, higher temperatures and in more radiation dense applications than silicon devices. To be able to utilize the full potential of the SiC material, it is therefore necessary to develop passivation layers that can sustain these more demanding operation conditions. In this presentation it will also be shown that passivation layers of Al2O3 deposited by atomic layer deposition have shown superior radiation hardness properties compared to traditional SiO2-based passivation layers.

  • 9.
    Henkel, Christoph
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bethge, O.
    Stöger-Pollach, M.
    Bertagnolli, E.
    Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks2011In: European Solid-State Device Res. Conf., 2011, p. 75-78Conference paper (Refereed)
    Abstract [en]

    The current work is discussing the surface passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition for use in Ge-based MOSFET devices. The improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing agencies in presence of thin Pt cap layers are investigated. The results suggest the formation of thin intermixed La xGeyOz interfacial layers with thicknesses controllable by oxidation time. An additional reduction treatment further improves the electrical properties of the gate dielectrics in contact to the Ge substrate. The scaling potential of the respective layered gate dielectrics used in MOS-based device structures is discussed. As a result low interface trap densities of the ALD deposited La2O3/ZrO2 layers on (100) Ge down to 3·1011 eV-1 cm -2 are demonstrated. A trade-off between improved interface trap density and equivalent oxide thickness is found.

  • 10.
    Henkel, Christoph
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Stoeger-Pollach, Michael
    Bethge, Ole
    Bertagnolli, Emmerich
    Impact of oxidation and reduction annealing on the electrical properties of Ge/La2O3/ZrO2 gate stacks2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, p. 7-12Article in journal (Refereed)
    Abstract [en]

    The paper addresses the passivation of Germanium surfaces by using layered La2O3/ZrO2 high-k dielectrics deposited by Atomic Layer Deposition to be applied in Ge-based MOSFET devices. Improved electrical properties of these multilayered gate stacks exposed to oxidizing and reducing ambient during thermal post treatment in presence of thin Pt cap layers are demonstrated. The results suggest the formation of thin intermixed LaxGeyOz interfacial layers with thicknesses controllable by oxidation time. This formation is further investigated by XPS, EDX/EELS and TEM analysis. An additional reduction annealing treatment further improves the electrical properties of the gate dielectrics in contact with the Ge substrate. As a result low interface trap densities on (100) Ge down to 3 x 10(11) eV(-1) cm(-2) are demonstrated. The formation of the high-k LaxGeyOz, layer is in agreement with the oxide densification theory and may explain the improved interface trap densities. The scaling potential of the respective layered gate dielectrics used in Ge-based MOS-based device structures to EOT of 1.2 nm or below is discussed. A trade-off between improved interface trap density and a lowered equivalent oxide thickness is found.

  • 11. Mitrovic, I. Z.
    et al.
    Althobaiti, M.
    Weerakkody, A. D.
    Sedghi, N.
    Hall, S.
    Dhanak, V. R.
    Chalker, P. R.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interface engineering of Ge using thulium oxide: Band line-up study2013In: Microelectronic Engineering, ISSN 0167-9317, E-ISSN 1873-5568, Vol. 109, p. 204-207Article in journal (Refereed)
    Abstract [en]

    This paper investigates the band line-up and optical properties (dielectric function) of Tm2O3/Ge gate stacks deposited by atomic layer deposition. X-ray photoelectron spectroscopy has been performed to ascertain the shallow core levels (Ge3d and Tm4d) in ultra-thin and bulk Tm2O3/Ge stacks as well as valence band maxima in Ge and bulk Tm2O3. The valence band offset of Tm2O3/Ge has been found to be 2.95 +/- 0.08 eV. Vacuum ultra violet variable angle spectroscopic ellipsometry studies reveal the indirect band gap nature of Tm2O3, with the value extracted from the Tauc method of 5.3 +/- 0.1 eV. A distinct absorption feature is observed at similar to 3.2 eV below the band gap of Tm2O3, and clearly distinguished from the Si and Ge critical points. A dielectric constant of 14 to 15 has been derived from the electrical measurements on 5 nm Tm2O3/epi Ge/Si gate stacks. The band line-up study of Tm2O3/Ge implies an acceptable barrier for holes (2.95 eV) and electrons (greater than 1.7 eV) for Ge MOSFET engineering.

  • 12. Mitrovic, I. Z.
    et al.
    Althobaiti, M.
    Weerakkody, A. D.
    Sedghi, N.
    Hall, S.
    Dhanak, V. R.
    Mather, S.
    Chalker, P. R.
    Tsoutsou, D.
    Dimoulas, A.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Litta, Eugenio D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Interface engineering routes for a future cmos ge-based technology2014In: ECS Transactions, 2014, no 2, p. 73-88Conference paper (Refereed)
    Abstract [en]

    We present an overview study of two germanium interface engineering routes, firstly a germanate formation via La2O3 and Y2O3, and secondly a barrier layer approach using Al2O3 and Tm2O3. The interfacial composition, uniformity, thickness, band gap, crystallinity, absorption features and valence band offset are determined using X-ray photoelectron spectroscopy, ultra violet variable angle spectroscopic ellipsometry, and high resolution transmission electron microscopy. The correlation of these results with electrical characterization data make a case for Ge interface engineering with rare-earth inclusion as a viable route to achieve high performance Ge CMOS.

  • 13. Mitrovic, I. Z.
    et al.
    Hall, S.
    Althobaiti, M.
    Hesp, D.
    Dhanak, V. R.
    Santoni, A.
    Weerakkody, A. D.
    Sedghi, N.
    Chalker, P. R.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits. X-FAB Semiconductor Foundries AG, Germany.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Tan, H.
    Schamm-Chardon, S.
    Atomic-layer deposited thulium oxide as a passivation layer on germanium2015In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 117, no 21, article id 214104Article in journal (Refereed)
    Abstract [en]

    A comprehensive study of atomic-layer deposited thulium oxide (Tm2O3) on germanium has been conducted using x-ray photoelectron spectroscopy (XPS), vacuum ultra-violet variable angle spectroscopic ellipsometry, high-resolution transmission electron microscopy (HRTEM), and electron energy-loss spectroscopy. The valence band offset is found to be 3.05±0.2eV for Tm2O3/p-Ge from the Tm 4d centroid and Ge 3p3/2 charge-corrected XPS core-level spectra taken at different sputtering times of a single bulk thulium oxide sample. A negligible downward band bending of ∼0.12eV is observed during progressive differential charging of Tm 4d peaks. The optical band gap is estimated from the absorption edge and found to be 5.77eV with an apparent Urbach tail signifying band gap tailing at ∼5.3eV. The latter has been correlated to HRTEM and electron diffraction results corroborating the polycrystalline nature of the Tm2O3 films. The Tm2O3/Ge interface is found to be rather atomically abrupt with sub-nanometer thickness. In addition, the band line-up of reference GeO2/n-Ge stacks obtained by thermal oxidation has been discussed and derived. The observed low reactivity of thulium oxide on germanium as well as the high effective barriers for holes (∼3eV) and electrons (∼2eV) identify Tm2O3 as a strong contender for interfacial layer engineering in future generations of scaled high-κ gate stacks on Ge.

  • 14.
    Naiini, Maziar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    ALD high-k layer grating couplers for single and double slot on-chip SOI photonics2011In: 41st European Solid-State Device Research Conference, ESSDERC 2011, 2011, p. 191-194Conference paper (Refereed)
    Abstract [en]

    State of the art grating couplers for horizontal single and double slot waveguides are presented; in these devices the input signal is transmitted from a single mode optical fiber to silicon on insulator slot waveguides. In the waveguides, atomic layer deposited (ALD) high-k dielectrics form the low refractive index slot. It is demonstrated that the new fully etched design combined with precision of ALD result in highly reproducible devices with efficiency variations less than 1%. Devices have a peak coupling efficiency of 24% at 1.55 &#x03BC;m. In order to achieve the optimal design, optical properties of high-k films are studied with spectroscopic ellipsometry. Measured refractive indices show variations from reference values, originated from film densities.

  • 15.
    Naiini, Maziar
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Low loss high-k slot waveguides for silicon photonics2013In: Dev. Res. Conf. Conf. Dig., IEEE conference proceedings, 2013, p. 95-96Conference paper (Refereed)
    Abstract [en]

    Silicon photonic integrated circuits are promising solutions for high speed on-chip data communication. Producing crystalline silicon optical waveguides at the backend of the IC process flow requires wafer-bonding and a deep substrate etching of an SOI wafer. Fabrication of optical interconnects is less complex and more cost effective if deposited amorphous silicon can be used instead. Amorphous silicon on the other hand suffers from a high absorption. Slot waveguide is a suitable solution for integration of alternative materials with silicon waveguides. Active devices with slot waveguides have been reported by Ramirez et al where the slot layer is doped with rare-earth metals to generate light. In this work successful fabrication and characterization of CMOS compatible low loss high-k amorphous silicon slot waveguides is reported.

  • 16.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    ALD high-k layer grating couplers for single and double slot on-chip SOI photonics2012In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 74, p. 58-63Article in journal (Refereed)
    Abstract [en]

    State of the art grating couplers for horizontal single and double slot waveguides are presented; in these devices the input signal is transmitted from a single mode optical fiber to silicon on insulator slot waveguide. In the waveguides, atomic layer deposited (ALD) high-k dielectrics form the low refractive index slot. It is demonstrated that a fully etched design combined with precision of ALD result in highly reproducible devices with theoretical efficiency variations less than 1%. Devices have a peak calculated coupling efficiency of 24% at 1.55 mu m. In order to achieve an optimal design, optical properties of high-k films are studied by spectroscopic ellipsometry. Measured refractive indices show variations from reference values, originated from film variation in densities. Chips with a test slot material are fabricated and the optical efficiency of the couplers is characterized. The maximum measured coupling efficiency of the couplers is 18.5%.

  • 17.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    CMOS compatible ALD high-k double slot grating couplers for on-chip optical interconnects2012In: Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European, IEEE , 2012, p. 93-96Conference paper (Refereed)
    Abstract [en]

    Silicon-on-insulator(SOI) novel on-chip grating couplers for double slot high-k waveguides are experimentally demonstrated. The devices were fabricated with standard CMOS process technology. The grating couplers were designed for the best performance at the C-band communication range. Two thin layers of aluminum oxide formed the slot region of the waveguide. The high-k layers were deposited using the atomic layer deposition (ALD) method. A reliable process was realized by etching the structures to the buried oxide. Effect of the top oxide cladding layer on the efficiency was studied. The grating couplers had a measured efficiency of 22% at 1.55μm wavelength. This efficiency is competitive to other results reported by other groups.

  • 18.
    Naiini, Maziar M.
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Double slot high-k waveguide grating couplers for silicon photonics2012In: Device Research Conference (DRC), 2012 70th Annual, IEEE , 2012, p. 69-70Conference paper (Refereed)
    Abstract [en]

    Novel on-chip double slot high-k waveguide grating couplers have been successfully fabricated, and characterized. Silicon cannot yet be directly used for light generation and modulation in photonic devices because of its weak nonlinear optical effects. Slot waveguide is a solution to this problem, this structure consists of silicon and low refractive index material layers as the active material[1, 2]. Previously, grating couplers were demonstrated for horizontal single slot SiO 2 waveguides [3, 4]. Double slot waveguide is of great interest since the confinement of the optical power in the active material is significantly larger. Atomic layer deposited (ALD) high-k aluminum oxide (Al 2O 3) was used as the slot layer because of a superior layer quality and thickness uniformity. The ultimate goal of this work is the demonstration of the highly reproducible on-chip photonic devices.

  • 19.
    Usman, Muhammad
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hallén, Anders
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    HfO2/Al2O3 bilayered high-k dielectric for passivation and gate insulator in 4H-SiC devices2013In: ECS Journal of Solid State Science and Technology, ISSN 2162-8769, Vol. 2, no 8, p. N3087-N3091Article in journal (Refereed)
    Abstract [en]

    The electrical and chemical properties of high-k dielectric stacks consisting of Hafnium oxide (HfO2) and Aluminum oxide (Al 2O3) deposited on 4H-SiC have been investigated by preparing metal insulator semiconductor (MIS) structures of HfO 2/Al2O3/SiC. The bilayer gate stack was deposited by using atomic layer deposition (ALD). The samples were also treated by rapid thermal annealing (RTA) at 970°C for 5 mins in an inert gas atmosphere. Structural properties of the deposited films were analyzed with X-ray diffraction (XRD), atomic force microscopy (AFM) and Rutherford backscattering spectroscopy (RBS). Capacitance-voltage (CV) measurements performed on as-deposited and RTA treated structures at room temperature show that the RTA treatment increases the effective oxide charges in the whole dielectric but decreases the interface trap density. Current-voltage (IV) measurements have been performed in order to extract the leakage current density as well as the breakdown characteristics of the stack. Our results show that a combination of HfO2 and Al2O3 can be a better choice for SiC than individual Al2O3 layer because of the higher value of effective dielectric constant. It is shown that the stacked dielectrics are stable at high temperatures and under annealing conditions up to 300°C, which makes the layers compatible with SiC device processing and higher operating temperatures compared to silicon.

  • 20.
    Vaziri, Sam
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lupina, Grzegorz
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dabrowski, Jarek
    Lippert, Gunther
    Mehr, Wolfgang
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A Graphene-Based Hot Electron Transistor2013In: Nano letters (Print), ISSN 1530-6984, E-ISSN 1530-6992, Vol. 13, no 4, p. 1435-1439Article in journal (Refereed)
    Abstract [en]

    We experimentally demonstrate DC functionality of graphene-based hot electron transistors, which we call graphene base transistors (GBT). The fabrication scheme is potentially compatible with silicon technology and can be carried out at the wafer scale with standard silicon technology. The state of the GBTs can be switched by a potential applied to the transistor base, which is made of graphene. Transfer characteristics of the GBTs show ON/OFF current ratios exceeding 10(4).

  • 21.
    Vaziri, Sam
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lupina, Grzegorz
    Paussa, Alan
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lippert, Gunther
    Dabrowski, Jarek
    Mehr, Wolfgang
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    A manufacturable process integration approach for graphene devices2013In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 84, p. 185-190Article in journal (Refereed)
    Abstract [en]

    In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for future integration of graphene in microelectronics: bottom gates with ultra-thin (2 nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing. We assess, through simulation, the effects of the quantum capacitance and band bending in the silicon substrate on the effective electric fields in the top and bottom gate oxide. The proposed process technology is suitable for other graphene-based devices such as graphene-based hot electron transistors and photodetectors.

  • 22.
    Vaziri, Sam
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lupina, G.
    Lippert, G.
    Dabrowski, J.
    Mehr, W.
    An integration approach for graphene double-gate transistors2012In: Solid-State Device Research Conference (ESSDERC), 2012 Proceedings of the European, IEEE , 2012, p. 250-253Conference paper (Refereed)
    Abstract [en]

    In this work, we propose an integration approach for double gate graphene field effect transistors. The approach includes a number of process steps that are key for microelectronics integration: bottom gates with ultra-thin (2nm) high-quality thermally grown SiO2 dielectrics, shallow trench isolation between devices and atomic layer deposited Al2O3 top gate dielectrics. The complete process flow is demonstrated with fully functional GFET transistors and can be extended to wafer scale processing and other graphene-based devices.

  • 23.
    Östling, Mikael
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Henkel, Christoph
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Naiini, Maziar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Olyaei, Maryam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Vaziri, Sam
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bethge, O.
    Bertagnolli, E.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Atomic layer deposition-based interface engineering for high-k/metal gate stacks2012In: ICSICT 2012 - 2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, Proceedings, IEEE , 2012, p. 6467643-Conference paper (Refereed)
    Abstract [en]

    This review will discuss the in-situ surface engineering of active channel surfaces prior to or during the ALD high-k/metal gate deposition process. We will show that by carefully choosing ALD in-situ pre-treatment methods and precursor chemistries relevant electrical properties for future high-k dielectrics can be improved. Different high-k dielectrics such as Hafnium-Oxide (HfO2), Aluminum-Oxide (Al2O3), Lanthanum-Lutetium-Oxide (LaLuO3) and Lanthanum-Oxide (La 2O3) for CMOS-based device technology are investigated in combination with Silicon (Si) and Germanium (Ge) substrates. Additionally, the use of ALD for deposition of a high-k dielectric gate stack on Graphene is discussed.

1 - 23 of 23
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