Change search
Refine search result
1 - 5 of 5
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Lu, Zhonghai
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Thid, Rikard
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Millberg, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Nilsson, Erland
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    NNSE: Nostrum Network-on-Chip Simulation Environment2005In: Proceedings of Swedish System-on-Chip Conference, Stockholm, Sweden, April 2005., 2005Conference paper (Other academic)
    Abstract [en]

    A main challenge for Network-on-Chip (NoC) design isto select a network architecture that suits a particular application.NNSE enables to analyze the performance impactof NoC configuration parameters. It allows one to(1) configure a network with respect to topology, flow controland routing algorithm etc.; (2) configure various regularand application specific traffic patterns; (3) evaluatethe network with the traffic patterns in terms of latency and throughput.

  • 2.
    Millberg, Mikael
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nilsson, Erland
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Thid, Rikard
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Guaranteed bandwidth using looped containers in temporally disjoint networks within the Nostrum network on chip2004In: Design, Automation And Test In Europe Conference And Exhibition, Vols 1 And 2, Proceedings / [ed] Gielen G, Figueras J, LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2004, p. 890-895Conference paper (Refereed)
    Abstract [en]

    In today's emerging Network-on-Chips, there is a need for different traffic classes with different Quality-of-Service guarantees. Within our NoC architecture Nostrum, we have implemented a service of Guaranteed Bandwidth (GB), and latency, in addition to the already existing service of Best-Effort (BE) packet delivery. The guaranteed bandwidth is accessed via Virtual Circuits (VC). The vcs are implemented using a combination of two concepts that we call 'Looped Containers' and 'Temporally Disjoint Networks'. The Looped Containers are used to guarantee access to the network - independently of the current network load without dropping packets; and the TDNS are used in order to achieve several VCs, plus ordinary BE traffic, in the network. The TDNS are a consequence of the deflective routing policy used, and gives rise to an explicit time-division-multiplexing within the network. To prove our concept an HDL implementation has been synthesised and simulated. The cost in terms of additional hardware needed, as well as additional bandwidth is very low - less than 2 percent in both cases! Simulations showed that ordinary BE traffic is practically unaffected by the VCs.

  • 3.
    Millberg, Mikael
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Nilsson, Erland
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Thid, Rikard
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kumar, S.
    Jantsch, Axel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    The Nostrum Backbone: a Communication Protocol Stack for Networks Chip2004In: 17th International Conference On Vlsi Design, Proceedings - Design Methodologies For The Gigascale Era, LOS ALAMITOS, USA: IEEE COMPUTER SOC , 2004, p. 693-696Conference paper (Refereed)
    Abstract [en]

    We propose a communication protocol stack to be used in Nostrum, our Network on Chip (NoC) architecture. In order to aid the designer in the selection process of what parts of protocols, and their respective facilities, to include, a layered approach to communication is taken. A nomenclature for describing the individual layers' interfaces and service definitions of the layers in the protocol stack is suggested,and used. The concept includes support for best effort traffic packet delivery as well as support for guaranteed bandwidth traffic, using virtual circuits. Furthermore an application to NoC adapter is defined, as part of the Resource to Network Interface, and is used to communicate between the Nostrum protocol stack and the application. An industrial example has been implemented, simulated, and the results justifies the suggested layered approach.

  • 4.
    Thid, Rikard
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Millberg, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Jantsch, Axel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Evaluating NoC communication backbones with simulation2003In: Proceedings of the 21th NorChip Conference, IEEE conference proceedings, 2003, p. 27-30Conference paper (Refereed)
    Abstract [en]

    This paper describes a Network on Chip simulatorthat was developed to evaluate our NoC architecture Nostrum.It is shown how SystemC’s features for communicationrefinement is used to make a highly flexible simulator.The simulator is reconfigurable so that it is possibleto try different NoC platforms and different mappingsof workloads. In addition to the modeling of our Nostrumarchitecture, a bus-based architecture is modeled aswell, and the performance for a simple workload modelis compared.

  • 5.
    Thid, Rikard
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Flexible bus and NoC performance analysis with configurable synthetic workloads2006In: DSD 2006: 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools, Proceedings / [ed] Muthukumar, V, 2006, p. 681-688Conference paper (Refereed)
    Abstract [en]

    We present a flexible method for bus and network on chip performance analysis, which is based on the adaptation of workload models to resemble various applications. Our analysis method assists in the selection of a communication infrastructure early in the design process. The method uses (1) synthetic workload models which are similar to timed Petri nets and (2) the b-model for self-similar workloads. This allows the exploration of larger portions of the design space than possible with traditional stochastic models. The method is illustrated with tutorial examples where both a No C and a bus based platform are analyzed.

1 - 5 of 5
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf