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  • 1.
    Badel, Xavier
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Linnros, Jan
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Doping of electrochemically etched pore arrays in n-type silicon: processing and electrical characterization2005In: Journal of the Electrochemical Society, ISSN 0013-4651, E-ISSN 1945-7111, Vol. 152, no 4, p. G252-G258Article in journal (Refereed)
    Abstract [en]

    Silicon p-n diodes formed in the walls of deep pores have been electrically characterized. The pores were electrochemically etched in low-doped n-type silicon substrates, and the entire pore array was doped p(+) by boron diffusion at 1050 degrees C. Two different process flows were investigated to disconnect the p(+) layers from one pore to another. The first consists of removing a few micrometers of silicon at the top of the sample using reactive ion etching after diffusion while the second enables the prevention of doping at the top of the pore walls with an oxide, acting as a barrier during diffusion. Current-voltage and capacitance-voltage characteristics of p-n junctions are presented and related parameters, such as the serial resistance and the ideality factor are discussed. The results show good rectifying behavior of the diodes with a reverse current about four to five decades smaller than the forward current. Measurements with two pores connected in a transistor-like configuration (p(+)/n(-)/p(+)), were also performed. Device simulations were used to examine the device behavior. Finally, our results demonstrate that pores could work as individual detector pixels for moderate reverse voltages, suitable for radiation imaging applications.

  • 2. Buchholt, K.
    et al.
    Eklund, P.
    Jensen, J.
    Lu, J.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Behan, G.
    Zhang, H.
    Spetz, A. Lloyd
    Hultman, L.
    Growth and characterization of epitaxial Ti3GeC2 thin films on 4H-SiC(0001)2012In: Journal of Crystal Growth, ISSN 0022-0248, E-ISSN 1873-5002, Vol. 343, no 1, p. 133-137Article in journal (Refereed)
    Abstract [en]

    Epitaxial Ti3GeC2 thin films were deposited on 4 degrees off-cut 4H-SiC(0001) using magnetron sputtering from high purity Ti, C, and Ge targets. Scanning electron microscopy and helium ion microscopy show that the Ti3GeC2 films grow by lateral step-flow with {11 (2) over bar0} faceting on the SiC surface. Using elastic recoil detection analysis, atomic force microscopy, and X-Ray diffraction the films were found to be substoichiometric in Ge with the presence of small Ge particles at the surface of the film.

  • 3. Buchholt, Kristina
    et al.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, J.
    Eklund, Per
    Hultman, Lars
    Lloyd Spetz, Anita
    Ohmic contact properties of magnetron sputtered Ti3SiC2 on n- and p-type 4H-silicon carbide2011In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 98, no 4, p. 042108-Article in journal (Refereed)
    Abstract [en]

    Epitaxial Ti3SiC2 (0001) thin film contacts were grown on doped 4H-SiC (0001) using magnetron sputtering in an ultra high vacuum system. The specific contact resistance was investigated using linear transmission line measurements. Rapid thermal annealing at 950 degrees C for 1 min of as-deposited films yielded ohmic contacts to n-type SiC with contact resistances in the order of 10(-4) Omega cm(2). Transmission electron microscopy shows that the interface between Ti3SiC2 and n-type SiC is atomically sharp with evidence of interfacial ordering after annealing. (c) 2011 American Institute of Physics.

  • 4.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Current Gain Degradation in 4H-SiC Power BJTs2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 702-705Article in journal (Refereed)
    Abstract [en]

    SiC airs are very attractive for high power application, but long term stability is still problematic and it could prohibit commercial production of these devices. The aim of this paper is to investigate the current gain degradation in BJTs with no significant degradation of the on-resistance. Electrical measurements and simulations have been used to characterize the behavior of the BJT during the stress test. Current gain degradation occurs, the gain drops from 58 before stress to 43 after 40 hours, and, moreover, the knee current shows fluctuations in its value during the first 20 hours. Current gain degradation has been attributed to increased interface traps or reduced lifetime in the base-emitter region or small stacking faults in the base-emitter region, while fluctuations of the knee current might be due to stacking faults in the collector region.

  • 5.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of Emitter Width and Emitter-Base Distance on the Current Gain in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 10, p. 2664-2670Article in journal (Refereed)
    Abstract [en]

    The influence of the emitter-base geometry on the current gain has been investigated by means of measurements and simulations. Particular attention has been placed on the emitter width and on the distance between the emitter edge and the base contact. When the emitter width is decreased from 40 to 8 mu m, the current gain is reduced by 20%, whereas when the distance between the base contact and the emitter edge is decreased from 5 to 2 mu m, the current gain is reduced by 10%. Simulations have been used to investigate the reasons for the current gain reduction. The reduction of the emitter width induces two mechanisms of current gain reduction: earlier forward biasing of the base-collector junction and higher recombination in the emitter region. Both mechanisms result from the higher current density flowing under the emitter region. Placing the base contact very close to the emitter edge increases the base current by increasing the gradient of the electron concentration toward the base contact. The effect of increasing the base doping in the extrinsic region has been simulated, and the results demonstrate that the current gain can be improved if a high doping concentration in the range of 5 x 10(18) cm(-3) is used.

  • 6.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of Current Gain Versus Temperature in 4H-SiC Power BJTs2010In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 57, no 3, p. 704-711Article in journal (Refereed)
    Abstract [en]

    Accurate physical modeling has been developed to describe the current gain of silicon carbide (SiC) power bipolar junction transistors (BJTs), and the results have been compared with measurements. Interface traps between SiC and SiO2 have been used to model the surface recombination by changing the trap profile, capture cross section, and concentration. The best agreement with measurement is obtained using one single energy level at 1 eV above the valence band, a capture cross section of 1 x 10(-15) cm(2), and a trap concentration of 2 x 10(12) cm(-2). Simulations have been performed at different temperatures to validate the model and characterize the temperature behavior of SiC BJTs. An analysis of the carrier concentration at different collector currents has been performed in order to describe the mechanisms of the current gain fall-off at a high collector current both at room temperature and high temperatures. At room temperature, high injection in the base ( which has a doping concentration of 3 x 10(17) cm(-3)) and forward biasing of the base-collector junction occur simultaneously, causing an abrupt drop of the current gain. At higher temperatures, high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the acting mechanism for the current gain fall-off. Forward biasing of the base-collector junction can also explain the reduction of the knee current with increasing temperature by means of the negative temperature dependence of the mobility.

  • 7.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Temperature Modeling and Characterization of the Current Gain in 4H-SiC Power BJTs2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, p. 1061-1064Article in journal (Refereed)
    Abstract [en]

    The current gain of 4H-SiC BJTs has been modeled using interface traps between SIC and SiO2 to describe surface recombination, by a positive temperature dependence of the carrier lifetime in the base region and by bandgap narrowing in the emitter region. The interface traps have been modeled by one single level at 1 eV above the valence band, with capture cross section of 1 x 10(-15) cm(2) and concentration of 2 x 10(12) cm(-2). The temperature behavior of SiC BJTs has been simulated and the results have been compared with measurements. An analysis of the carrier concentration has been performed in order to describe the mechanisms for fall-off of the current gain at high collector current. At room temperature high injection in the base and forward biasing of the base-collector junction occur simultaneously causing an abrupt drop of the current gain. At higher temperatures high injection in the base is alleviated by the higher ionization degree of the aluminum dopants, and then forward biasing of the base-collector junction is the only acting mechanism for the current gain fall-off at high collector current. This mechanism and the negative temperature dependence of the carrier mobility can also explain the reduction of the knee current for gain fall-off with increasing temperature. Simulations with different emitter widths have been also performed and analyzed to characterize the emitter size effect. Higher current density caused by reducing the emitter width introduces higher carrier recombination in the emitter region, leading to a reduction of the current gain.

  • 8.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Bengt Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modeling and Characterization of the ON-Resistance in 4H-SiC Power BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 7, p. 2081-2087Article in journal (Refereed)
    Abstract [en]

    The ON-resistance of silicon carbide bipolar transistors is characterized and simulated. Output characteristics are compared at different base currents and different temperatures in order to validate the physical model parameters. A good agreement is obtained, and the key factors, which limit the improvement of R-ON, are identified. Surface recombination and material quality play an important role in improving device performances, but the device design is also crucial. Based on simulation results, a design that can enhance the conductivity modulation in the lowly doped drift region is proposed. By increasing the base doping in the extrinsic region, it is possible to meet the requirements of having low voltage drop, high current density, and satisfactory forced current gain. According to simulation results, if the doping is 5 x 10(18) cm(-3), it is possible to conduct 200 A/cm(2) at V-CE = 1 V by having a forced current gain of about 8, which represents a large improvement, compared with the simulated value of only one in the standard design.

  • 9.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Investigation of Current Gain Degradation in 4H-SiC Power BJTs2012In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 717-720, p. 1131-1134Article in journal (Refereed)
    Abstract [en]

    The current gain degradation of 4H-SiC BJTs with no significant drift of the on-resistance is investigated. Electrical stress on devices with different emitter widths suggests that the device design can influence the degradation behavior. Analysis of the base current extrapolated from the Gummel plot indicates that the reduction of the carrier lifetime in the base region could be the cause for the degradation of the gain. However, analysis of the base current of the base-emitter diode shows that the degradation of the passivation layer could also influence the reduction of the current gain.

  • 10.
    Buono, Benedetto
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl -Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simulations of Open Emitter Breakdown Voltage in SiC BJTs with non Implanted JTE2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 615-617, p. 841-844Article in journal (Refereed)
    Abstract [en]

    Ion implantation for selective doping of SiC is problematic due to damage generation during the process and low activation of dopants. In SiC bipolar junction transistor (BJT) the junction termination extension (JTE) can be formed without ion implantation using instead a controlled etching into the epitaxial base. This etched JTE is advantageous because it eliminates ion implantation induced damage and the need for high temperature annealing. However, the dose, which is controlled by the etched base thickness and doping concentration, plays a crucial role. In order to find the optimum parameters, device simulations of different etched base thicknesses have been performed using the software Sentaurus Device. A surface passivation layer consisting of silicon dioxide, considering interface traps and fixed trapped charge, has been included in the analysis by simulations. Moreover a comparison with measured data for fabricated SiC BJTs has been performed.

  • 11. Chen, M.
    et al.
    Lutz, J.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Felsl, H. P.
    Schulze, H. -J
    A novel diode structure with controlled injection of backside holes (CIBH)2006Conference paper (Refereed)
    Abstract [en]

    In this paper we present a novel 3.3kV diode structure with controlled injection of backside holes, i.e. CIBH diode. This new diode structure features buried floating p layers at the cathode side. These p doped areas prevent the formation of high electric field strength at the nn+ junction and accordingly avoid the avalanche generation at the nn+ junction. The CIBH diode concept provides, compared to diodes without p layers and the same design, significantly improved dynamic ruggedness and improved sott reverse recovery at low current densities. Simulations and results of the first fabricated diodes show the readability of this new promising diode concept.

  • 12. Danielson, E.
    et al.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Forsberg, U.
    Janzen, E.
    Investigation of thermal properties in fabricated 4H-SiC high power bipolar transistors2003In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 47, no 4, p. 639-644Article in journal (Refereed)
    Abstract [en]

    Silicon carbide bipolar junction transistors have been fabricated and investigated. The transistors had a maximum current gain of approximately 10 times, and a breakdown voltage of 450 V. When operated at high power densities the device showed a clear self-heating effect, decreasing the current gain. The junction temperature was extracted during self-heating to approximately 150 degreesC, using the assumption that the current gain only depends on temperature. Thermal images of a device under operation were also recorded using an infrared camera, showing a significant temperature increase in the vicinity of the device. The device was also tested in a switched setup, showing fast turn on and turn off at 1 MHz and 300 V supply voltage. Device simulations have been used to analyze the measured data. The thermal conductivity is fitted against the self-heating, and the lifetime in the base is fitted against the measurement of the current gain.

  • 13.
    Danielsson, Erik
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schöner, Adolf
    Acreo AB.
    Hallin, Christer
    Department of Physics and Measurement Technology, Linköping University.
    A 4H-SiC BJT with an Epitaxially Regrown Extrinsic Base Layer2005In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 483-485, p. 905-908Article in journal (Refereed)
    Abstract [en]

    4H-SiC BJTs were fabricated using epitaxial regrowth instead of ion implantation to form a highly doped extrinsic base layer necessary for a good base ohmic contact. A remaining p(+) regrowth spacer at the edge of the base-emitter junction is proposed to explain a low current gain of 6 for the BJTs. A breakdown voltage of 1000 V was obtained for devices with Al implanted JTE.

  • 14.
    Danielsson, Erik
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Domeij, Martin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Schöner, Adolf
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Extrinsic base design of SiC bipolar transistors2004In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 457-460, no II, p. 1117-1120Article in journal (Refereed)
    Abstract [en]

    The SiC npn bipolar junction transistor (BJT) is a very promising device for high voltage and high power switches. The SiC BJT has, due to junction voltage cancellation, potentially a low on-resistance. However, the high resistivity in the base layer can induce a locally forward biased base collector junction and a premature current from the base to collector at on-state. In this work we propose a new technique to fabricate the extrinsic base using regrowth of the extrinsic base layer. This technique can put the highly doped region of the extrinsic base a few tenths of a micron from the intrinsic region. We also propose a new mobility model in our simulations to correctly account for the ionized impurities in minority carrier transport and elevated temperature.

  • 15.
    Domeij, Martin
    KTH, Superseded Departments, Electronics.
    Dynamic avalanche in Si and 4H-SiC power diodes1999Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Semiconductor power modules for the control of high currentsand high voltages have important applications in motor drives,traction and power transmission. Dynamic avalanche is of atechnological interest since it may limit the safe operatingarea for bipolar switching devices and for power diodes, whichare important integral parts of a power module. Dynamicavalanche is caused by a current-controlled space charge, whichmay enhance the electric field to the critical field strengthat voltages below the static breakdown voltage. Measurementsand simulations of reverse recovery at high power densitieswere performed for Si and 4H-SiC p+nn+power diodes to investigate the failure limitcaused by dynamic avalanche. A special optical measurementtechnique was used to eliminate influence of the junction edgeand thereby probe the bulk diode area.

    It was found experimentally that it is possible for Si powerdiodes to sustain dynamic avalanche at very high powerdensities (>1MW/cm2) during reverse recovery. It is proposed thatthese diodes eventually fail as a result of impact ionizationat the diode nn+junction, which according to device simulations,results in current filamentation and an excessive localizedheating. No temperature dependence was found for the failurelimit and similar results were obtained for diodes with andwithout carrier lifetime control. The high failure limitmeasured with the optical technique correlates with a very gooddynamic ruggedness in conventional electrical reverse recoverymeasurements. Device simulations indicate that a deep n+profile may improve the diode failure limit.

    A low failure limit close to the onset of dynamic avalanchewas found for another Si power diode, which had a structuredp-zone with a lowly doped p profile extending to the metalcontact in a fraction of the active area. A suggested failurecause for this diode is punch-through of a high electric fieldthrough the p region to the metal contact, an effect which maybe enhanced by an inhomogeneous current resulting from dynamicavalanche.

    Some of the investigated 4H-SiC p+nn+diodes showed no dynamic reduction of thebreakdown voltage in reverse recovery measurements. The highpredicted onset level of dynamic avalanche for 4H-SiC couldhowever not be reached, since breakdown at the junction edgelimited the static breakdown voltage to between 800 and 1200 V.A similarly processed test diode showed a clear avalanche inthe bulk during reverse recovery at 300 V, even though thediodes could block more than 2 kV in static measurements. Basedon device simulation, it is proposed that this largediscrepancy between static and dynamic breakdown voltage iscaused by temporary trapping of holes in deep donor levelswhich enhance the space charge and thus the peak electricfield. Deep hole traps were found in the vicinity of the pnjunction by DLTS measurements.

    Keywords:dynamic avalanche, power diode, failure limit,dynamic ruggedness, avalanche injection, silicon, siliconcarbide, impact ionization

  • 16.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Hillkirk, Leonardo
    KTH, Superseded Departments, Electronics.
    Linnros, Jan
    KTH, Superseded Departments, Electronics.
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Dynamic avalanche in 3.3-kV Si power diodes1999In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 46, no 4, p. 781-786Article in journal (Refereed)
    Abstract [en]

    Measurements of the safe reverse recovery limit were performed for 3.3-kV Si power diodes using a novel optical experimental technique. In this experiment, influence of the junction termination is effectively eliminated by optical generation of a laterally-localized carrier plasma. The turn-off failures observed in measurements at two temperatures showed no temperature dependence and could not be reproduced in ordinary one-dimensional (1-D) or two-dimensional (2-D) device simulations. To simulate the stability of the current density toward current filamentation, two 1-D diodes with an area ratio 1:19 and a 10% difference in initial carrier plasma level, were simulated in parallel. This resulted in a strongly inhomogeneous current distribution, and a rapid reverse voltage fall resembling the measured turn-off failures. Inhomogeneous current distribution in these simulations appears as the current decay ceases due to impact ionization, in qualitative agreement with a current instability condition proposed by Wachutka [1].

  • 17.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Linnros, Jan
    KTH, Superseded Departments, Electronics.
    Ostling, Mikael
    KTH, Superseded Departments, Electronics.
    Avalanche injection in high voltage Si PiN diodes1997In: Physica scripta. T, ISSN 0281-1847, Vol. T69, p. 134-137Article in journal (Refereed)
    Abstract [en]

    An experimental technique using optical excitation by a YAG laser pulse for studying avalanche injection in power devices is demonstrated This technique enables the creation of high uniform excess carrier concentrations in an optically defined device volume, involving very little heating. A method for determining the onset of avalanche multiplication, by studying the time integral of the reverse recovery current, is proposed. A PiN diode is observed to turn off from avalanching at a dissipated power density of more than 200 kW/cm(2).

  • 18.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Linnros, Jan
    KTH, Superseded Departments, Electronics.
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Avalanche Injection in High Voltage Si P-i-N Diodes Measurements and Device Simulations1997In: ISPSD '97: Proceedings of the International Symposium on Power Semiconductor Devices and ICs, 1997, p. 125-Conference paper (Other academic)
  • 19.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Linnros, Jan
    KTH, Superseded Departments, Electronics.
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Reverse Recovery and Avalance Injection in High Voltage SiC PIN Diodes1998In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 264-268, p. 1041-Article in journal (Other academic)
  • 20.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Lutz, Josef
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Dynamic avalanche in Si power diodes and impact ionization at the nn(+) junction2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 3, p. 477-485Article in journal (Refereed)
    Abstract [en]

    The reverse recovery failure limit was measured with an optical technique for power diodes which sustain high levels of dynamic avalanche. Measurements and simulations indicate that these diodes withstand dynamic avalanche at the pn-junction and eventually fail as a result of a strongly inhomogeneous current distribution caused by the onset of impact ionisation at the diode nn(+) junction - a mechanism similar to the reverse bias second breakdown of bipolar transistors.

  • 21.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Åberg, Denny
    KTH, Superseded Departments, Electronics.
    Martinez, Antonio
    KTH, Superseded Departments, Electronics.
    Bergman, P
    Dynamic avalanche and trapped charge in 4H-SiC diodes2000In: SILICON CARBIDE AND RELATED MATERIALS: 1999 PTS, 1 & 2 / [ed] Carter CH; Devaty RP; Rohrer GS, 2000, Vol. 338-3, p. 1327-1330Chapter in book (Other academic)
    Abstract [en]

    A dynamically reduced breakdown voltage from more than 2 kV under static conditions to 300 V during reverse recovery was measured for 4H-SiC p(+)nn(+) diodes. Device simulation indicates that deep hole-trapping donors in the n-base, close the pn junction, could explain the dynamically reduced breakdown voltage. Hole traps situated 0.66 eV above the valence band were found in the diode n-base by DLTS measurements.

  • 22.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Lutz, Josef
    Stable dynamic avalanche in Si power diodes1999In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 74, no 21, p. 3170-3172Article in journal (Refereed)
    Abstract [en]

    A stable dynamic avalanche at a maximum power density of about 2.4 MW/cm(2) was measured in small areas of 3.3 kV Si power diodes, using an optical measurement technique, and very good dynamic ruggedness was verified in a conventional turn-off measurement. Device simulations of a diode with a shallow n(+) emitter indicate that impact ionization at the nn(+) junction can result in negative differential resistance (NDR) and current filamentation, whereas a deep n(+) emitter in the experimentally studied diode suppresses NDR. It is, therefore, proposed that the deep n(+) emitter is important for the stable dynamic avalanche.

  • 23.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Danielsson, Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Current gain of 4H-SiC bipolar transistors including the effect of interface states2005In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 483, p. 889-892Article in journal (Refereed)
    Abstract [en]

    The current gain (β) of 4H-SiC BJTs as function of collector current (I-C) has been investigated by DC and pulsed measurements and by device simulations. A measured monotonic increase of β with I-C agrees well with simulations using a constant distribution of interface states at the 4H-SiC/SiO2 interface along the etched side-wall of the base-emitter junction. Simulations using only bulk recombination, on the other hand, are in poor agreement with the measurements. The interface states degrade the simulated current gain by combined effects of localized recombination and trapped charge that influence the surface potential. Additionally, bandgap narrowing has a significant impact by reducing the peak current gain by about 50% in simulations.

  • 24.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Danielsson, Erik
    Liu, W.
    Zimmermann, U.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Measurements and simulations of self-heating and switching with 4H-SIC power BJTs2003In: IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), Cambridge, 2003, p. 375-378Conference paper (Refereed)
    Abstract [en]

    Transient measurements and device simulations were performed to investigate self-heating and switching with 4H-SiC BJTs. A current gain decrease was found during self-heating presumably due to reduced electron mobility with increasing temperature. Surface recombination increased the simulated maximum temperature but the current gain decrease during self-heating was similar as for bulk recombination. A fast switching of 0.5 A and 200 V was shown with a voltage rise-time of about 70 ns and fall-time of 50 ns. Turn-off measurements show a noticeable delay time before fall-off of the emitter current, indicating a significant amount of stored carriers in the base.

  • 25.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Danielsson, Erik
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schöner, Adolf
    Acreo AB, Stockholm .
    Geometrical effects in high current gain 1100-V 4H-SiC BJTs2005In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 26, no 10, p. 743-745Article in journal (Refereed)
    Abstract [en]

    This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain beta = 64 and a breakdown voltage of 1100 V. The high beta value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The BJTs show a clear emitter-size effect indicating that surface recombination has a significant influence on beta. A minimum distance of 2-3 mu m between the emitter edge and base contact implant was found adequate to avoid a substantial beta reduction.

  • 26.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Analysis of the base current and saturation voltage in 4H-SiC power BJTs2007In: 2007 European Conference On Power Electronics And Applications: Vols 1-10, 2007, p. 2744-2750Conference paper (Refereed)
    Abstract [en]

    Silicon carbide (SiC) power bipolar junction transistors are interesting competitors to Si IGBTs for 1200 V power electronics applications. Advantages of SiC BJTs are low collector-emitter saturation voltages, little stored charge and high temperature capability. In this work, SiC NPN power BJTs with common emitter current gains of 40 have been fabricated and characterized. Electrical measurements for BJTs with different emitter widths indicate that the current gain is limited by surface recombination. A low value of V-CESAT=0.9 V at J(C)=100 A/cm(2) was obtained for small and large area (3.4 mm(2)) BJTs and correlated with the formation of low-resistive ohmic contacts to the base. Large area BJTs were shown to operate with a current gain of 48 in pulsed mode at a collector current of 12 A corresponding to J(C)=360 A/cm(2).

  • 27.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schoner, A.
    Current gain dependence on emitter width in 4H-SiC BJTs2006In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 527-529, p. 1425-1428Article in journal (Refereed)
    Abstract [en]

    This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain beta = 64 and a breakdown voltage of 1100 V. The high beta value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The current gain of the BJTs increases with increasing emitter width indicating a significant influence of surface recombination. This "emitter-size" effect is in good agreement with device simulations including recombination in interface states at the etched termination of the base-emitter junction.

  • 28.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schöner, A.
    SiC power bipolar junction transistors: Modeling and improvement of the current gain2005In: 2005 European Conference on Power Electronics and Applications, Dresden, 2005, Vol. 2005, p. 1665888-Conference paper (Refereed)
    Abstract [en]

    Epitaxial silicon carbide bipolar junction transistors (BJTs) for power switching applications have been designed and fabricated with a maximum breakdown voltage of 1100 V. The BJTs have high common emitter current gains with maximum values exceeding 60, a result that is attributed to design optimization of the base and emitter layers and to a high material quality obtained by a continuous epitaxial growth. Device simulations of the current gain as function of collector current have been compared with measurements. The measurements show a clear emitter-size effect that is in good agreement with simulations including surface recombination in interface states at the etched termination of the base-emitter junction. Simulations indicate an optimum emitter doping around 1-1019 cm-3 in agreement with typical state-of-the-art BJTs.

  • 29.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Schöner, Adolf
    High current gain silicon carbide bipolar power transistors2006In: Proceedings of the 18th International Symposium on Power Semiconductor Devices and ICs, 2006, p. 141-144Conference paper (Refereed)
    Abstract [en]

    Silicon carbide NPN bipolar junction transistors were fabricated and a current gain exceeding 60 was obtained for a BJT with a breakdown voltage BV(CEO)=1100 V. A reduction of the current gain was observed after contact annealing at 950 degrees C and this was attributed to degradation of the oxide passivation. Device simulations with varying emitter doping resulted in a maximum current gain for an emitter doping around 1(.)10(19) cm(-3). Resistive turn-off measurements were performed and a minimum collector-emitter voltage (V(CE)) rise-time of 40 ns was found. The VCE rise-time showed a clear dependence on the on-state base current thus indicating a significant stored charge.

  • 30.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Lutz, J.
    Silber, D.
    On the destruction limit of Si power diodes during reverse recovery with dynamic avalanche2003In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 50, no 2, p. 486-493Article in journal (Refereed)
    Abstract [en]

    The reverse recovery destruction limit of 3.3 kV fast recovery diodes was investigated by measurements and device simulations. Based on a good agreement between the measured destruction limit and current filamentation in simulations, it is proposed that the destruction is triggered by the onset of impact ionization at the nn(+) junction. The proposed destruction mode has large similarities with previously described second breakdown at the static breakdown voltage. An approximate analytical model which was derived indicate that avalanche at the nn(+) junction should become unstable with a time constant on the order of nanoseconds, whereas dynamic avalanche at the pn junction should be stable. Simulations and measurements give at hand that the reverse recovery safe operating area depends on the n-base width. An approximate equation is proposed to determine the minimum n-base width required for a nondestructive reverse recovery with dynamic avalanche as function of the reverse peak voltage.

  • 31.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zaring, C.
    Konstantinov, A. O.
    Nawaz, M.
    Svedberg, J-O
    Gumaelius, K.
    Keri, I.
    Lindgren, A.
    Hammarlund, B.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Reimark, M.
    2.2 kV SiC BJTs with low V(CESAT) fast switching and short-circuit capability2010In: SILICON CARBIDE AND RELATED MATERIALS 2009, PTS 1 AND 2 / [ed] Bauer, AJ; Friedrichs, P; Krieger, M; Pensl, G; Rupp, R; Seyller, T, 2010, p. 1033-1036Conference paper (Refereed)
    Abstract [en]

    This paper reports large active area (15 mm(2)) 4H-SiC BJTS with a low V(CESAT)=0.6 V at 1(C)=20 A (J(C)=133 A/cm(2)) and an open-base breakdown voltage BV(CEO)=2.3 kV at T=25 degrees C. The corresponding room temperature specific on-resistance R(SP.ON)=4.5 m Omega cm(2) is to the authors knowledge the lowest reported value for a large area SiC BJT blocking more than 2 kV. The onstate and blocking characteristics were analyzed by device simulation and found to be in good agreement with measurements. Fast switching with VcE rise- and fall-times in the range of 20-30 ns was demonstrated for a 6 A 1200 V rated SiC BJT. It was concluded that high dynamic base currents are essential for fast switching to charge the BJT parasitic base-collector capacitance. In addition, 10 mu s short-circuit capability with V(CE)=800 V was shown for the 1200 V BJT.

  • 32.
    Eriksson, K. G. Peter
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    A Simple and Reliable Electrical Method for Measuring the Junction Temperature and Thermal Resistance of 4H-SiC Power Bipolar Junction Transistors2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 600-603, p. 1171-1174Article in journal (Refereed)
    Abstract [en]

    To determine the maximum allowed power dissipation in a power transistor, it is important to determine the relationship between junction temperature and power dissipation. This work presents a new method for measuring the junction temperature in a SiC bipolar junction transistor (BJT) that is self-heated during DC forward conduction. The method also enables extraction of the thermal resistance between junction and ambient by measurements of the junction temperature as function of DC power dissipation. The basic principle of the method is to determine the temperature dependent IN characteristics of the transistor under pulsed conditions with negligible self-heating, and compare these results with DC measurements with self-heating. Consistent results were obtained from two independent temperature measurements using the temperature dependence of the current gain, and the temperature dependence of the base-emitter IN characteristics, respectively.

  • 33.
    Farese, Luca
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Experimental Study of Degradation in 4H-SiC BJTs by Means of Electrical Characterization and Electroluminescence2010In: SILICON CARBIDE AND RELATED MATERIALS 2009 / [ed] Bauer AJ; Friedrichs P; Krieger M; Pensl G; Rupp R; Seyller T, 2010, Vol. 645-648, p. 1037-1040Conference paper (Refereed)
    Abstract [en]

    SiC power bipolar junction transistors (BJTs), for high voltage applications, have been studied under elevated temperature and electrical stress conditions. Electroluminescence has been used to capture effects of defect motion and growth, in complete transistor structures, leading to a quantifiable degradation in the electrical performance. The observed degradation of current gain (beta) and on-resistance (RON) was relatively modest and saturated after a limited stress time, resulting in stable device performance. The characteristic wavelength (450 nm) of the electroluminescence, or light emission, in the visual and near infrared (NIR) range, coupled to the shape of the defects indicates that basal plane dislocations and stacking faults are involved.

  • 34.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Esteve, Romain
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schöner, Adolf
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Han, Jisheng
    Dimitrijev, Sima
    Reshanov, Sergey A.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Surface-passivation effects on the performance of 4H-SiC BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, p. 259-265Article in journal (Refereed)
    Abstract [en]

    In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

  • 35.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 11, p. 1170-1172Article in journal (Refereed)
    Abstract [en]

    Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of similar to 1.2 x 10(13) cm(-2) in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single-and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.

  • 36.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Voltage, Low On-resistance 4H-SiC BJTs with Improved Junction Termination Extension2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 706-709Article in journal (Refereed)
    Abstract [en]

    In this work, implantation-free 4H-SiC bipolar transistors with two-zone etched-JTE and improved surface passivation are fabricated. This design provides a stable open-base breakdown voltage of 2.8 kV which is about 75% of the parallel plane breakdown voltage. The small area devices shows a maximum dc current gain of 55 at Ic=0.33 A (J(C)=825 A/cm(2)) and V-CESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4 m Omega.cm(2). The large area device shows a maximum dc current gain of 52 at Ic = 9.36 A (J(C)=312 A/cm(2)) and V-CESAT = 1.14 V at Ic = 5 A that corresponds to an ON-resistance of 6.8 m Omega.cm(2). Also these devices demonstrate a negative temperature coefficient of the current gain (beta=26 at 200 degrees C) and positive temperature coefficient of the ON-resistance (R-ON = 10.2 m Omega.cm(2)).

  • 37.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High current-gain implantation-free 4H-SiC Monolithic Darlington Transistor2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 2, p. 188-190Article in journal (Refereed)
    Abstract [en]

    An implantation-free 4H-SiC Darlington transistor with high current gain of 2900 ( JC= \970A/cm2) and VCE) = 6V) at room temperature is reported. The device demonstrates a record maximum current gain of 640 at 200 hC, offering an attractive solution for high-temperature applications. The monolithic Darlington device exhibits an open-base breakdown voltage of 1 kV that is less than the optimum bulk breakdown due to isolation trench between the driver and the output bipolar junction transistor. On the same wafer, a monolithic Darlington pair with a nonisolated base layer was also fabricated. At room temperature, this device shows a maximum current gain of 1000 and an open-base breakdown voltage of 2.8 kV, which is 75% of the parallel-plane breakdown voltage

  • 38.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedotto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Shayestehaminzadeh, Seyedmohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of crystal orientation on the current gain in 4H-SiC BJTs2010In: Device Research Conference - Conference Digest, DRC, 2010, p. 131-132Conference paper (Refereed)
    Abstract [en]

    The 4H-SiC bipolar junction transistors (BJT) are considered as efficient high power switching devices due to the ability of obtaining very low specific on-resistance compared to FET based devices. However, one drawback with the present high voltage BJTs is the relatively low current gain. To reduce the power required by the drive circuit, it is important to increase the common-emitter current gain ( #x03B2;). 4H-SiC (0001) Si-face has become a favorable plane for vertical power BJTs with epitaxial layers that shows higher mobility along the c-axis and provides higher current gain. Furthermore, important progress on improving the current gain focused on the quality of surface passivation at the SiC/SiO2 interface has been reported during previous years. Higher quality of passivation can provide less interface traps and thereby minimizes the surface recombination current. Conventionally, vertical 4H-SiC BJTs are fabricated along the [11_00] direction on (0001) Si-face. However due to anisotropic properties of 4H-SiC, different orientations on Si-face can also affect the base current of the BJT through variation of mobility and interface traps density distribution along each direction. In this work, single-finger small area BJTs are fabricated on (0001) Si-face along [12_10], [011_0], [112_0] and [11_00] directions. This design can provide various orientations of BJTs that corresponds to an angular range between 0 to 180 degrees relative to conventional [11_00] direction. The goal was to find a correlation between different crystallographic orientation, mobility and interface traps density distribution through transistor characteristics and finally comparison with simulation. Fig.1 shows a cross section and top view of fabricated BJTs. The n+ emitter epi-layer is 1.35 #x03BC;m nitrogen doped to 6 #x00D7;1018 cm-3 and capped by 200-nm-thick 2 #x00D7;1019 cm-3 layer. The base epi-layer is 650 nm Al-d- - oped with concentration of 4.3 #x00D7;1017 cm-3. The drift n- epilayer is 20 #x03BC;m thick and doped to 6 #x00D7;1015 cm-3. Inductively coupled plasma (ICP) etching with an oxide mask was used to form emitter and base mesas. Fig.2 is a comparison of the maximum current gain with different orientations normalized to the maximum current gain along [11_00] before surface passivation and contact metallization. The results indicate that the maximum current gain is orientation-dependent and has a maximum for BJTs with the emitter edge aligned to the [112_0] direction. The variation effect of planar mobility and interface traps concentration on the current gain is simulated based on the previous work and is illustrated in Fig.3. The simulation shows that interface oxide charges has more influence on the current gain compared to the mobility and higher current gain is attributed to lower oxide interface charges. The orientation dependence of the transistor parameters such as maximum current gain after passivation and the base resistance will be evaluated and compared with simulation.

  • 39.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedotto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Shayestehaminzadeh, Seyedmohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Removal of Crystal Orientation Effects on the Current Gain of 4H-SiC BJTs Using Surface Passivation2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 5, p. 596-598Article in journal (Refereed)
    Abstract [en]

    In this letter, the dependence of current gain and base resistance on crystal orientations for single-finger 4H-SiC bipolar junction transistors ( BJTs) is analyzed. Statistical evaluation techniques were also applied to study the effect of surface passivation and mobility on the performance of the devices. It is shown that BJTs with an emitter edge aligned to the [1 (2) under bar 10] direction shows a lower current gain before surface passivation and higher base resistance after contact formation compared with other investigated crystal directions. However, the devices show a similar current gain independent of the crystal orientation after surface passivation.

  • 40.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Esteve, R.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schoner, A.
    Han, J.
    Dimitrijev, S.
    Reshanov, S. A.
    Zetterling, Carl -Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Experimental evaluation of different passivation layers on the performance of 3kV 4H-SiC BJTs2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, no Part 1-2, p. 661-664Article in journal (Refereed)
    Abstract [en]

    In this work, the electrical performance in terms of maximum current gain, ON-resistance and blocking capability has been compared for 4H-SiC BJTs passivated with different surface passivation layers. Variation in BJT performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O ambient at 1100 degrees C during 3 hours. Variations in breakdown voltage for different surface passivations were also found, and this is attributed to differences in fixed oxide charge that can affect the optimum dose of the high voltage JTE termination.

  • 41.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Voltage (2.8 kV) Implantation-free 4H-SiC BJTs with Long-TermStability of the Current Gain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 8, p. 2665-2669Article in journal (Refereed)
    Abstract [en]

    In this work, implantation-free 4H-SiC BJTs with high breakdown of 2800 V have been fabricated utilizing acontrolled two-step etched junction termination extension (JTE). The small area devices show a maximum dc current gainof 55 at Ic=0.33 A (JC=825 A/cm2) and VCESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4mΩ·cm2. The large area device have a maximum dc current gain of 52 at Ic = 9.36 A (JC=289 A/cm2) and VCESAT = 1.14 Vat Ic = 5 A that corresponds to an ON-resistance of 6.8 mΩ·cm2. Also these devices demonstrate a negative temperaturecoefficient of the current gain (β=26 at 200°C) and a positive temperature coefficient of the ON-resistance (RON = 10.2mΩ·cm2 at 200°C). The small area BJT shows no bipolar degradation and low current gain degradation after 150 Hrs stressof the base-emitter diode with current level of 0.2A (JE=500 A/cm2). Also, large area BJT shows a VCE fall time of 18 nsduring turn-on and a VCE rise time of 10 ns during turn-off for 400 V switching characteristics.

  • 42.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl - Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Implantation-Free Low on-resistance 4H-SiC BJTs with Common-Emitter Current Gain of 50 and High Blocking Capability2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 615-617, p. 833-836Article in journal (Refereed)
    Abstract [en]

    In this study, high voltage blocking (2.7 kV) implantation-free SiC Bipolar Junction Transistors with low on-state resistance (12 m Omega-cm(2)) and high common-emitter current gain of 50 have been fabricated. A graded base doping was implemented to provide a low resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high temperature dopant activation annealing and for avoiding generation of life-time killing defects that reduces the current gain. Also in this process large area transistors showed common-emitter current gain of 38 and open-base breakdown voltage of 2 kV.

  • 43.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of 2700-v 12-m Omega center dot cm(2) non ion-implanted 4H-SiC BJTs with common-emitter current gain of 502008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 10, p. 1135-1137Article in journal (Refereed)
    Abstract [en]

    High-voltage blocking (2.7-kV) implantation-free SiC bipolar junction transistors with low ON-state resistance (12 m Omega . cm(2)) and high common-emitter current gain of 50 have been fabricated. A graded-base doping was implemented to provide a low-resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high-temperature dopant activation annealing and for avoiding generation of lifetime-killing defects that reduce the current gain.

  • 44.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ostling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simultaneous study of nickel based ohmic contacts to Si-face and C-face of n-type silicon carbide2007In: 2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2, NEW YORK: IEEE , 2007, p. 311-311Conference paper (Refereed)
  • 45.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Backside Nickel Based Ohmic Contacts to n-type Silicon Carbide2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 600-603, p. 635-638Article in journal (Refereed)
    Abstract [en]

    This work focuses on Ni ohmic contacts to the C-face (backside) of n-type 4H-SiC substrates. Low-resistive ohmic contacts to the wafer backside are important especially for vertical power devices. Ni contacts were deposited using E-beam evaporation and annealed at different temperatures (700-1050 degrees C) in RTP to obtain optimum conditions for forming low resistive ohmic contacts. Our results indicate that 1 min annealing at temperatures between 950 and 1000 degrees C provides high quality ohmic contacts with a contact resistivity of 2.3x10(-5) Omega cm(2). Also our XRD results show that different Ni silicide phases appear in this annealing temperature range.

  • 46.
    Hallén, Anders
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Nawaz, Muhammad
    Zaring, Carina
    Usman, Muhammad
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Low-Temperature Annealing of Radiation-Induced Degradation in 4H-SiC Bipolar Junction Transistors2010In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 31, no 7, p. 707-709Article in journal (Refereed)
    Abstract [en]

    Radiation hardness is tested for 4H-SiC n-p-n bipolar junction transistors designed for 1200-V breakdown voltage by implanting MeV protons and carbon ions at different doses and energies. The current gain is found to be a very sensitive parameter, and a fluence as low as 1 x 107 cm(-2) of 10 MeV C-12 can be clearly detected in the forward-output characteristics, I-C(V-CE). At this low dose, no influence of ion radiation is seen in the open-collector characteristics, I-B(V-EB), or the reverse bias leakage and breakdown properties. Moreover, by annealing the implanted devices at 420 degrees C for 30 min, a complete recovery of the electrical characteristics is accomplished.

  • 47. Konstantinov, A.
    et al.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zaring, C.
    Keri, I.
    Svedberg, J. -O
    Gumaelius, K.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Reimark, M.
    Operation of Silicon Carbide BJTs Free from Bipolar Degradation2010In: SILICON CARBIDE AND RELATED MATERIALS 2009, PTS 1 AND 2 / [ed] Bauer, AJ; Friedrichs, P; Krieger, M; Pensl, G; Rupp, R; Seyller, T, 2010, p. 1057-1060Conference paper (Refereed)
    Abstract [en]

    The mechanisms of bipolar degradation in silicon carbide BJTs are investigated and identified. Bipolar degradation occurs as result of stacking fault (SF) growth within the low-doped collector region. A stacking fault blocks vertical current transport through the collector, driving the defective region into saturation. This results in considerable drop of emitter current gain if the BJT is run at a reasonably low collector-emitter bias. The base region does not play any significant role in bipolar degradation. Long-term stress tests have shown full stability of large-area high-power BJTs under minority carrier injection conditions provided the devices are fabricated using low Basal Plane Dislocation (BPD) material. However, an approximately 20% current gain compression is observed for the first 30-60 hours of burn-in under common emitter operation, which is related to instability of surface recombination in the passive base region.

  • 48. Koo, S. -M
    et al.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Forsberg, U.
    Janzen, E.
    Simulation and Measurement of Switching Characteristics of 4H-SiC Buried-Gate JFETs2003In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 433-436, p. 773-776Article in journal (Refereed)
    Abstract [en]

    Buried-gate junction field-effect transistors (JFETs) have been fabricated in 4H polytype silicon carbide (SiC). The dynamic switching characteristics of the JFETs in a circuit with inductive load have been characterized. The drain voltage rise/fall time of ∌30 ns and 25 ns have been observed for turn-off and turn-on, respectively. The results have been compared to numerical mixed-mode circuit simulations with finite element structures.

  • 49.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bipolar Integrated OR-NOR Gate in 4H-SiC2011In: Proceedings of International Conference on Silicon Carbibe and Related Materials 2011, 2011Conference paper (Refereed)
  • 50.
    Lanni, Luigia
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ghandi, Reza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Measurements and simulations of lateral PNP transistors in a SiC NPN BJT technology for high temperature integrated circuits2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 758-761Article in journal (Refereed)
    Abstract [en]

    In this work, a 4H-SiC lateral PNP transistor fabricated in a high voltage NPN technology has been simulated and characterized. The possibility of fabricating a lateral PNP with a current gain larger than 1 has been investigated. Device and circuit level solutions have been performed.

12 1 - 50 of 71
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